– 1 – csce 513 fall 2015 lec08 memory hierarchy iv topics pipelining review load-use hazard...
TRANSCRIPT
– 1 – CSCE 513 Fall 2015
Lec08Memory Hierarchy IV
Lec08Memory Hierarchy IV
Topics Topics Pipelining Review
Load-Use Hazard Memory Hierarchy Review
Terminology reviewBasic Equations6 Basic Optimizations
Memory Hierarchy – Chapter 2
Readings: Appendix B, Chapter 2Readings: Appendix B, Chapter 2September 28, 2015
CSCE 513 Computer Architecture
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AMAT EquationsAMAT Equations
Terminology Terminology (abbreviations)(abbreviations)
•AMATAMAT
•HT – HitTimeHT – HitTime
•MR miss RateMR miss Rate
•MP miss PenaltyMP miss Penalty
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AMAT – weighted average AMAT – weighted average
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AMAT – weighted average (continued)AMAT – weighted average (continued)
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2.2 - 10 Advanced Cache Optimizations2.2 - 10 Advanced Cache Optimizations
Five CategoriesFive Categories
1.1.Reducing Hit Time-Small and simple first-level caches and way-Reducing Hit Time-Small and simple first-level caches and way-prediction. Both techniques also generally decrease power prediction. Both techniques also generally decrease power consumption. consumption.
2.2. Increasing cache bandwidth— Pipelined caches, multibanked Increasing cache bandwidth— Pipelined caches, multibanked caches, and nonblocking caches. These techniques have varying caches, and nonblocking caches. These techniques have varying impacts on power consumption. impacts on power consumption.
3.3.Reducing the miss penalty— Critical word first and merging write Reducing the miss penalty— Critical word first and merging write buffers. These optimizations have little impact on power. buffers. These optimizations have little impact on power.
4.4.Reducing the miss rate— Compiler optimizationsReducing the miss rate— Compiler optimizations
5.5.Reducing the miss penalty or miss rate via parallelism— Reducing the miss penalty or miss rate via parallelism— Hardware prefetching and compiler prefetching.Hardware prefetching and compiler prefetching.
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Way PredictionWay Prediction
To improve hit time, predict the way to pre-set To improve hit time, predict the way to pre-set muxmux Mis-prediction gives longer hit time Prediction accuracy
> 90% for two-way> 80% for four-wayI-cache has better accuracy than D-cache
First used on MIPS R10000 in mid-90s Used on ARM Cortex-A8
Extend to predict block as wellExtend to predict block as well “Way selection” Increases mis-prediction penalty
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Pipelining CachePipelining Cache
Pipeline cache access to improve bandwidthPipeline cache access to improve bandwidth Examples:
Pentium: 1 cyclePentium Pro – Pentium III: 2 cyclesPentium 4 – Core i7: 4 cycles
Increases branch mis-prediction penaltyIncreases branch mis-prediction penalty
Makes it easier to increase associativityMakes it easier to increase associativity
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Nonblocking CachesNonblocking CachesAllow hits before Allow hits before
previous misses previous misses completecomplete “Hit under miss” “Hit under multiple
miss”
L2 must support thisL2 must support this
In general, In general, processors can processors can hide L1 miss hide L1 miss penalty but not L2 penalty but not L2 miss penaltymiss penalty
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– 9 – CSCE 513 Fall 2015Copyright © 2012, Elsevier Inc. All rights reserved.
Multibanked CachesMultibanked Caches
Organize cache as independent banks to Organize cache as independent banks to support simultaneous accesssupport simultaneous access ARM Cortex-A8 supports 1-4 banks for L2 Intel i7 supports 4 banks for L1 and 8 banks for
L2
Interleave banks according to block addressInterleave banks according to block address
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Critical Word First, Early RestartCritical Word First, Early Restart
Critical word firstCritical word first Request missed word from memory first Send it to the processor as soon as it arrives
Early restartEarly restart Request words in normal order Send missed work to the processor as soon as
it arrives
Effectiveness of these strategies depends Effectiveness of these strategies depends on block size and likelihood of another on block size and likelihood of another access to the portion of the block that has access to the portion of the block that has not yet been fetchednot yet been fetched
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Merging Write BufferMerging Write BufferWhen storing to a block that is already pending in When storing to a block that is already pending in
the write buffer, update write bufferthe write buffer, update write buffer
Reduces stalls due to full write bufferReduces stalls due to full write buffer
Do not apply to I/O addressesDo not apply to I/O addresses
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No write buffering
Write buffering
– 12 – CSCE 513 Fall 2015Copyright © 2012, Elsevier Inc. All rights reserved.
Compiler OptimizationsCompiler Optimizations
Loop InterchangeLoop Interchange Swap nested loops to access memory in
sequential order
BlockingBlocking Instead of accessing entire rows or columns,
subdivide matrices into blocks Requires more memory accesses but improves
locality of accesses
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Hardware PrefetchingHardware Prefetching
Fetch two blocks on miss (include next Fetch two blocks on miss (include next sequential block)sequential block)
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Pentium 4 Pre-fetching
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Compiler PrefetchingCompiler PrefetchingInsert prefetch instructions before data is Insert prefetch instructions before data is
neededneeded
Non-faulting: prefetch doesn’t cause Non-faulting: prefetch doesn’t cause exceptionsexceptions
Register prefetchRegister prefetch Loads data into register
Cache prefetchCache prefetch Loads data into cache
Combine with loop unrolling and software Combine with loop unrolling and software pipeliningpipelining
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SummarySummary Ad
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Memory TechnologyMemory Technology
Performance metricsPerformance metrics Latency is concern of cache Bandwidth is concern of multiprocessors and
I/O Access time
Time between read request and when desired word arrives
Cycle timeMinimum time between unrelated requests to
memory
DRAM used for main memory, SRAM used DRAM used for main memory, SRAM used for cachefor cache
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– 17 – CSCE 513 Fall 2015Copyright © 2012, Elsevier Inc. All rights reserved.
Memory TechnologyMemory Technology
SRAMSRAM Requires low power to retain bit Requires 6 transistors/bit
DRAMDRAM Must be re-written after being read Must also be periodically refeshed
Every ~ 8 msEach row can be refreshed simultaneously
One transistor/bit Address lines are multiplexed:
Upper half of address: row access strobe (RAS)Lower half of address: column access strobe (CAS)
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– 18 – CSCE 513 Fall 2015Copyright © 2012, Elsevier Inc. All rights reserved.
Memory TechnologyMemory TechnologyAmdahl:Amdahl:
Memory capacity should grow linearly with processor speed
Unfortunately, memory capacity and speed has not kept pace with processors
Some optimizations:Some optimizations: Multiple accesses to same row Synchronous DRAM
Added clock to DRAM interfaceBurst mode with critical word first
Wider interfaces Double data rate (DDR) Multiple banks on each DRAM device
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Memory OptimizationsMemory OptimizationsM
emo
ry Tech
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y
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Memory OptimizationsMemory OptimizationsM
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Memory OptimizationsMemory Optimizations
DDR:DDR: DDR2
Lower power (2.5 V -> 1.8 V)Higher clock rates (266 MHz, 333 MHz, 400 MHz)
DDR31.5 V800 MHz
DDR41-1.2 V1600 MHz
GDDR5 is graphics memory based on DDR3GDDR5 is graphics memory based on DDR3
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– 22 – CSCE 513 Fall 2015Copyright © 2012, Elsevier Inc. All rights reserved.
Memory OptimizationsMemory Optimizations
Graphics memory:Graphics memory: Achieve 2-5 X bandwidth per DRAM vs. DDR3
Wider interfaces (32 vs. 16 bit)Higher clock rate
» Possible because they are attached via soldering instead of socketted DIMM modules
Reducing power in SDRAMs:Reducing power in SDRAMs: Lower voltage Low power mode (ignores clock, continues to
refresh)
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Memory Power ConsumptionMemory Power ConsumptionM
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Flash MemoryFlash Memory
Type of EEPROMType of EEPROM
Must be erased (in blocks) before being Must be erased (in blocks) before being overwrittenoverwritten
Non volatileNon volatile
Limited number of write cyclesLimited number of write cycles
Cheaper than SDRAM, more expensive than Cheaper than SDRAM, more expensive than diskdisk
Slower than SRAM, faster than diskSlower than SRAM, faster than disk
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Understand ReadyBoost and whether it will Speed Up your SystemUnderstand ReadyBoost and whether it will Speed Up your SystemWindows 7 supports Windows ReadyBoost. Windows 7 supports Windows ReadyBoost.
• This feature uses external USB flash drives as a hard disk cache to improve disk read performance.
• Supported external storage types include USB thumb drives, SD cards, and CF cards.
• Since ReadyBoost will not provide a performance gain when the primary disk is an SSD, Windows 7 disables ReadyBoost when reading from an SSD drive.
External storage must meet the following requirements:External storage must meet the following requirements:• Capacity of at least 256 MB, with at least 64 kilobytes (KB) of
free space. The 4-GB limit of Windows Vista has been removed.
• At least a 2.5 MB/sec throughput for 4-KB random reads• At least a 1.75 MB/sec throughput for 1-MB random writes
http://technet.microsoft.com/en-us/magazine/ff356869.aspx
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Memory DependabilityMemory Dependability
Memory is susceptible to cosmic raysMemory is susceptible to cosmic rays
Soft errorsSoft errors: dynamic errors: dynamic errors Detected and fixed by error correcting codes
(ECC)
Hard errorsHard errors: permanent errors: permanent errors Use sparse rows to replace defective rows
Chipkill: a RAID-like error recovery Chipkill: a RAID-like error recovery techniquetechnique
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Solid State DrivesSolid State Drives
http://en.wikipedia.org/wiki/Solid-state_drive
http://www.tomshardware.com/charts/hard-drives-and-ssds,3.html
• Hard Drives 34 dimensions: eg Desktop performance• SSD -
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Windows Experience IndexWindows Experience Index
Control Panel\All Control Panel Items\Performance Control Panel\All Control Panel Items\Performance Information and ToolsInformation and Tools
Control Panel\All Control Panel Items\Performance Information and Tools