© 2000 morgan kaufman overheads for computers as components cpus: memory system mechanism...

© 2000 Morgan Kaufman

Overheads for Computers as Components

CPUs: Memory System Mechanism

Microprocessor clock rates are increasing

Memories are falling behind microprocessor clocks

Caches: Increase average performance of the memory system

Memory management: Perform address translation to provide a larger virtual memory space in a smaller physical memory



Cache: To speed up memory access time

CPUca

che

cont

roll

er

cache

mainmemory

data

data

address

data

address

Mediates between CPU and memory system (cache and main memory)

Holds copies of some of the contents of main memory



Cache operation

Many main memory locations are mapped onto one cache entry.

May have caches for: instructions; data; data + instructions (unified).

Memory access time is no longer deterministic.



Terms

Cache controller sends memory requests:

- If in cache read from cache - If not controller waits for value from

memory and forwards it to CPUCache hit: required location is in

cache.Cache miss: required location is

not in cache victim?



Memory system performance

h = cache hit probabilitytcache = cache access time,

tmain= main memory access time.Average memory access time:

tav = htcache + (1-h)tmain

~5ns

50-60 ns (DRAM)



Multiple levels of cache

CPU L1 cache L2 cache

May also be on-chip memory Off-chip memory:

Larger but slower



Multi-level cache access time

h1 = cache hit rate.

h2 = rate for miss on L1, hit on L2.Average memory access time:

tav = h1tL1 + h2tL2 + (1- h2-h1)tmain



Memory management units

Logical address vs physical address

Example- Rabbit 16 bit microprocessor: 64k logical address space (16 bit), 1Mb physical address space (20 bit)

MMU translates 16bit logical address to 20 bit physical address



Z180: 3 registers CBAR (common/bank address register , CBR common base register), BBR (bank base register)

Root memory

BIOS (Flash)

Extended memory

00000

FFFFF

0000

FFFF

comm bank

E000

2000

CBR

BBR

CBAR

Root code growsfrom here up

Root data growsfrom here down

Physical memory

Point to physical memory

Added to CBR/BBR



MMU

Memory management unit (MMU): Translates addresses between CPU and

Physical Memory (memory mapping)Early computers used MMU to

compensate for limited address space in instruction set

For modern CPUS’s MMU is used for “virtual addressing”



… Memory management units

Memory management unit (MMU) translates addresses:

CPUmain

memory

memorymanagement

unit

logicaladdress

physicaladdress

Multiple programs

SecondaryStorage for virtual memory

swappingdata

RAM address



Memory management tasks

Allows programs to move in physical memory during execution.

One can change physical program location by changing MMU’s tables No data/code change

Allows virtual memory: memory images kept in secondary

storage; images returned to main memory on

demand during execution.



Address translation

Requires some sort of register/table to allow arbitrary mappings of logical to physical addresses.

Two basic schemes: Segmented: large, arbitrary sized region of

memory Program fragmentation: Program scattered

around physical memory Paged: small equally sized regions

Segmentation and paging can be combined (x86): Segmented, paged scheme.



Segments and pages

memory

segment 1

segment 2

page 1page 2

Uniform size: Simplifies hardware

Specified by: Start Address + Size

Physical memory



Segment address translation

segment base address logical address

rangecheck

physical address

+

rangeerror

segment lower boundsegment upper bound

Currently active segment

Extracted from aninstruction



Page address translation Pages are small: 512-4k

page number offset

page offset

page i base

concatenate

Logical address

Physical address

© 2000 morgan kaufman overheads for computers as components cpus: memory system mechanism...

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