© 2005 hanback corporation · thumb: 16 bit instructions a subset of the 32-bit arm® instructions...

© 2005 HANBACK Corporation

Guide to the SoC System Design

HANBACK Co., Ltd.Cha Jong In


2

Agenda

SOC (System-On-Chip) ConceptSOC Design & Development EnvironmentARM Architecture & AMBA BusALTERA Embedded Device ExcaliburExcalibur Design VerificationHANBACK SOC Platform


3

Typical System Today

Backplane

Optical/Analog

ProcessorProcessor

SRAMSRAM

Others

SRAMSRAMASSP

ASSP

DSPBus

Bus

Bus

Bus

Flas

h

DR

AM

DR

AM

DR

AM

PLD

PLD

DSP ASSP ASSPPMD

PMD

PMD


4

SOPC Vision

Backplane

Optical/Analog

Flas

h

DR

AM

DR

AM

DR

AM

PMD

PMD

PMD


5

What is SOC?

SOC = System On a ChipA generic SOC– At least one microprocessor, microcontroller, or DSP core

with its Memory subsystem– Peripheral to interface with external system– Accelerating function units/data transformation block– Analog/mixed signal/RF block


6

Advantage

Save Board SpaceLow Production CostHigh and Stable PerformanceFast Time-to-MarketLow Power ConsumptionDesign Reuse Use IP


7

Challenge

Market to address: What to designHow to verify the design(functionality)How to maintain consistency through the whole design procedure(EDA tools)How to integrate various process technologies(analog, DRAM, etc)How to deal with many different players.(foundry, EDA vendor, IP vendor, system house, software/firmware/RTOS vendor, test/packaging house,..)How to reduce TTM(Time-to-market)


8

SoC vs. ASIC

Soc is a mixture of heterogeneous technologyDesign ReuseLow Power DesignDesign/Verification MethodologyEmbedded Software


9

Agenda



10

Design Flow

C Header files

Peripheral Drivers

Quartus II SoftwareIndustry-StandardCompiler/Linker/

Relocator

Excalibur Device

JTAGTrace

User Code

Libraries

RTOS

Executable

Configure Embedded Stripe

Generate

Hardware Design Software

Makeprogfile.exe

Debugger &Trace Analyzer

Verilog/VHDL filesUser-Defined PeripheralsIP Cores

Configuration

Bus Functional Models

Embedded Stripe Models

Logic Synthesis

DesignVerification

Exc_flash_programmer.exe

Quartus II MegaWizard

EDA or Quartus II

EDA or Quartus II

GCC or ADS ARM Compiler

Multi-ICE & ByteBlasterETM Analyzor

Insight DebuggerAXD Debugger

*.sbi

*.hex


11

Design Flow(cont.)

HardwareDesign Entry

Fitter

MakeProgFile

HDLTemplate

v. Or .vhdStripe

declaration

SystemBuild

Descriptor(.sbd)

.h

Intel.hex

.o

Library.hexout

SoftwareDesignentry

Software BuildEnvironment

Link andConvert

.edf

.sbi

.v or .vhdChip design

Synthesize

ExcaliburMegaWizard

Plug-in

.h, .c

.sof .pof

Hard

war

e de

sign

Softw

are

desig

n

MakeProgFile.exeExc_flash_programmer.exe

MegaWizard in Quartus II

Quartus II

EDA or Quartus II

…

MentorSynopsisSimplicity

ADS ARM C/C++Compiler

GCC ARM C/C++Compiler


12

Development Tool

ALTERA Quartus II– Supports Excalibur Processor

+ARM-Base, Nios II– Integrated Software Development Environment– Generate Combined Programming Files

+PLD Configuration plus Software CodeThird Party : ModelSim, Exemplar Logic,Simplify, Leonardospectrum, Precision, …Software Build Tool(C language compiler)– GNUPro Toolkit from Redhat(Included in SOPC Builder 2.7)– ADS(ARM Development Suite) from ARM

Debug Tools– Insight Debugger in GCC– AXD Debugger


13

Toolset Directory in Quartus II

Assignments > Settings … Menu Click

12


14

Software Build SettingsAssignments > Settings … Menu Click

Click


15

Software Build Settings

Click

C header file path


16


Click

Assembly reference path


17


Click


18

AXD Debugger with ByteBlasterProgram > ARM Development Suite v1.2 …Click

Tool > Configure Target


19

ByteBlaster SetupTools > Programmer Click

EXC_FLASH_PROGRAMMER Flash Program Utility


20

Program Download

Flash Program Utility in Quatur IIExc_flash_programmer.exe– Variable options are exist.– P : program– V : verify– G : start after program– A : erase– E<n> : EBI bus chip select– Ex) exc_flash_programmer –p *_flash.hex

exc_flash_programmer –p –v –g *_flash.hexexc_flash_programmer –p –v –g –e 0 *_flash.hexexc_flash_programmer –p –v –g –e 1 *_flash.hex


21

Agenda



22

Architecture Version

ARM{x}{y}{z}{T}{D}{M}{I}{E}{J}{F}{-S}– x : product family– y : MMU/MPU– z : cache– T : Thumb 16-bit support– D : JTAG Debug feature– M : High speed multiplier– I : Embedded-ICE macrocell– E : DSP Extended Instruction– J : Jazelle– F : VFP– S : synthesizable version


23

Architecture Version(cont.)

ARMv1– First ARM processor– 26-bit addressing– Ex) ARM1

ARMv2– 32-bit Multiplier– Support 32-bit Co-processor– Ex) ARM2

ARMv2a– On-chip cache– Support Swap Instruction– Co-processor 15(CP15) for cache management– Ex) ARM3


24


ARMv3– 32-bit addressing– Split cpsr & spsr register– Undefined instruction & abort processor mode are added– Provide MMU for virtual memory– Ex) ARM6 & ARM7DI

ARMv3M– Signed/unsigned multiply extend instruction– Ex) ARM7M

ARMv4– Signed/unsigned half-word & byte load-store instruction– System processor mode is added– Do not support 26-bit addressing any more– Ex) StrongARM


25


ARMv4T– Thumb Instruction set support– Ex) ARM7TDMI & ARM9T

ARMv5TE– Enhanced multiply instruction– Additional DSP instruction– More fast MAC (Multiply-Accumulator)– Ex) ARM9E & ARM10E

ARMv5TEJ– Java accelerator– Ex) ARM7EJ & ARM926EJ


26


ARMv6– Enhanced multiprocessor instruction– New multimedia instruction– Ex) ARM11


27

ARM Products feature

16X3216X328X328X32Multiplier

HavardHavardHavardVon NeumannBus architecture1.21.31.10.97MIPS/MHz

0.4mW/MHz(+cache)

0.5mW/MHz(+cache)

0.19mW/Mhz(+cache)

0.06mW/MhzmW/Mhz

33526015080Speed

8-stage6-stage5-stage3-stagePipeline

ARM11ARM10ARM9ARM7

a) 0.13 micronb) Drystone MIPS

a)

b)


28

ARM Processors

Yesv5TEYesYesCache&TCMMMU&MPUARM1026EJ-S

yesv6YesYes16K/16KMMuARM1136JF-SYesV6YesYesCache&TCMMMUARM1136J-S

Yesv5TEYesNoCache&TCMMMUARM1022EYesv5TEYesNo16K/16KMMUARM1020EYesv5TEYesNo32K/32KNoneARM966E-SYesv5TEYesNoTCMMPUARM946E-SNov4TYesNoTCMMPUARM940TYesv5TEJYesYesCache&TCMMMUARM926EJ-SNov4TYesNo8K/8KMMUARM922TNov4TYesNo16K/16KMMUARM920TNov4TYesNo8KMMUARM720TYesv5TEJYesYesNoneNoneARMEJ-SNov4TYesNoNoneNoneARM7TDMIEISAThumbJazelleCacheMMU/MPUCPU core a)

a) Enhanced Satuate multiply instruction

Excalibur Uses


29

StrongARM & Xscale

StrongARM– Developt with Digital Semiconductor– Intel has a ownership(License)– For low power dissipation PDA & application– Splitted D+I cache & 5-stage pipeline with havard bus

architecture– Thumb is not supported

Xscale– Is next version of StrongARM, owned Intel– Execute v5TE ARM instruction , and has a havard bus

architecture. Similar to StrongARM– Is now ~ing (Up to 1Ghz)


30

ARM922T Processor

Based on ARM922™ (ARM920™ Derivative) & Incorporating ARM9TDMI™High-Speed Cache (8-KB Instruction + 8-KB Data) Memory Management Unit (MMU) Facilitates Implementation of Real-Time Operating Systems (RTOSs)Advanced Built-In System Debugging Features– Debugging Module– Embedded Trace Module (ETM)

ARM Thumb Instruction Set Support200-MHz, 0.18-µ Process


31

ARM922T Internal Organization

ARM9TDMI Processor Core

(+ Embedded ICE Interface)

AMBA Bus

Interface

Data MMU

Instruction Cache (8KB)

Embedded Trace

Module

Data Cache (8KB)

Write BackPage Address

TAGRAM

Write Data

Buffer

JTAG AHB

C13IVA[31:0]

C13DVA[31:0]

IMVA[31:0]

DMVA[31:0]

ID[31:0]

DD[31:0]

Instruction MMU

IPA[31:0]

DPA[31:0]

WBPA[31:0]


32

Thumb: 16 bit instructions

A Subset of the 32-bit ARM® Instructions That Are Compressed Into 16-bits– Processor core executes both 16 and 32 bit instructions– Allows runtime inter-working between ARM and Thumb®

codeThumb Programs Typically– Are ~30% smaller than ARM programs– Are ~30% faster when accessing 16 bit memory– Consume less power– Require less external memory


33

What is AMBA?

Advanced Microcontroller Bus Architecture (AMBA)Is a specification that defines on chip communications standards for high performance embedded systems.

Developed by Arm Limited in conjunction with other partners with the goal to standardize the way the ARM bus was being used.

– November 1993 – First Spec called Embedded Module Bus (EMB)– September 1995 – AMBA Rev C –Added tri-state turnaround for all signals– April 1997 – AMBA Rev D – Minor changes to reset and arbitration scheme– May 1999 –AMBA Rev 2.0 – Added AHB and changed APB rising clock

edge scheme


34

The AMBA Spec

The AMBA specification describes the architecture, protocol, and interconnection schemes. – Three bus standards

+Advanced High-Performance Bus (AHB)+Advanced System Bus (ASB)+Advanced Peripheral Bus (APB)


35

Block Diagram of typical AMBA Bus

Excalibur uses AHB so we will focus on AHB


36

Advance High-Performance Bus (AHB)

High Performance– Non-tri-state Implementation– Single Cycle Bus Master Handover– Burst Transfers– Pipelined Operation

Multiple Bus Masters– Up to 16 Bus Masters

Split TransactionsWide Data Bus Configuration– Up to 1024 bit wide

Excalibur Uses a Multi-layered AHB system bus


37

AHB System Components

AHB Master– Initiates both read and write bus transactions– Generates address and control information for transaction

AHB Slave– Responds to transactions in it’s given address range– Signals back the status of transaction to initiating master

AHB Arbiter– Ensures that only one bus master is initiating a transaction– Arbitration scheme is defined by designer

AHB Decoder– Centralized Decoding Scheme– Decodes Address and provides chip enable signal for slaves


38

Bus Interconnection Diagram

Centralized Mux Bus Interconnection Scheme


39

AHB Master I/O

InputsSignal Source DescriptionHCLK Clock Source Bus clockHRESETn Reset Controller ResetHRDATA[31:0] Slave Read data busHREADY Slave Transfer doneHRESP[1:0] Slave Transfer responseHGRANTx Arbiter Bus grant

Outputs

Signal Destination DescriptionHBUSREQx Arbiter Bus requestHLOCKx Arbiter Locked transfersHTRANS[1:0] Arbiter/Slave Transfer typeHADDR[31:0] Arbiter/Slave/Decoder Address busHWRITE Slave Transfer directionHSIZE[2:0] Slave Transfer sizeHBURST[2:0] Arbiter/Slave Burst typeHPROT[3:0] Protection Unit Protection Control HWDATA[31:0] Slave Write data bus


40

AHB Slave I/O

Inputs

Signal Source DescriptionHCLK Clock Source Bus clockHRESETn Reset Controller ResetHTRANS[1:0] Master Transfer typeHSIZE[2:0] Master Transfer sizeHBURST[2:0] Master Burst typeHWRITE Master Transfer directionHREADY Slave Transfer doneHMASTLOCK Arbiter Locked transfersHADDR[31:0] Master Address busHWDATA[31:0] Master Write data busHSELx Decoder Chip SelectHMASTER[3:0] Arbiter Master Number

Outputs

Signal Destination DescriptionHRDATA[31:0] Master Read data busHREADY_out Master/slave Transfer doneHRESP[1:0] Master/Arbiter Transfer responseHSPLITx Arbiter Split completion req


41

AHB Arbiter I/O

Inputs

Signal Source DescriptionHCLK Clock Source Bus clockHRESETn Reset Controller ResetHTRANS[1:0] Master Transfer typeHRESP[1:0] Slave Transfer responseHSPLITx Slave Split completion reqHLOCKx Master Locked transfersHBURST[2:0] Master Burst typeHBURSREQx Master Bus requestHREADY Slave Transfer doneHADDR[31:0] Master Address bus

Outputs

Signal Destination DescriptionHMASTER[3:0] Slave Master NumberHGRANT Master Bus grantHMASTLOCK Arbiter Locked transfers


42

AHB Decoder I/O

Inputs

Signal Source DescriptionHADDR[31:0] Master Address bus

Outputs

Signal Destination DescriptionHSELx Slave Chip enable


43

AMBA Protocol Overview

Basic AHB transaction consist of two phases.– Before transaction can commence, AHB master must request the

bus by asserting HBUSREQx. The AHB master is granted the bus when the Arbiter send back HGRANTx and HREADY is high.

Address Phase– Master must drive address and control information on to the bus.– Slave must sample address and control information during this

phase.Data Phase– Slave will respond to the address and control information from

master.– Slave will sample data from master.– Master will sample slave’s response and data.– Master can drive the next address to during data phase.


44

Basic AHB Transaction Timing Diagram

AHB Transaction consist of address and data phase

Address Phase

A

Control A

Data Phase

Data A

Data A

HCLK

HADDR[31:0]

Control

HWDATA[31:0]

HREADY

HRDATA[31:0]


45

AHB Transaction With Wait States

Wait states can be inserted if slave is not ready to process the transaction– Wait states can only be introduced by slave– Slaves introduce wait states by driving HREADY low– Extends the data phase for transaction

Master is responsible for holding data stable for write operations during wait statesSlave is not required to present valid read data until HREADY is driven back high


46

AHB Transaction With Wait State

HREADY is used by slave to insert wait states

Address Phase

A

Control A

Data A

Data Phase

Data A

HCLK

HADDR[31:0]

Control

HWDATA[31:0]

HREADY

HRDATA[31:0]


47

Multiple AHB Transactions

AHB bus uses a pipelined implementation– Allows for faster throughput– A Transaction’s Data Phase can be overlap with the next

transaction’s Address Phase– Wait state will extend the data phase of the current

transaction and the address phase of the next transaction


48

Multiple AHB Transactions

Overlapping address and data with wait state for B transaction

HCLK

HADDR[31:0]

Control

HWDATA[31:0]

HREADY

HRDATA[31:0]

Address Phase A

A

Control A

Data A

B

Control B

Data A

Data Phase AAddress Phase B

C

Control C

Data B

Data B

Data Phase BAddress Phase C

Data C

Data C

Data Phase C


49

Other AHB Transactions

Burst transactions– Can be incremental and wrap burst of 4, 8, 16 beats

+Can do incremental of unspecified lengthSplit transactions– Used to separate the address and data phase of a transaction

+Slow access time peripherals Locked Transactions– Masters can indicates that the current transaction can’t be

interrupted+Prevents split from occurring


50

AHB Transaction Control SignalsMasters drive transaction control signals that determine how to process transactions during address phase.

– HWRITE – Transaction direction:+ High signifies a write+ Low signifies a read

– HTRANS[1:0] - Transaction type: + IDLE:Master is granted the bus but doesn’t have data to transfer+ BUSY:Master wait states. Used for Burst Transaction. + NONSEQ:Single transaction. Every transaction starts with Nonseq+ SEQ:Burst transaction. Each beat’s transaction type is Sequential

– HSIZE[2:0] -Transaction size: 8-bits to 1024-bits– HBURST[2:0] – Length and type of burst:

+ INCR and WRAP 4,8,16+ Unspecified INCR

– HPROT[3:0] – Additional info on bus access. Used by protection units


51

Slave Responses

Slaves drive responses to transactions during data phase.– HREADY – Used by slave to insert wait states:

+Low signifies not ready to process transaction+High signifies ready to process transaction

– HRESP[1:0] – Slaves response to transaction:+OKAY:Transaction is processing with no problems+ERROR:Transaction produce an Error+RETRY: Not able to process transaction at current time. Retry

later+SPLIT:Indicates that the Slave in the middle of a split transaction+ERROR, RETRY, and SPLIT require a minimum two clock cycle

response to flush pipeline of erroneous transactions.


52

Slave Responses

Slave issues two cycle error response to clear pipe

Transaction A

HCLK

HADDR[31:0]

HTRANS[1:0]

HWDATA[31:0]

HREADY

HRESP[1:0]

Address Phase A

A

NONSEQ

Data A

B

NONSEQ

OKAY

Data Phase AAddress Phase B

C

NONSEQ

ERROR

Data B

Data Phase BAddress Phase C

ERROR

IDLE

Address Phase D

OKAY

NONSEQ

D

Transaction ATransaction B Transaction ATransaction C Transaction B

Transaction B

Transaction C

Transaction C

Transaction D Transaction D


53

Arbitration

Arbiter grant access to the bus to the master which has the high priority, indicated by HGRANTx. – Master is granted the bus when HREADY and HGRANT are high.– Priority scheme is determined by designer


54

Other Aspects of AHB Protocol

Error responses from slaves– Only used to signify a transaction error

+ Writing to a register that is read only+ Writing or reading a address that is not actually in memory space

Early Burst Termination– Slaves have to monitor HTRANS during a burst.– Must have a way to recover from a IDLE or NONSEQ from master

Dummy Master– Every system must have a Dummy Master– Dummy Master that only generates IDLE cycles on bus– Granted when all masters SPLIT– Typically Master #0


55

Other Aspects of AHB ProtocolDefault Master– Granted the bus when no other master requires the bus– Generally the Default master is the master most like to require the

bus– Generates IDLE when not requesting the bus– Avoids two clock cycle arbitration period– Has immediate access to the bus

Default Slave– Should be selected slave when all other are not selected– Issues OKAY response to IDLE or BUSY transactions– Issues ERROR for SEQ and NONSEQ transactions– Purpose is to prevent bus deadlock

For additional AHB information download AMBA Specification:– http://www.arm.com


56

Summary

ARM architecture & ARM processor familyARM922T featureAbout AMBAAdvance High-performance BusAHB ComponentAMBA protocolBasic AHB TransactionMultiple AHB TransactionAHB Transaction Control SignalSlave Responses


57

Agenda



58

Introduction to Altera devices

An industry leader in programmable logic– Inventor of the EPLD in 1983

Programmable Logic Families– Excalibur™ Embedded Processor Solutions

+ARM®-Based, Nios II™– SRAM Based

+APEX™ II, APEX™ 20K, Mercury™, HardCopy™, ACEX™ 1K, FLEX 10K®, FLEX® 6000, FLEX 8000, Cyclone, Cyclone II, Stratix, Stratix GX, Stratix II

– EEPROM Based+MAX II, MAX® 3000, MAX 7000, MAX 9000, Classic™

Configuration Devices Software development systems: Quartus® II, MAX+PLUS® II


59

What’s New in Quartus II ?New Product Support– APEX™ II Family– FLEX 10KE Family– ACEX 1K Family

Improved Design Flow With LogicLock– Performance preservation– Incremental synthesis

Excalibur MegaWizard®

PowerFit™ Fitter Improvements– Multiple slack timing tables implemented

New Timing Assignments– Wildcard allowed & ability to apply multi-cycle to enables

PowerGauge™ Enhancements– Mercury, LVDS I/O, & ModelSim™ support

Toolnet Cross Probing with Synplicity 7.0


60

Features32 Bit RISC Processor– Up to 200 MHz ARM922T™

High Performance .18 µm 8LM TSMC ProcessAMBA™ Bus Architecture– Industry Standard Bus Architecture

Stripe Memory– Single Port and Dual Port

External Memory I/F– Embedded SDRAM/DDR SDRAM Controller (Dedicated Pin)– Flash/EEPROM/SRAM (Through EBI Bus)


61

Hard Processor PLD Architecture

PLL

Timer

UART

InterruptControllerWatchdog

Timer

JTAG

128 Kbytes SRAM64 Kbytes DPRAM



EmbeddedProcessorStripe

PLD

DPRAM

EPXA1

EPXA4

EPXA10

TraceModule

ARM922T

SRAM SRAM SRAM

DPRAM DPRAM

ExternalMemory

InterfacesProcessor & Interfaces

I-CACHE D-CACHEARM 8K Bytes 8K Bytes

LEs 4160ESB Bytes 6.5K

LEs 16400ESB Bytes 26K

LEs 38400ESB Bytes 40K


62

Feature EPXA1 EPXA4 EPXA10

Maximum System Gates 263,000 1,052,000 1,772,000

Typical Gates 100,000 400,000 1,000,000

LEs 4,160 16,640 38,400

Embedded System Blocks (ESBs) 26 104 160

Maximum RAM Bits 53,248 212,992 327,680

Maximum User I/O Pins 178 360 521

Single-Port SRAM 32 Kbytes 128 Kbytes 256 Kbytes

Dual-Port SRAM 16 Kbytes 64 Kbytes 128 Kbytes

Total Ram Bits (PLD + Stripe) 446,464 1,785,856 3,473,408

Device Summary

HBE-SOC-Entry II Platform


63

Excalibur Device Packages

Pins 484 672 1020 612 864

Pitch (mm) Plastic, 1.0 Plastic, 1.0 Plastic, 1.0 Plastic, 1.27 Plastic, 1.27

EPXA1 173 178 178

EPXA4 275 360 215 360

EPXA10 521 365

Migration Vertical Vertical Vertical Vertical

I/O FineLine BGA BGA

Size (mm) 23 27 33 35 45

N/A

HBE-SOC-Entry II Platform


64

PLD Area for Customer Design

ARM922TCore

Single-PortRAM

Dual-PortRAM

Die Picture

Stripe IP is placed physically

on the top of the APEX20KE PLD


65

Excalibur Stripe Components32 Bit RISC Processor AHB1 & AHB2 BusesPLL SupportMemory– Single Port– Dual Port– SDRAM Controller

Expansion Bus InterfacePeripherals– UART– Interrupt Controller– Watchdog Timer– Timer

Reset & Mode control


66

Excalibur Stripe Components

WatchdogTimer

PLL

AHB 1-2Bridge

Dual Port SRAM

SDRAMController

Single Port SRAM

32 Bit RISC Processor

Interrupt Controller

AHB1

AHB2

SDRAM

Embedded StripeSRAMFLASH

APEX 20KE

PLD - Stripe Bridge

PLDMaster

ConfigurationLogic Master

Reset Module Timer

PLD Slave

UARTBus

Expansion (EBI)

Stripe - PLD Bridge

ROM

PLD Slave

PLDModule

PLDModule

Excalibur Hard IP

External Devices

APEX Soft IP


67

Excalibur MegaWizard

Select ARM®-Based™ Excalibur™

– Easily create the desired stripe configuration


68

MegaWizard

Select family and device

Hold processor in reset?

Endianess

Reserve pins

Boot from FLASH?


69

Quartus II SymbolSchematic Instantiation


AHB in Excalibur


71

AMBA High Performance Bus (AHB)

AMBA - Advanced Micro-controller Bus Architecture Connects Embedded Stripe and PLD Devices 200MHz Maximum Clock Rate32 Bit Wide Pipelined Bus– Burst transfers - one cycle per data word– Non-tristate implementation

Multi-master With Distributed Address Decoding– Single-cycle bus master handover

Split Transactions Extensions– Needed to fully exploit bus bandwidth in a multi-master bus


72

AHB1 Bus

Processor Is the Sole MasterSupport for Locked TransfersUser Will Not Interface to This BusHighest Speed Bus Connection to Memory (200MHz)– SRAM– SDRAM– DDR RAM


73

AHB1 Bus

WatchdogTimer

PLL

AHB 1-2Bridge

Dual Port SRAM

SDRAMController

Single Port SRAM



AHB1

SDRAMEmbedded Stripe

SRAMFLASH

APEX 20KE

PLD - Stripe Bridge

PLDMaster


Reset Module Timer

PLD Slave

UARTBus

Expansion (EBI)

Stripe - PLD Bridge

ROM

PLD Slave

PLDModule

PLDModule

Excalibur Hard IP

External Devices

APEX Soft IP


74

AHB2 Bus

Connects Processor Standard Cell to the PLD Master and Slave Devices3 Bus Masters– AHB1-2 bridge– Configuration logic– PLD master interface

Multiple Slave DevicesSupports Split Transaction– Needed to fully exploit bus bandwidth

Operates at Half the Frequency of AHB1


75

AHB2 Bus

WatchdogTimer

PLL

AHB 1-2Bridge

Dual Port SRAM

SDRAMController

Single Port SRAM



AHB2

SDRAMEmbedded Stripe

SRAMFLASH

APEX 20KE

PLD - Stripe Bridge

PLDMaster


Reset Module Timer

PLD Slave

UARTBus

Expansion (EBI)

Stripe - PLD Bridge

ROM

PLD Slave

PLDModule

PLDModule

Excalibur Hard IP

External Devices

APEX Soft IP


76

MegaWizard

Select the AHB2 to PLD bridges

Select Interrupt sources

Select Trace/Debug


Registers & Memory Map


78

Registers

Registers Are Used Throughout the Stripe Components for Configuration and Status– Controlled by software and configuration logic

All Registers Are Located Within One 16 Kbyte Memory Region– The registers are spread throughout the stripe– The base address is 7FFFC000H at reset– Base address can be relocated at any time

Register Descriptions Identify Read/Write Capability– R = read access– R* = read access with possible side effects (clear interrupt)– W = write a 0 or 1– S = writes of 1 set bits, writes of 0 do nothing– C = writes of 1 clear bits, writes of 0 do nothing


79

Registers

Memory Map Control Registers

EN Setting this bit enables decoding of the rangeNP No Pre-FetchSIZE log2(region size) -1BASE Bits [31..14] of the base address

Address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 080H MMAP_REGISTERS BASE 0 1 EN90H MMAP_SRAM0 BASE SIZE 0 0 EN94H MMAP_SRAM1 BASE SIZE 0 0 ENA0H MMAP_DPSRAM0 BASE SIZE 0 0 ENA4H MMAP_DPSRAM1 BASE SIZE 0 0 ENB0H MMAP_SDRAM0 BASE SIZE 0 0 ENB4H MMAP_SDRAM1 BASE SIZE 0 0 ENC0H MMAP_EBI0 BASE SIZE 0 NP ENC4H MMAP_EBI1 BASE SIZE 0 NP ENC8H MMAP_EBI2 BASE SIZE 0 NP ENCCH MMAP_EBI3 BASE SIZE 0 NP END0H MMAP_PLD0 BASE SIZE 0 NP END4H MMAP_PLD1 BASE SIZE 0 NP END8H MMAP_PLD2 BASE SIZE 0 NP ENDCH MMAP_PLD3 BASE SIZE 0 NP EN

R/W Read/Write

R Read Only

00

0 130000

0000

0000


80

Memory Map

Memory Map Regions

Memory Map Control Registers Accessed Via AHB2– Only word access is allowed– Must disable write posting in PLD - stripe or AHB1 - AHB2

before writing from a PLD master or AHB1– Will not take effect until any writes outstanding on AHB2

complete– Minimum size is 16 Kbytes (13)

Name SizeEBI0, EBI1, EBI2, EBI3 16 Kbytes to 32 Mbytes eachSDRAM0, SDRAM1 16 Kbytes to 256 Mbytes eachInternal SRAM0, SRAM1 256 Kbytes total (for XA/M10)Internal dual-port DPSRAM0, DPSRAM1 128 Kbytes total (for XA/M10)Registers 16 KbytesPLD ranges PLD0, PLD1, PLD2, PLD3 16 Kbytes to 2 Gbytes each


81

Memory Map

While the System Is in Boot Mode, an Additional Mapping Is Present at Address 0H– This mapping is the first 32 kbytes of EBI0– Boot-mode mapping can be switched off using the boot

configuration register BOOT_CRMost of the Range Definition Registers Are Fully Read/write Enabled Except As Follows– For these registers, the NP bit is 0

MMAP_SDRAM0, MMAP_SDRAM1MMAP_SRAM0, MMAP_SRAM1MMAP_DPRAM0, MMAP_DPRAM1

– For MMAP_REGISTERS, SIZE = 13 NP = 1


82

MegaWizard

Enter the base address & size

Automatic checking for overlapping

regions or incorrect base address


PLLs & Clock Domains


84

Stripe PLL’s

Stripe PLL’s Provide Clock Boost Multiplication Only– Default power-up operation is bypass– Program control registers through configuration logic or the

embedded processor – State machine control to put PLL in bypass mode if lock is

lost– Can change PLL frequency with proper software control

PLL1– Clock for processor and peripheral bus– Up to 400 Mhz operation divided by 2 or 4

PLL2– Clock for the SDRAM controller– Up to 266 Mhz operation


85

Stripe PLL’s

Stripe Contains 2 PLL’s

PLL 1 & PLL 2 are similar to APEX PLLs– Fout = CLK_REF (MHz) * M/ (N *K) where M, N, K are integers

– PLLs can be bypassed

PLL1

PLL2

CLK_REF

CLK_AHB1

CLK_AHB2

CLK_SDRAM

÷2

÷4


86

Clock Domains

Name Frequency (MHz)

Derivation Use

CLK_REF 10-66 Pin Feeds Stripe PLL's and Fixed Frequency Logic (e.g. Watchdog Timer)

CLK_AHB1 <=200 PLL1 Embedded Processor BusCLK_AHB2 <=100 PLL1 Peripheral BusCLK_SDRAM 266 PLL2 SDRAM Memory Controller

SLAVE_HCLK <=100 PLD Clocks the Slave Port of the PLD - Stripe Bridge; Invertible

MASTER_HCLK <=100 PLD Clocks the Master Port of the Stripe - PLD Bridge; Invertible

CLK_PLDA[3..0] <=100 PLD Clocks the PLD Application Interface (SRAM access); Invertible


87

Clock Domains

SDRAM Domain (133MHz)

ProcessorCache+ MMU

DPRAM

Debug & Trace

Brid

geAHB1 bus

PLL SDRAMcontroller

Brid

ge

AHB2 bus

BusExpansion

Commscontroller

AHB bus

DSPfunction

Brid

ge

UART Timer

LCD

Processor Domain

AHB2 Domain

Typical PLD Domains( X MHz)

XXX

USB

othe

r bus

PLL

PLL, Mul or Div

DSPfunction

SRAM

4 PLL’s in XA4 & XA102 PLL’s in XA1

PLD

-AH

B2

Brid

geA

HB

2-P

LDB

ridge

AHB bus

DPRAM Interface


88

Control Registers

PLL Control RegistersAddress Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

300H CLK_PLL1_NCNT 0 CT2 CT1 CT0 0 C 10..8 0 2..0304H CLK_PLL1_MCNT 0 CT2 CT1 CT0 0 C 10..8 0 2..0308H CLK_PLL1_KCNT 0 CT2 CT1 CT0 0 C 030CH CLK_PLL1_CTRL 0 CTRL P310H CLK_PLL2_NCNT 0 CT2 CT1 CT0 0 C 10..8 0 2..0314H CLK_PLL2_MCNT 0 CT2 CT1 CT0 0 C 10..8 0 2..0318H CLK_PLL2_KCNT 0 CT2 CT1 CT0 0 C 031CH CLK_PLL2_CTRL 0 CTRL P320H CLK_DERIVE 0 BP2 BP1 0 1 0324H CLK_STATUS 0 P2 P1 C2 C1 L2 L1328H CLK_AHB1_COUNT Count of Processor Cycles Since Reset

R/W Read/Write R/C Read/Clear 1

R Read Only W Write Only

9..8

9..8

1..0

1..0


89

Clock Multiplication

Formula and Determination of M, N, & KF vco =F in ×M/Nwhere:0<M≤15, 0<N≤15, & 0<K≤7and 200≤F vco≤400 (300 is ideal)Finally, PLL out =F vco /K


90

MegaWizard

External clock reference

AHB1 / AHB2 clock settings

SDRAM clock setting


Single Port SRAM


92

Excalibur Memory HierarchyHard Logic PLD

AHB 1-2Bridge

SDRAMController

PLD Application Interfaces

Single Port SRAM #1

Processor+

MMU+

Cache

AHB1 AHB2

Memory Mapped Peripherals

SDRAMSRAM Flash

PLD - AHB2 Bridge

PLDMaster(s)

BusExpansion

Single Port SRAM #2

Arbiter #1 Arbiter #2

Dual Port SRAM #1

Dual Port SRAM #2

Depth / Width Muxing

PLD Master Bus Clk is application dependent

Secondary Bus(AHB2) <= 100MHzProcessor Local Bus

(AHB1) <= 200MHz

AHB2

Arbiter #1 Arbiter #2

AHB1


93

Single Port SRAM

Stripe Memory Is Virage IP– 2 blocks available on AHB1 or AHB2 bus– 32, 128, or 256 Kbytes total depending on device size

Available From AHB1 and AHB2 Bus– Arbiter controls bus access– 32 bit wide

Each SRAM Block Is Byte AddressableSupports Big or Little Endian Transfers


94

Single Port SRAM

DualPort

DualPort

SinglePort

Single Port

AHB1

AHB2

Deep / Wide Muxing

PLD Application Interface(s)

2 blocks of Independently Addressable Single Port SRAM– Accessible to AHB Masters


95

Single Port SRAM

Status Register

AHB2 Interface

AHB1 Interface

Arbiter

Single PortSRAM

DataOut

AHB1

AHB2

AHB1 Clock

Address,DataIn, Control


96

Interface

Arbiter Resolves Competition Between AHB1 and AHB2 Interfaces for Access to the SRAM– Defaults to fixed round-robin scheme with fairness– Supports locked transfers

AHB1 Interface– Provides single-cycle response– Initial wait state may be inserted– Interface and arbiter insert minimal wait states on

embedded processor accessAHB2 Interface– Synchronizes transfers between AHB1 and AHB2 clock

domains– Operation is the same as the AHB1 interface


Dual Port SRAM


98

Dual Port SRAM

Stripe Memory Is Virage IP– 2 blocks available on AHB1 or AHB2 bus– 16, 64, or 128 Kbytes depending on device size– Each block can itself be configured as 2 blocks for a total of

4Available From AHB1, AHB2, or PLD– Arbiter controls access

Each Block Is Byte AddressableSupports Various Widths and Depths


99

Dual Port SRAM

DualPort

DualPort

SinglePort

Single Port

AHB1

AHB2

Deep / Wide Muxing

PLD Application Interface(s)

Up to 4 Blocks of Independently Addressable Dual Port SRAM– Accessible to AHB Masters

– Accessible to PLD in Several Depth/width Configurations


100

Block Diagram

Registers

AHB2 Interface

AHB1 Interface

Arbiter

Dual PortSRAM

Port PortB A

Port A DataOut

AHB1 Clock

Address,DataIn

Port B DataOut

Port A Address,DataIn

PORT_A_CLK

PORT_B_CLK

PLD Interface

Port B Address,DataIn

LOCK_GRANT_DPn,

LOCK_REQ_DPn


101

Control Registers

Dual Port Registers

GLBL R Global dual port mode (global CRAM [1:0])MODE R Dual port mode (CRAM [3:0])SIZE R Memory Block Size in KbytesLOCKADDR R/W Bits [16:5] Start address of the lock addressable

region

Address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 030H DPSRAM0_SR SIZE 0 GLBL MODE34H DPSRAM0_LCR 0 LOCKADDR 038H DPSRAM1_SR SIZE 0 GLBL MODE3CH DPSRAM1_LCR 0 LOCKADDR 0

R/W Read/Write

R Read Only


102

Dual Port SRAM

Dual Port Locking– At and above the address specified in DPSRAMx_LCR, the

arbiter only allows access by the AHB interfaces if LOCK_GRANTDPx has not been granted+If LOCK_GRANTDPx is true, AHB transactions are wait-

stated.+If the AHB interfaces are accessing when LOCK_REQDPx is

asserted, LOCK_GRANTDPx is not asserted until the end of the AHB transaction

– When configured as PLD only dual port, the lock signals are irrelevant

AHB1 and AHB2 Interface Works the Same As the Single Port SRAM


103

Dual Port SRAM Configurations

B2

PLD

DPRAM Block #132K x 16

DPRAMBlock #232K x 16


Processor

Dual Port SRAM BlockConfigurations(Excalibur1000)

AHBInterface -

PLDInterface

1 x 16k x 321 x 32k x 162 x 16k x 161 x 64k x 82 x 32k x 8

32k x 16 Dual Port (*)

Dual Port SRAM blocks can be

configured 6 ways

(*) - Configuration shown here

PLD

AHB1

Processor


(*) - Configurations shown here

16Kx16 16Kx16 32Kx8 32Kx8

Dual Port SRAM Block Configurations (Excalibur1000)

AHB Interface

128 Kbytes (16Kx16) 256 Kbytes (32Kx8)

PLD Interface

1 x 16k x 32 1 x 32k x 16

2 x 16k x 16 (*) 1 x 64k x 8

2 x 32k x 8 (*) 32k x 16 Dual Port


104

Dual Port SRAM

AHB Bus Always Has Full Depth of Address Space

2 x 32K x 8 2 x 16K x 16 1 x 32K x 16

32K

64K

16K

32K 32K

DPRAM 2,3

DPRAM 0,1

Note: No bus errors are generated reading the non-physical region.


105

MegaWizard

SRAM0,SRAM1 DPRAM0, DPRAM1

Memory Map

Combine dual port?

DPRAM0 setting DPRAM1 setting


SDRAM Controller


107

SDRAM

SDRAM controller is required for interfacing from processors to DRAM– Converts AHB byte address read/write to bit address

read/write signals the SDRAM requires– SDRAM must be initialized through software control

Synchronous Dynamic Random Access Memory– High density– Low cost– Relatively fast

DDR SDRAM - Dual Data Rate


108

SDRAM Controller

Stripe Contains a Controller for SDRAM or DDR SDRAM External Memory– Either 16 or 32 bit SDRAM or DDR SDRAM can be connected but

not bothRuns Asynchronously to AHB1 or AHB2Supports Byte, Half-word, and Word TransfersAddressing– AHB buses are byte addressed, DRAM is bit addressed– DRAMS have row, column, and bank address– Number of row and column bits depends on memory used

Supports 2 Blocks and up to 512 Mbytes Total of External DRAMSupports PC100/133 SDR SDRAMs and PC200/266 DDR SDRAMs


109

Block Diagram

FIFO

AHB2 I/F

AHB1 I/F

Arbiter

Data Out

Write Data

Control

FIFO

FIFO

FIFO

Data Capture

Read Data

Write Data

Control

Read Data

CLK_AHB1 266

CLK_AHB1 266

CLK_AHB2 266

CLK_AHB2 266

SDRAM Controller

266133


110

Control Registers

SDRAM RegistersAddress Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

400H SDRAM_TIMING1 0 RCD RAS RRD RP WR404H SDRAM_TIMING2 0 RC CL RFC 0408H SDRAM_CONFIG 0 MT 040CH SDRAM_REFRESH 0 RFSH410H SDRAM_ADDR 0 ROW COLUMN 041CH SDRAM_INIT 0 EN PR LM LEM RF BS SR 0420H SDRAM_MODE0 0 VAL424H SDRAM_MODE1 0 VAL

R/W Read/Write

R Read Only

W Write Only

BL

BA


111

MegaWizard

SDRAM0, SDRAM1 Memory map

Select device and port width

Click on the Show details button


112

MegaWizard

Memory Type

Timing parameters

Address bits


Expansion Bus Interface


114

Expansion Bus Interface (EBI)

Provides Capability to Interface to External DevicesConvert AHB Addressing to Signals External Devices Such As FLASH Memory Understand.– FLASH memory is nonvolatile and in-system re-

programmable– Store the APEXE configuration, user boot code, store data

Different Sizes and Types Available


115

Expansion Bus Interface (EBI)

Rate-Adaptation Between Flash Memories or Memory Mapped Peripherals and AHB2 Bus Masters

Four Chip Select Outputs– Each Address Space Can Be Configured to Operate in an

8- or 16-Bit Mode.

– Bus Timing and Interface Signals Can be Configured by a Bus Master

Supports Split Bus Transactions– Prevents Stalling of Other AHB2 Bus Masters


116

Block Diagram

Transaction FIFO

EBI Transaction Sequencer

AHB2 Interface

Timeout

EBI Interface

Start/Stop

Read Return FIFO

Control and Status

Registers

AHB2 Slave Interface

Control

Con

trol

Rea

d D

ata

Writ

e D

ata

EBI_DATA [15:0]

EBI_ADDR [24:0]

EBI_CS_n

EBI_WE_n

EBI_OE_n

EBI_BE_n

EBI_ACK

EBI_CLK

72

32

HWDATA

HADDR

HSIZE

HRDATA

InterruptTimer


117

Control Registers

EBI RegistersAddress Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

380H EBI_CR R 0 CE TE TIMEOUT 0 SP EO WP OP BPEBI_SR XP XF XE RF RE 0 CE TE TIMEOUT 0 SP EO WP OP BP

390H EBI_BLOCK0 0 BE BH CP WAIT SA394H EBI_BLOCK1 0 BE BH CP WAIT SA398H EBI_BLOCK2 0 BE BH CP WAIT SA39CH EBI_BLOCK3 0 BE BH CP WAIT SA3A0H EBI_INT_SR 0 TOI3A4H EBI_INT_ADDRSR B3 B2 B1 B0 0 ADDRESS

R/W Read/Write W Write Only

R Read Only R/C Read/Clear 1

CLK_DIVCLK_DIV


118

EBI Signals

Synchronous Read/Write


119


EBI Transaction Sequencer– Asynchronous reads and writes depend on the EBI_ACK

signal while synchronous does not– EBI_CLK is important in the sense of cycle timing only for

asynchronous operation– Software must ensure that EBI is not processing a transaction

when the speed is changed– Must use a timeout to prevent system lock-up when in

asynchronous mode in case EBI_ACK is not received– Reset using the R bit in EBI_CR to return to operational

condition


120


EBI Operation– The EBI is a slave only interface

+Capable of issuing a split response+Default is split disabled+Must be careful when switching split from disable to

enable– Write operations complete immediately– Non-split reads stall the AHB until the results are available


121

MegaWizard

EB0-3 Memory map

Select device settings


UART


123

UART5 to 8 data bits1 or 2 stop bitsEven, odd, stick, or no parity75 to 230,400 baud rate16-byte transmit FIFO16-byte receive FIFO.Programmable baud generator divides any input clock by 2 to 65535 and generates the 16 × baud clockTransmit FIFO interrupt for empty indication and transmitter idle indicationFalse-start bit detection

Internal diagnostic capabilities

– Loop-back control for communications-link fault isolation

– Break insertion and detection in loop-back mode

Modem communication support8-bit data connection– 8-bit registers on 4 byte

boundaries using an 8 bit data connection


124

Block Diagram

UART Core

Modem ControlSee interrupt

controller

AHB Interface

RTS_n

RXD

CTS_n

DSR_n

RI_n

DCD_n

DTR_n

TXD

CLK_AHB2

INTR

AHB2


125

Control Registers

UART RegistersAddress Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

280H UART_RSR 0 RE 0 RX_LEVEL284H UART_RDS 0 BI FE PE OE288H UART_RD 0 RX_DATA28CH UART_TSR 0 TXI 0 TX_LEVEL290H UART_TD 0 TX_DATA294H UART_FCR 0 RX_THR TX_THR RC TC298H UART_IES 0 ME TIE TE RE29CH UART_IEC 0 ME TIE TE RE2A0H UART_ISR 0 MI TII TI RI2A4H UART_IID 0 IID2A8H UART_MC 0 OE SP EP PE ST CLS2ACH UART_MCR 0 AC AR BR LC DCD RI DTR RTS

2B0H UART_MSR 0 DCD RI DSR CTSDDCD

TERI

DDSR

DCTS

2B4H UART_DIV_LO 0 DIV2B8H UART_DIV_HI 0 DIV

R/W Read/Write R* Read/effect

R Read Only R/S Read/Set 1

W Write Only R/C Read/Clear 1


127


User Configurable to Three System Modes– Interrupt Sources Can Arise From Stripe and PLD

Priority and Enabling Scheme – All Interrupts Disabled on Power-up

– Sets Priority on Interrupt Sources

– Enables or Disables Individual Interrupt Sources


128

Block Diagram


ARM 922T


129

Control Registers

Interrupt RegistersAddress Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

C00H INT_MASK_SET 0 FC M1 M0 AE PE EE PS T1 T0 UA IP P5 P4 P3 P2 P1 P0C04H INT_MASK_CLEAR 0 FC M1 M0 AE PE EE PS T1 T0 UA IP P5 P4 P3 P2 P1 P0C08H INT_SOURCE_STATUS 0 FC M1 M0 AE PE EE PS T1 T0 UA IP P5 P4 P3 P2 P1 P0C0CH INT_REQUEST_STATUS 0 FC M1 M0 AE PE EE PS T1 T0 UA IP P5 P4 P3 P2 P1 P0C10H INT_ID 0 IDC14H INT_PLD_PRIORITY 0 PLD_PRIC18H INT_MODE 0C80H INT_PRIORITY_0 0 FQ PRIC84H INT_PRIORITY_1 0 FQ PRIC88H INT_PRIORITY_2 0 FQ PRIC8CH INT_PRIORITY_3 0 FQ PRIC90H INT_PRIORITY_4 0 FQ PRIC94H INT_PRIORITY_5 0 FQ PRIC98H INT_PRIORITY_6 0 FQ PRIC9CH INT_PRIORITY_7 0 FQ PRICA0H INT_PRIORITY_8 0 FQ PRICA4H INT_PRIORITY_9 0 FQ PRICA8H INT_PRIORITY_10 0 FQ PRICACH INT_PRIORITY_11 0 FQ PRICB0H INT_PRIORITY_12 0 FQ PRICB4H INT_PRIORITY_13 0 FQ PRICB8H INT_PRIORITY_14 0 FQ PRICBCH INT_PRIORITY_15 0 FQ PRICC0H INT_PRIORITY_16 0 FQ PRI

R/W Read/Write R/S Read/Set 1

R Read Only R/C Read/Clear 1

MODE


130

MegaWizard

Select the Interrupts


Watchdog Timer


132

Watchdog Timer

Protects the System against Software / Hardware Failures

One-shot Timer Resets Entire Chip When It Expires

32-bit Register Interface Provides User-selected Timeouts– Up to 30s With a 33MHz Clock


133

Control Registers

Watchdog Timer RegistersAddress Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A00H WDOG_CR 0 TRIGGER 0 LKA04H WDOG_COUNT 0 COUNTA08H WDOG_RELOAD MAGIC

R Read Only

R/W Read/Write

W Write Only


134

Watchdog Timer

Trigger Assertion Resets the SystemHardware Trigger– A low signal on DEBUG_EN enables the hardware

watchdog, which then triggers if COUNT in WDOG_COUNT overflows.

Software Trigger– Setting TRIGGER in WDOG_CR to a non-zero value enables

the software trigger.Writing MAGIC Values– A5A5A5A5H must be first after TRIGGER is written– 5A5A5A5AH is the second value and then must alternate

between the two– Watchdog triggers if an incorrect value is written


Timer


136

Timer

Dual-Channel Timer32 Bit Prescaler32 Bit Timer RegisterThree Operating Modes– Free running interrupt (heartbeat)– Software controlled start/stop (interval timer) with interrupt

on limit– One-shot interrupt after programmable delay


137

Block Diagram

AHB Interface

Channel 0

Channel 1

AHB2

INT_TIMER1

INT_TIMER0


138

Control Registers

Timer RegistersAddress Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

200H TIMER0_CR 0 S CI IETIMER0_SR 0 S CI IE

210H TIMER0_PRE PRESCALE220H TIMER0_LIMIT LIMIT230H TIMER0_READ READ240H TIMER1_CR 0 S CI IE

TIMER1_SR 0 S CI IE250H TIMER1_PRE PRESCALE260H TIMER1_LIMIT LIMIT270H TIMER1_READ READ

R/W Read/Write

R Read Only

W Write Only

MODE

MODE

MODE

MODE


Reset & Mode Control


140

Reset & Mode Control

PLD power-on resetResets from external sources– Configuration pin nCONFIG– External reset pin (bi-directional open drain pin, supplying

reset output to flash devices)– External power-on reset

Resets from internal sources– Software watchdog timer reset– JTAG module– Configuration error


141

Reset Sequence


142

Control Registers

Reset and Mode RegistersAddress Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0H BOOT_CR 0 RE HM BF4H RESET_SR 0 ER JT CR WR8H IDCODE IDCODE40H IOCR_SDRAM 0 OC IO LK44H IOCR_EBI 0 OC IO LK48H IOCR_UART 0 OC IO LK4CH IOCR_TRACE 0 OC IO LK7CH SDRAM_WIDTH 0 W LK

R/W Read/Write

R Read Only

R/C Read/Clear 1

IC

ICICIC


143

Agenda



144

Peripheral VerificationBus Functional Models– AHB Transactions Simulated

+Reads, Writes, Bursts, etc.– Functional & Timing Simulations Possible– Does Not Model

+ARM-Based Excalibur Stripe+Stripe-to-Programmable Logic Bridge+Programmable Logic-to-Stripe Bridge

Embedded Stripe Models– Cycle-Accurate Model Based on Embedded Stripe Register

Transfer Level (RTL)– Functional & Timing Simulations Possible– Models

+ARM-Based Excalibur Stripe+Stripe-to-Programmable Logic Bridge+Programmable Logic-to-Stripe Bridge


Peripheral VerificationUsing Bus Functional Model


146

Bus Functional Model:Master Port

Models AHB Master Bus Transactions

Bus Functional Model

Master Port

mastercommands.dat

slavememory.cfg.dat

Logic Slave

PeripheralControl Signal

Address

Data


147

Bus Functional Model:Slave Port

Models AHB Slave Bus Transactions

Bus Functional Model

Slave Port

mastercommands.datslavememory.cfg.dat

Logic Master

PeripheralControl

Address

Data

slavememory.<bank#>.dat


148

input.datBus Transactor Translates input.dat to mastercommands.datinput.dat Format

WRITE ( START, SIZE, LENGTH, DATAVALUE, [ , DATAVALUE …] );

READ ( START, SIZE, LENGTH);

IDLE ( CYCLES );

Example


149

mastercommands.dat


150

Pre-Synthesis Simulation

Quartus IISoftware

Design

input.dat

mastercommands.dat

stimulus.doslavememory.cfg.dat

(Slavememory.<bank#>.dat)

Output# MASTER: trans=[ 1] addr=[00000004] WRITE data=[00000005] expected=[00000005] WORD OKAY

# MASTER: trans=[ 3] addr=[00000004] READ data=[00000000] expected=[00000000] WORD OKAY

ModelSimTool

Altera_mf.vAlt_exc_stripe_bfm.v

Design.v

exc_bus_translate.exe


151

Quartus IISoftware

Designexc_bus_translate.exe

input.dat

mastercommands.dat

stimulus.doslavememory.cfg.dat

(slavememory.<bank#>.dat)

ModelSimTool

apex20ke_atoms.v<design>.vo

<design>..sdoalt_exc_stripe_bfm.v

Post-Synthesis Simulation

Third-Party

SynthesisTool

# MASTER: trans=[ 1] addr=[00000004] WRITE data=[00000005] expected=[00000005] WORD OKAY

# MASTER: trans=[ 3] addr=[00000004] READ data=[00000000] expected=[00000000] WORD OKAY

Output

DesignEDIF

Input File(.edf)


System VerificationUsing Embedded Stripe Model


153

Excalibur System

SDRAMModel

Excalibur Stripe

Programmable Logic

Stripe-to-PLD (Master Port)

EBI Port

SDRAM Port

Master

Slave

PLD-to-Stripe (Slave Port)

ROMModel

Bus Functional Model Verification

Full Stripe Model Verification


154

System-Level SimulationProcessorTimerInterrupt ControllerUARTEBIDPRAM, SRAM

SDRAM ControllerAHB1-AHB2 BridgeStripe-to-Programmable Logic BridgeProgrammable Logic-to-Stripe BridgePLLs (Limited Model of Behavior)PLD Configuration Not Modeled

WatchdogTimer

PLLDual-Port SRAM

SDRAMController

Single-Port SRAM

32-Bit RISC Processor


AHB1

AHB2

Programmable Logic

PLD-to-Stripe Bridge

Programmable Logic Master

Peripheral


Reset Module Timer

Logic SlavePeripheral

UARTEBI

Stripe-to-PLD Bridge

Logic Slave Peripheral

LogicModule

LogicModule

AHB1-AHB2Bridge


155

System-Level Simulation

Embedded Stripe Model– Cycle Accurate

Programmable Logic– Programmable Logic Peripherals Interacting with Embedded Stripe– Independent Logic

External Components– Flash

+Connect ROM Model to EBI Port– SDRAM

+Connect SDRAM Model to SDRAM Port


156

Tool Flow

ExcaliburMegaWizard Plug-In

Configured Stripe

Instance

Top-Level Design

User SelectionsProgram-

mableLogic

Third-Party Synthesis

Full Stripe Model

Mentor GraphicsModelSim/

Synopsys VCS

BusFunctional

Model

BehavioralRTL

Testbench

ROM Model

SDRAM Model

C/Assembly

Code

Netlist Output

Quartus IISoftware

Gate-Level/Timing


157

Simulation Procedure

*Optional

Create Configured Stripe Library of Parameterized Modules (LPM)

Generate Stripe Model Initialization Files*

Convert Code to Memory Model Format*

Perform RTL Simulation

Synthesize Programmable Logic

Place & Route in Quartus II Software

Perform Timing Simulation


158

Agenda



159

SOC-ENTRY II Feature

SoC(System on Chip) Design Solution : ExcaliburARM922T ARM-Based Embedded Processor & FPGAA variety of memory & peripheral : Flash, SDRAM, SRAM, 10/100T Ethernet, UART, 1024X768 24-bit Color VGA, 3.5 Inch TFT-LCD, CIS(CMOS Image Sensor), USB2.0, AC97 Audio Codec, High speed ADC/DAC, PCMCIA, ATA-IDE I/F, PS/2, Text LCD, Keypad, 7-Segment, Step motor, User I/O, etcDebug method : Multi-ICE, ByteBlasterExternal User I/O Interface(70~140Pin)


160

H/W Spec.

Key pad(0~9, *, #)Dip switch(16bit)

PeripheralI/O

UART(ARM), UART(PLD)Serial Port10/100MT Ethernet 2EAEthernet

Multi-ICE, JTAGDebug & Download

(Optional)Config. Device32MB x 4, 32MB x 4, Total 256MBSDRAM16MB x 2, 32MBFlash25MHz/50MHzRef. Clock

ARM922T(EPXA1/EPXA4)100,000/400,000 GateAHB1 : 200MHz, AHB2 : 100MHzInternal Memory : SRAM/DPRAM

Excalibur

SOC-ENTRY IISpec.


161

H/W Spec.

Real Time Clock 1EARTC256KB x 16 External SRAM 2EASRAM3.5 Inch TFT LCD with Touch Screen 1EADisplayCIS(CMOS Image Sensor) 1EACameraPCMCIA Slot 1EACard Slot

USB2.0 Controller 2Port & 1Port(OTG)USBAC97 Audio Codec MIC in & SPK outAudio1024-768 24-bit VGA DAC 1EAVGA20MSPS 12-bit ADC 1EA125MSPS 12-bit DAC 1EA

AD/DA

16X2 Text LCD 1EA8-Digit 7-Segment 1EALED 16EA5X7 Dot matrix 4EA(10 X 14 Matrix)Piezo 1EA

PeripheralI/O


162

H/W Spec.

Expansion Port(70Pin/140Pin)25 X 2 Expansion Pin Header(46Pin)

User I/O

336(W) X 279(H) 10-layerPCB

Keyboard or Mouse port 2EAPS/2

Ethernet Cross 1EASerial Cross 1EAByteBlaster 1EA25P-Parallel 1EAPower 1EA

Cable

220V DC Input/+5V DC OutputPower


163

Block Diagram


164

SOC-ENTRY II Board

PS/2

UART

VGA DOT

7-Segment

Text-LCD

AC97 AD/DA

Ethernet USB2.0DC/DC

IDE

USER Ex.

Ref.Clock

RTC

Sept Motor

Cables3.5 TFT LCD

CIS Dip-SwitchPush&Keypad

SRAM

SDRAM

Flash

Excalbur

Multi-ICEByte

Expansion Board~140Pin

PCMCIA

LED PIEZO

Case


165

Ref. Clock

25MHz

50MHz

ClockDriver

Excalibur

ARM Ref. Clock

CLK1p

CLK2p

CLK3p

CLK4p

P20CLK1p

W6CLK2p

R23CLK3p

Y5CLK4p

I/O PinSymbol

Dedicated Input Clock Pin

Output Select

1-250MHz

2-325Mhz

SettingFunc.

Clock Output Setting(J28)


166

Boot Mode

1-2Flash

2-3PROM

SettingFunc.

Boot Mode(J21)


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Debug setting(JTAG Mode)

1-2Parallel (Multi-ICE & Byte)

2-3Serial (Byte only)

SettingFunc.

JTAG Mode(J23)

Serial JTAG Mode

parallel JTAG Mode

ByteBlaster Only

ByteBlaster

Muti-ICE


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Using Peripheral I/OQuestion : I want to use LED or Dot or 7-Segment or Dip-Switch or Keypad or Text LCD or Piezo or UART(PLD) or Motor or PS/2 in Hanback Soc-entry II platform, but I can’t. What is the problem? Please help me.Answer : Soc-entry II Excalibur I/O pins are connected to several device. For example….(cont.)

I/O PinSwitch

(next page)

LED or LCD or 7-Segment or …

I/O Pin

Excalibur I/O Pins

Device Input/Output Pin

Device Input/Output Pin

SDRAM


169

Using Peripheral I/OAnswer : Thus user should set peripheral I/O connection enable switch(Ref.No S1 or S6).

Dip-Switch #28

Dip-Switch #17

Text-LCD&Piezo6

Keypad5

Dot-Matrix4

7-Segment3

LED #22

LED #11

DescriptionNo. of Pos DescriptionNo. of Pos

RESERVED8

RESERVED7

RESERVED6

RTC5

Motor4

RESERVED3

UART(PLD)2

PS/21

S1 S6


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Platform Setup

Serial Cable

Parallel Cable

ByteBlaster

Ethernet Cable

Multi-ICE1)

1) Multi-ICE is ARM Debugger


171

Product Components


172

Additional Expansion BoardXilinx Virtex II FPGA 1M ~ 8M Gates Module(110WX110D) 144Pin SODIMM PC133 Memory Module

144Pin SODIMM CIS/SRAM/Flash/Prom Module


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What can It Do?

Real Time Test with Linux O.S.ARM based IP VerificationMemory Controller & Communication ControllerAMBA Bus protocol ImplementationMultifunction PrintersNetwork PrintersEnterprise Backbone SwitchesGigabit Ethernet Switches (as I/O Processor)Embedded RoutersInfrastructure Equipment for Storage Area NetworksxDSL Line Cards


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Contents in CDHBE-SoC-Entry II User’s Guide

– Doc folder+ User’s Manual & Schematic

– Tools+ Window TFT server program & SOPC Builder2.7 for GCC

– Tutorials+ AC97 reference design+ FPGA reference design+ PS/2 Keyboard reference design+ Simple Watch reference design+ ARM Interrupt reference design+ ARM Keyboard reference design+ ARM Keypad reference design+ ARM Led drive reference design+ ARM Multi-slave reference design+ ARM External SRAM read/write reference design+ ARM Text-LCD control reference design+ ARM TFT-LCD with DMA reference design+ ARM VGA with DMA reference design

HBE-SoC-Entry II Linux Guide– Boot-loader source/Linux OS source/Cross-tools/Binary image/Cygwin/Manual


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HANBACK Technical Support

Reference User’s ManualConsult Applications– Tel: (042) 524-2580 (9:00 a.m. ~ 6:00 p.m.)– E-mail: [email protected]

Sales– Tel: (042) 536-3001 (9:00 a.m. ~ 6:00 p.m.)– E-mail: [email protected]

World-Wide Web: http://www.hanback.co.kr– Answers to Technical Problems – View Design Examples

© 2005 hanback corporation · thumb: 16 bit instructions a subset of the 32-bit arm® instructions...

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