© 2010 eric pop, uiucece 598ep: hot chips 1 transient thermal response transient models –lumped:...
TRANSCRIPT
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 1
Transient Thermal Response
• Transient Models– Lumped: Tenbroek (1997), Rinaldi
(2001), Lin (2004)
– Introduce CTH usually with approximate
Green’s functions; heated volume is a function of time (Joy, 1970)
– Finite-Element methods
( , ) erfc2 2Si
P rT r t
k r t
Temperature evolution of a step-heated point source into silicon half-plane (Mautry 1990)
Simplest (~ bulk Si FET)
Instantaneous T rise
E P tT
C cV
Due to very sharp heating pulse t ‹‹ V2/3/
2
3/ 2 3/ 20
1 ( ')( , ) exp ' '
8 ( ) ( ') 4 ( ')
t P t rT r t dV dt
cV t t t t
More general
Temperature evolution anywhere (r,t) due to arbitrary heating function P(0<t’<t) inside volume V (dV’ V) (Joy 1970)
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 2
Instantaneous Temperature Rise
• Neglect convection & radiation
• Assuming lumped body
• Biot = hL/k << 1, internal resistance and T variation neglected, T(x) = T = const.
Instantaneous T rise
E P tT
C cV
Due to very sharp heating pulse t ‹‹ V2/3/
L
W d
2
02
'''( )
T P hA c TT T
x k kV k t
1/
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 3
Lumped Temperature Decay
• After power input switched off
• Assuming lumped body
• RTH = 1/hA
• CTH = cV
• Time constant ~ RTHCTH
T decay
( / )0( ) e hA cV t
HT T T
L
W dT(t=0) = TH
2
02
'''( )
T P hA c TT T
x k kV k t
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 4
Electrical and Mechanical Analogy
• Thermal capacitance (C = ρcV) normally spread over the volume of the body
• When Biot << 1 we can lump capacitance into a single “circuit element” (electrical or mechanical analogy)
There are no physical elements analogousto mass or inductance in thermal systems
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 5
Transient Edge (Face) Heating
Also http://www.uh.edu/engines/epi1384.htm
Lienhard book, http://web.mit.edu/lienhard/www/ahtt.html
When is only the surface of a body heated?I.e. when is the depth dimension “infinite”?
2
2
1T T
x t
Note: Only heated surface B.C. is available
erf2
fire
i fire
T T x
T T t
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 6
• If body is “semi-infinite” there is no length scale on which to build the Biot number
• Replace Biot (αt)1/2
2erf exp erfc2 2
fire
i fire
T T
T T
x
t
h t
k
Note this reduces to previous slide’s simplerexpression (erf only) when h=0!
Transient Heating with Convective B.C.
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 7
Transient Lumped Spreading Resistance
• Point source of heat in material with k, c and α = k/c
• Or spherical heat source, outside sphere
• This is OK if we want to roughly approximate transistor as a sphere embedded in material with k, c
Source: Timo Veijola, http://www.aplac.hut.fi/publications/bec-1996-01/bec/bec.html
2
2
1 ( ) 1rT P T
r r k t
( , ) erfc2 2Si
P rT r t
k r t
Temperature evolution of a step-heated point source into silicon half-plane (Mautry 1990)
~ Bulk Si FET transient
Characteristic diffusion length LD = (αt)1/2
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 8
Transient of a Step-Heated Transistor
In general:
Carslaw and Jaeger (2e, 1986)
“Instantaneously” means short pulse timevs. Si diffusion time (t < LD
2/α) orshort depth vs. Si diffusion length (L < (αt)1/2)
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 9
Device Thermal Transients (3D)
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 10
Temperature of Pulsed Diode
Holway, TED 27,433 (1980)
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 11
Interconnect Reliability
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 12
Transient of a Step-Heated Interconnect
When to use “adiabaticapproximation” andwhen to worry aboutheat dissipation intosurrounding oxide
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 13
Transient Thermal Failure
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 14
Understanding the sqrt(t) Dependence
• Physical = think of the heated volume as it expands ~ (αt)1/2
• Mathematical = erf approximation
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 15
Time Scales of Thermal Device Failure
• Three time scales:– “Small” failure times: all heat dissipated within defect, little
heat lost to surrounding ~ adiabatic (ΔT ~ Pt)– Intermediate time: heating up surrounding layer of (αt)1/2 – “Long” failure time ~ steady-state, thermal equilibrium
established: ΔT ~ P*const. = PRTH
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 16
Ex: Failure of SiGe HBT and Cu IC
Wunsch-Bell curve of HBT
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 17
Ex: Failure of Al/Cu Interconnects
• Fracture due to the expansion of critical volume of molten Al/Cu. (@ 1000 0C)
Metal 4
~ 12 mmFailed Interconnect
AlCu on polymer Intel Corporation
Ju & Goodson, Elec. Dev. Lett. 18, 512 (1997)
0
0
t = 200 ns
150 ns
100 ns
T along Interconnect
x
T
200 K
Banerjee et al., IRPS 2000
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 18
Temperature Rise in Vias
Via and interconnect dimensions are not consistent from a heat generation / thermal resistance perspective, leading to hotspots. New model accounts for via conduction and Joule heating and recommends dimensions considering temperature and EM lifetime.
Based on ITRS global lines of a 100 nm technology node(Left: ANSYS simulation. Right: Closed-Form Modeling)
S. Im, K. Banerjee, and K. E. Goodson, IRPS 2002
Metal Line
ILD
Via Hotspot
0
5
10
15
1 2 3 4 5 6 7 8T
n-T
0 [o C
]Metal Level (n)
no vias
isothermalvias
vias withJoule heating
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 19
Time Scales of Electrothermal Processes
10-12 10-11 10-10 10-9 10-8 10-7
seconds
MechanisticTimescales
StressTimescales
electron & phononrelaxation times
conduction processes within transistor and gate oxide diffusion processes within
interconnects, vias, passivation
clockperiod
gateswitching ESD / EOS Phenomena
-1
123
0 20 40 60 80 100 120ns
I ES
D(A
)
CDM
HBM
MM
456
Governs peak transistor temperature & mobility reduction, leakage augmentation
Governs total power consumption, package-level cooling
Governs relative importance of failure modes for ESD
Source: K. Goodson
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 20
ESD: Electrostatic Discharge
• High-field damage
• High-current damage
• Thermal runaway
…
…
J. Vinson & J. Liou, Proc. IEEE 86, 2 (1998)
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 21
Common ESD Models
Combined, transient,electro-thermal device models
Gate
DrainSourceJ. Vinson & J. Liou, Proc. IEEE 86, 2 (1998)
Lumped: Human-Body Model (HBM)
Lumped: Machine Model (MM)
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 22
Reliability
• The Arrhenius Equation: MTF=A*exp(Ea/kBT)
• MTF: mean time to failure at T• A: empirical constant
• Ea: activation energy
• kB: Boltzmann’s constant
• T: absolute temperature
• Failure mechanisms:
• Die metalization (Corrosion, Electromigration, Contact spiking)• Oxide (charge trapping, gate oxide breakdown, hot electrons)• Device (ionic contamination, second breakdown, surface-charge)• Die attach (fracture, thermal breakdown, adhesion fatigue)• Interconnect (wirebond failure, flip-chip joint failure)• Package (cracking, whisker and dendritic growth, lid seal failure)
• Most of the above increase with T (Arrhenius)
• Notable exception: hot electrons are worse at low temperatures
Source: M. Stan
Ea = 1.1 eV
Ea = 0.7 eV
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 23
Improved Reliability AnalysisM. Stan (2007), Van der Bosch, IEDM (2006)
( )
0
1
( )
failure at E
kT tthe dt const
kT t
life consumption rate
• There is NO “one size fits all” reliability estimate approach
• Typical reliability lifetime estimates done at worst-case temperature (e.g. 125 oC) which is an OVERDESIGN
• Apply in a “lumped” fashion at the granularity of microarchitecture units
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 24
Combined Package Model
Steady-state:
Tj – junction temperature
Tc – case temperature
Ts – heat sink temperature
Ta – ambient temperature
Rtotal(ITRS 2003)
RchipRchip
Rh
ea
tsin
k
0
0.1
0.2
0.3 oC/W
2000 2005 2010 2015 2020
3DIC3DIC
MulticoreMulticore
© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 25
Thermal Design Summary
• Temperature affects performance, power, and reliability
• Architecture-level: conduction only– Very crude approximation of convection as equivalent resistance– Convection, in general: too complicated, need CFD!
• Use compact models for package• Power density is key• Temporal, spatial variation are key• Hot spots drive thermal design