© 2013 uniklbmi design and analysis of monolithic bicmos...

Journal of Engineering Technology Vol. 3(1): 28-34, 2013

ISSN 2231-8798

© 2013 UniKLBMI

28

Design and Analysis of Monolithic BiCMOS

Quadrature LO Buffer 4G RFIC

S. BASIR

VLSI & RFIC VERIFICATION LABS

Universiti Kuala Lumpur Malaysian Spanish Institute

Corresponding email: [email protected]

Abstract: The transmitter section of a 4G RFIC utilized an eight-stage segmented open collector Gilbert Cell

up-mixer for the internal building block of the Quadrature RF Modulator. The modulator circuit block is

designed to include I/Q baseband AB Amplifiers, baseband low pass filters, voltage to current (V-to-I)

conversion circuit, Gilbert Cells, and the quadrature LO buffers. Prior to LO buffer is LO ramp up circuit to

smooth the rise and fall of LO signal to maintain carrier level of the modulator output less than -35dBc that

promise high linearity transmission at all specified transmit power levels per specifications (0 to –35dBm).

Keywords: 4G RFIC, Quadrature LO buffer, LO ramp circuit, RF Modulator, RF-CMOS

1.0 INTRODUCTION

A fundamental block of the RF transmitter is the up-

mixer that converts the baseband input signal to the higher

RF frequency. Among the various mixer topologies,

double-balanced Gilbert Cell mixer is preferred since it has

ample margin of LO carrier suppression at the output ports

[7].

The LO buffer with voltage level shifter is needed

simply to make it generates well balanced differential I/Q

signals with large enough swing to feed the up-mixer. As

shown in Fig. 1 the LO buffer is composed of two sections.

The first section converts the CMOS LO signals to CML

signals and uses the 1.875V transmit quadrature generator.

To minimize spectral splatter, the LO signals are ramped in

a controlled manner by ramping the referenced current

iref1 and iref2 [1], [2], [3]. A special LO ramp circuit is

used that includes an of chip capacitor to control the rate of

LO buffer ramp up and ramp down. The second section

includes transmission gates with common-mode level sets

channel voltage for the T-gates and output emitter

followers to drive the Gilbert Cell switches in the RF

Modulator. A small dc block capacitor is needed to avoid

signal attenuation due to parasitic capacitance and other RF

switching devices. The used of a 2.10pF capacitor and

High Frequency BJT switches in the Gilbert cells produced

good ac response as observed at emitter-follower node with

square LO signal at 800MHz to 1GHz. The ac gain is

maintained at 0.3dB and does not significantly affect its

linearity where the IMR3 is -43dBc measured at output

power per-tone of -3dBm.

2.0 LO BUFFER TOPOLOGY

The requirement for 4G LO Buffer is a differential

amplifier with resistor loads where the required input

signal is generated by quadrature generator with 1.8V

CMOS level and maximum carrier frequency at 1GHz.

The output must be able to drive a three parallel 2.775V

LO buffer blocks to accommodate 0dB, 10dB, and 20dB

mixer gain reduction and are designed and named

4G_tx_upm_lobuff_00db_2p7,

4G_tx_upm_lobuff_10db_2p7,

4G_tx_upm_lobuff_20db_2p7.

SPI bit controls the LO block’s activation sequence by

setting only one block at a time, whilst capacitive loading

still exists on the others. The

4G_tx_upm_lobuff_00db_2p7 is designed by using bigger

input DC block capacitors from 0.98pF to 4.8pF. The

main issue seen in the old 3G design is the signal being

attenuated too early. The source of the problem is related

to the RF-CMOS transistor named PFET33_RF acting as

switching devices loaded with higher parastic capacitance.

Based on intensive characterization of the device scaling

versus switching sequences, it is found that if the DC block


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capacitor remains at value of 4.8pF,

4G_tx_upm_lobuff_1p8 LO buffer needs to generate extra

12mA [4], [6].

The enhancement of 4G LO buffer has size reduction of

DC blocking capacitors as needed. Therefore the

PFET33_RF size is reduced to W/L=16/0.4 X 2 with each

capacitor is now resized at 2.10pF. The NPN transistors

Q4T, Q5T, Q5, Q4, Q3 are type high frequency BJTs to

permit higher current flows and for wider frequency

coverage. This enhancement version of LO provides better

response in GHz range with acceptable high linearity. The

series resistors R5, R4, R3 are scaled at 20-Ohms, 20-

Ohms, 200-Ohms respectively.

Another LO buffer with 1.8V DC referred as

4G_tx_upm_lobuff_1p8 is needed to drive the

4G_tx_upm_lobuff_10db_2p7 and the 10dB and 20/30dB

blocks. Below are the schematic of 3G LO buffer shown

in Fig. 2(a) versus the schematic enhancement version of

the 4G LO buffer shown in Fig. 2(b).

Fig.1 Quadrature LO Buffer Injection Path

Fig. 2 (a) LO Buffer of 3G RFIC


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Fig.2 (b) Enhanced LO Buffer 4G RFIC

Plots of Fig. 3 shown are comparison of AC output

bandwidth between LO buffer of a 3G RFIC and 4GRFIC

based on a typical operating condition where the yellow

plot is the AC signal probed at the output buffer of 3G LO

buffer. The black plot is the AC signal probed at the

output of the improved 4G LO buffer version with 2.1pF

capacitor which is observed at emitter-follower node

having a smooth roll off transition. It is also observed that

the AC signals are almost identical for both channels I/Q

differentially with square input LO injected at 800MHz.

With this enhancement, AC gain drops roughly 0.3dB

which does not affect much on the IMR3 ~ -43dBc and

Output Power Per-Tone ~-3.01dBm as expected required

by the design specifications.

Fig. 3. LO Buffer output bandwidth comparison between

3G RFIC and 4G RFIC

Fig. 4 below is the expected plot of wideband AC response

of the LO Buffer for 4G_tx_upm_lobuff_00db_2p7, which

output with NPN loading is analyzed for Monte Carlo

process mismatch corners, dc voltage sweep, and

temperature variances (PVT). The other two

4G_tx_upm_lobuff_00db_2p7 LO buffers are connected

but turned in battery save mode controlled by SPI bit

sequencer.

Fig. 4 Smooth AC response of

4G_ tx_upm_lobuff_00dB_2p7

3.0 LO BUFFER EVALUATIONS

A thorough characterization is done to measure the

integrity of the new LO Buffer. This is done by injecting

input signal from 0V to 1.8V and the output is 1V pk-pk

differential. As plotted in the next Fig. 4 is a transient

response at -30C, 27C, 100C, Vdd=2.65V, LVdd=1.8V.

The top plot is the output of 4G_tx_upm_lobuff_1p8 and


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the bottom plot is the output signal taken from output pin

of 4G_tx_upm_lobuff_00db_2p7.

Fig. 5 Good Quadrature CMOS signal response for

different PVT runs

Table 1: Rise/Fall time of 1.8V and 2.775V LO buffer

characterized for PVT 4GRFIC_tx_upm_lobuff_1p8 output 4GRFIC_tx_upm_lobuff_00db_2p7

Temp Corner PK-PK Rise TimeFall

Time Pk-PK Rise Time Fall Time

27C FFhh 1.114 -95.72p 95.72p 0.924 -98.79p 98.79p

-30C FFhh 1.078 -93.51p 93.51p 0.899 -96.39p 96.39p

100C FFhh 1.156 -99.91p 99.91p 0.949 -108p 108p

27C FFlh 0.9791 -76.88p 76.88p 0.801 -82.02p 82.02p

-30C FFlh 0.9542 -73.97p 73.97p 0.784 -77.16p 77.16p

100C FFlh 1.006 -80.15p 80.15p 0.819 -90.25p 90.25p

27C FShh 1.079 -101.6p 101.6p 0.886 -110.6p 110.6p

-30C FShh 1.044 -98.31p 98.31p 0.862 -104.6p 104.6p

100C FShh 1.12 -107.3p 107.3p 0.911 -120.9p 120.9p

27C FSlh 0.9791 -76.88p 76.88p 0.801 -82.02p 82.02p

-30C FSlh 0.9542 -73.97p 73.97p 0.784 -77.16p 77.16p

100C FSlh 1.006 -80.15p 80.15p 0.819 -90.25p 90.25p

27C SFhh 1.052 -101.8p 101.8p 0.871 -107.4p 107.4p

-30C SFhh 1.02 -98p 98p 0.848 -100.6p 100.6p

100C SFhh 1.092 -106.2p 106.2p 0.897 -117.9p 117.9p

27C SFlh 0.9252 -82.7p 82.7p 0.756 -89.27p 89.27p

27C bLSFlh 0.9092 -84.52p 84.52p 0.729 -95.97p 95.97p

-30C bLSFlh 0.8893 -80.58p 80.58p 0.718 -86.41p 86.41p

100C bLSFlh 0.9284 -90.05p 90.05p 0.727 -113.4p 113.4p

27C bLSShh 1.01 -110.7p 110.7p 0.811 -128.5p 128.5p

-30C bLSShh 0.9838 -105.3p 105.3p 0.798 -115p 115p

100C bLSShh 1.048 -116.9p 116.9p 0.816 -152.3p 152.3p

27C bLSSlh 0.8895 -91.78p 91.78p 0.704 -109p 109p

-30C bLSSlh 0.8711 -86.96p 86.96p 0.694 -96.29p 96.29p

100C bLSSlh 0.9079 -98.62p 98.62p 0.695 -133.1p 133.1p

27C typical 0.9894 -90.4p 90.4p 0.801 -98.12p 98.12p

-30C typical 0.9624 -86.31p 86.31p 0.783 -91.06p 91.06p

100C typical 1.019 -95.98p 95.98p 0.819 -106.9p 106.9p

Rise/Fall time is also measured at 10-90% of final value

and this is within the specification requirement. Table 1

listed some of the Rise/Fall time data taken at different

temperature sweeps from -30°C to 100°C.

The noise performance of the LO buffer is also

evaluated and benchmarked against the 3G noise level

spectrum. The following plots shown minimal increments

(~1dBc/Hz maximum) of phase noise at closed-in 1MHz

and 5MHz far-out noise offsets. The flicker noise corner is

also maintains at good margins lower than 25kHz offset

required by specification [8], [9].

Fig. 6 Phasenoise of QMOD00dB for C1=2.1pF

Fig. 7 Phasenoise of QMOD00dB for C1=4.8pF

These results confirmed the advantages of improved LO

Buffer in order to produce wider bandwidth by using a

2.1pF capacitor and change the performance rating of Q4,

Q5, Q4T, Q5T, and Q3 to high-fT transistors.

Further analysis is to verify the stability and impact of

the 3rd-Order Intermodulation Rejection (IMR3) of the LO

buffers performance contributed by these enhancement to

the next Quadrature RF Modulator. Fig. 8 describes the

output spectrums of the LO buffer for 2-tone analysis run

with LO frequency sets at 808MHz and 809MHz.

It is clearly seen that the LO buffer performs its

linearity characteristic very well to reject any possible 3rd-

order intermodulation for variations of IMR3 measured at

< -35dBc at all transmit power levels up to 0dBm average

output power [10]. The LO buffer output IMR3

characterization is performed with different Quadrature RF

Modulator voltage supply ratings called voc varied from

3.0V to 5.0 V to imitate variation of voltages supplied by

external battery sets.


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Fig.8 IMR3 plots probed at open collector Gilbert Cell for

supply voltage variations

4.0 LO BUFFER LAYOUT

(a)

Fig. 9 1.8V LO Buffer


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(b)

Fig. 10 Layout section of 2.7V LO Buffer for 0dB, 10dB

and 20dB Gain of RF Modulator

Fig. 11 Parasitic extracted 2 tones output spectrum

measured at RF Modulator output ports with 4:1 balun

Fig. 12 Layout versus schematic of differential I/Q LO

injection path to single cell RF Modulator

5.0 CONCLUSION

The LO buffer composed of two sections to drive the

LO path of the Quadrature RF Modulator for transmit line-

ups are presented with its layout as shown in Fig. 9 to Fig.

12. The first section of the LO buffer successfully

converts the CMOS LO signals to CML signals and uses

the 1.875V transmit quadrature generator. The post layout

parasitic extracted verifications for phase noise and

linearity are successfully carried out to confirm the

wideband coverage capability at low voltage applications

required by the differential Quadrature RF Modulator.

The utilization of a 2.10pF capacitor and High

Frequency BJT switches in the Gilbert Cells produced

good AC response as observed at emitter-follower node


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with square LO signal at 800MHz to 1GHz. The AC gain

is maintained at 0.3dB and does not significantly affect its

linearity where the IMR3 is measured across PVT at -

42dBc average with output power per-tone produced is -

3dBm. The size of transistors Q10, Q6, Q4, and Q5 are

scaled accordingly to accommodate the power level of

Gilbert cell switch for 0dB, 10dB, and 20/30dB. The phase

noise does increase with 1dBc/Hz but within the

specification of US EIA-TIA Standard for far out noise

offsets at 1MHz and 5MHz.

REFERENCES

[1] “4G Transceiver IC, Networks Enterprise Multiple

Band Multiple Protocol RF-and-Baseband Transceiver

IC”, DETAILED TECHNICAL SPECIFICATION

revision 0.6, June 27, 2008.

[2] “4G RFIC, iDEN Multiple Band MODEM IC”,

DETAILED TECHNICAL SPECIFICATION,

revision 0.2, February 6, 2006.

[3] “3G RFIC, iDEN Multiple Band Transceiver IC”,

DETAILED TECHNICAL SPECIFICATION,

revision 1.2, June 16, 2005.

[4] H. Barry, P. Walter, “Open-collector mixer design for

next generation RFICs, RF interconnect/interface”,

November 2002.

[5] G. Paul, M. Kevin, “3G Transceiver IC, Advanced

Technology Development”, Schaumburg, Illinois,

November 29, 2001.

[6] H. Darabi, and J. Chiu., ‘A Noise Cancellation

Technique in Active RF-CMOS Mixers’, IEEE J.

Solid-State Circuits, 2005, 40, (12), pp. 2628–2632.

[7] B. Gilbert, “The MICROMIXER: A Highly Linear

Variant of the Gilbert Mixer Using a Bisymmetric

Class-AB input Stage”, IEEE Journal of Solid-State

Circuits, vol. 32, pp. 1412-1423, September 1997.

[8] G. Watanabe, H. Lau, J. Schoepf, “Integrated Mixer

Design”, The Second IEEE Asia Pacific Conference

on ASICs / Aug 28-30, 2000. [9] R. Campbell, “An Integrated I-Q Mixer for Software-

Defined Radio Applications”, 2004 High Frequency

Electronics Summit Technical Media, LLC.

[10] S. H. Lee, H. C. Bae, S. Y. Lee, J. Kim, B. W. Kim, J.

Y. Kang, “A1-6 GHz Monolithic Up-Conversion

Mixer with Input/Output Active Baluns using SiGe

HBT Process”, 2004 Topical Meeting on Silicon

Monolithic Integrated Circuits in RF Systems.

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