2.

_1.

4.

5. E.rplain the various blocks of'.a..SiU florvchart.

6. Explain analysis and syrthesis process of AStvl.

7. Write short notes on the follorving :

I)iscuss llre fcarurcs ot.\\N4 ;:r:rl Afil.{ clrarl. (RCpv Bhopa!,:June,2003, Dri.,3orl_,,|:.rpl:r irr dirt:r s1,stt-rn dcsig... r,.,. (RGPY Bhopal, [)ec., 200:llorv will you construct equi'. al ,;'ASM chart for Mealy and Moore nrachine ? Exptair,tlris taking with examplcs of Nleal.t ir..' Moore state diagr ant.(RGpV Bhopul, Jtme; 200,\

(RGPY Bhopal, June, 200: ,

(RGPV Bhopal, June, 200( .

rJL:rt*- ";)\._'- j.

' (a) Firmware algorithm concept'' (O)Algorithmic srate machine.

8. what are some of the advantages and disadvantages ofASM chart /

. 9. Ilorv an SM chart can be reatizc by using a MUX and pLA ?

10. Iixplai^ tlre c.'cept of microprogranl*ecl controlrer.

PRO B LEM S

l. Obrain thc ASM clmrt for ftrltorving lirnction

/. = ,.llJ +. ("1)

(rr) It'rvc ca. put rvrrorc cxllrc.ssirl, irr co'clition box.

(l) If c*ch i'put variablc is ptaccct i. rhc conclition box.

2'. Cttttstrrrct ort.SM blobk thlt has 4 inPut varilblcs (A, IJ, C, D),3 outlluts (ll: A', ]), '.tt

2 cx(patlr.s, lrorthis blockoutput X is alrvays I orrtl Il = AD t.CD'arrcl l, = /,1J, .t CD,.

Convcrt thc statc diagrarrr of Fig. 7.g t to ASM chart.

(o) .o) tFlg.7.B't L4' Draw the ASM chart to describe a Mealy state machine that detects a sequence of l0l0

and that asserts a logical I at thc output during the last state of the seque'nc;.- -- - -' :

5' obtain a state diagram for a Moore circuit which produce output I rvhen it detects the Isequence I l0l . Overlapping sequOnces arc allowed. Also consiruct an SM .t urt fo, ti,t igivencircuit. -"-"'-' "': j----.' '-' "'r._ ir. I

I

I'lL-I

tI

'l

-.i

I

i

!

j

:

,.)rl

I

,.,

Execution of SM block is .............. Vhereas execution of instruction within SM btock is

ColumnlASM chart components

l. State box

2. Decision box

3. Conditionalbox

4. ASM block

Column trSynrbol

I-o-O'-l-rl

=-I

-\

Y

(A)

Gf)

(q

TRUE/FALSE

4. A path through an ASM block from entrance to cxit is refcrred to as a

5. ASM chart for contain only one state box.

flATCH THE C()LUTIII

l. AnAsM chart is a specilication or description of a digital systern

2 state box is a diamond shapcd box with tnre and falsi branches.

3. Execution of SM block is concunent process.'

4. ASM charts are not unique.

5. AsM chart for combinational network contain ouly one state box.

DESCRIPTIVE TYPE QUESTI()IISl. What is the fundanrental concept ofhardware./firmware algorithm ? Explain.

- $Cf Y Bhopal, Dec.,2002)

E)(ERCTSES-7

0BJECTIVE TYPE QUESTt0l,tSl. Thc statc of the system is reprcsr:r.. .a by

(a) Decision box (6) State box(c) Condirional box (r/)ASM block.

2. ASM block is a stnrcture consisting of(a) State box(c) conditionarbox (D) Decision box

(d) All of the above.3. Each data systim consists of

(a) Conroller(c)ASM (D) Data Processor

(d) Both (a) and (b).4. ASM charts can described the operation of

(a) Sequentialcircuit @) conrbinarionarcircuit

(c) Soflware program (rf Both (a) and (6).5. A conditional box is shorrr by

,rrO (rro(c)

(c) Randonr proccss (rrf notr, ("),;i(6),7. Basic ctcrrrcnt for branching is

(a) State box (6) Conditional box(c) Dccision block (@ASM block.8. ASM chart for combinational network contain

(o) no stare box (rt;;. srare box(c) two state box(rf) number of state box equal to number of literats.

9. The Moore output are ptaced in the(a) State box(c) Decision box.

lo fn l microprogrammed conhoiler contror words are hetd in(o) virtuat rrcnx,ry (6)t;;;i;; il.*ory(c) Conhol menr,ry (did;;mory.

Fftt H THE ErAl{KS :

l. .............. is midrvay bctween hardware and software.

6. []xccutiorr of instnictiorr rvithin SM block isj:lj::::::1i:1ryo..'s (0) concuncnr proccss

(6) &nditional box'(d)ASM block.

FYa

0it

tr'.l tlr,.tL

ri.. I t,L,

. [rII

z """""" are equivatent to a state graph and it leads directly to a hardware realization.

-'l.l

l(' r 8rc

, flip'..xfi0

number

'i ed.lf

I, f = I and Ir-1 =0thenX>l'.lf Xn-, =0and Yn-t=l thenX< Y.lf Xn-l=Yn-t,tltenitisnotp,rssible to decide at this stage wheth er X> Y or X < Y or X = L We shill both Xand l/ left by one

t,rr alld compare the bits nroved into ,tn-1 and /r-1. C is a countcr used to count tlte numbcr ofrhi(is in registers Xand l'. Tt. ASM chart of circuit is shorvn in Fig. 7.80.

ASM chart State dia

State diagram is conccrnecl only rvith

sequential system

State diagrams are less volirtlritlous llt:ttt

ASM charts.State diagran$ are unique.

l)

l'+r

lo

ASM chart is concented with digital system

which may be combinational or sequential.

ASM charts are more voluminous than state

diagramsASM charts may have one or more

cquivalent form.ASM chart contain'implicit timing

information.It is often easier to understand the operation

of a digital systcnr by inspection of thc SM

clurt.It ttsc nrorc conrpotlctlts tltatt statc diagrattl

n SM chlrt is ttlorc stnlctttrctl itt ll0tttrc all(l

lcads dircctly to a lttrclrvarc rcalization.

'l'lrc ASM chart spccifi.* ott thc stcps to bc

codcd ond hclps to prcvcnt ontissions or

crrors.

State diagram is not concerned rvith tirne

relationship.State diagram contain less inforn'ntiortas compared to n SM cltart.

It hrs a fcrv cotlll)otlenis.It is often diftlctrlt ttr tlcsigtt thc rlig,illlsystcm by using statc cli;rgratll its

conrpared to n SM cltart.

Statc diagratl$ are lcss crror prollc.

Flow chnrt

l. Flow charts arc usclul is dcsigrrirrg of any

tlpe of systcm.

2 Flow chart is not conccrned with tinle

relationship.3. Flow chart describes the sequcnce of

procedural steps and decision paths forany algorithm..

4. Flow charts provide a clear overview ofthe any type of problem and its algoritlurrIor solution.

5. It use r.norc components of different sizcs

and shapes than ASM chart.

6. The terminal symbol'in flow chart shorvs

the beginning, end or intemrption point

in a prograrn7. Flow charts are most probably unique itt

nature.

Comparison behveenASM chart and stete diagram .

Conrplrlson bctwocnASM chlrt lnd llorv cltnrt .

ASM charts are useful in hardwarc

designing of digital systent

ASM chart contain implicit timinginformationASM chart is a horv chart that defines

hardware algorithm

ASM chart is concerned with digital system

rvhich may be combinational or sequential.

The threg principal cornponents of anASMchart are state box, decision box and

conditional output boxNo such.symbols are used inASM charts.

ASM charts may havc or more equivalentform.

Thble 7.14

ROl\t address Nlicroinstruction Comrnents

0 R, e-0

-

Clear R2 counter

I R, +- R,, Carry +- 0 Clear carry, set status bits2 lf (Z= l) then go to

external addressDone ifR, = 6

3 R, e-crcR, Circulate R1 right rvith carry4 If (carry = 0) then go ro 3 Circulate again ifcrrrry = 65 frz eR, +l,goto9 Ifcarry = l, increment R2.

lixarrrpf e 7.38. Druv'an ASI|I chartfor o nngnirutle contpordtor.

Solulion.

:

Ftg.7.80Two n-bit registers Xand Iare loaded with external inputs. On the start signal Xand.Ir-c

compared.lfx> r'aflip'flopCistobesettot.lfx<Iaflip-hopListobesettol.IfX=lr,a fl.^,.flop f is to be set to l. It is assumed that the bic ofXand-lrare respectivel y Xn_tXn_2...,..Xi,and In-1 Yn-z,,.,, YtYo.

Initially, clear all flip-flops and thc sequcnce counter C is ser to a nurnber 'a'equal to numblrof bits in thc external inputs Xor Y. First MSB of Xond I. namelyXn-1 and yn_1 arcconpared ,t

I

I

X -- lnpulY -- lnput

C.l,,li -.- 0

C--ll

ffi . 11.5.,

Teble 7.13

ROII{ address Microinstruction Comnrcnts

0 A <-0;C +- 0 Clear 8-bits registers A and C

I B +- (00001010)2 Load input to 8-bit register B

2 A+ A+ B The contents of register A are to be added to the

contents of rcgister 8, and the sum transferred

to rcgister I

3 B+B-l DccrementB

4 If (B * 0) then go to 2 Add and decrement if B + 0

5 C<_A Done if B = 0. The sunr transferred to register C.

Exanrple 7.37.ll'ritc the mictoprcgramfor the/low chart given in Fig. 7.79for counting

tlrc nuntber of I s in register R 1

F19.7.79

Solutlon. The microprogram routine in symbolic form is presented in Table 7.14.

t

be

I

Start (Addrcss 8)

Rn- R2+ l

I

t

I

Fi1.7.77,l)xanrple 7.35. Dnnv rlte ASlt{ cltortlrtr XOR gatc,.

Solutlon. Wc knorv that output of XOR gatc is

Z=A,IJ+AB,

]'hc ASM clrrrt of circuit is shown bclow :

.Exrmpre 736. write the nticrop,*trlli;'ira ,n, swn of an the lirst r0, I oit ilJ,numbersfrom (00000001)2 to IOOOOtOtOlr. '"-- "'1

solutlon' The mi^croprogram is symbolic P* i, given below. The variou.adr.rr* ol !RoM are listed in the nnt cotin'u tn oe se-cond colunri, the microirutruction that m,st b" rtir'.,rt each address is given in symbolic forrn The comrneni, ir. used to clarify the register tran rfrslatenrcnts -.v uJls rv rrqrrry tn i

trlIr

:-l

C.A* 0B + A{ul:ipticandQ * MulriplierP ._n

tfl[,!n;"oo C,A*A+ts

Prtx.lucr in A,()

t;

I

a. d its

:

p' ;ined

J

!

ti

I

t

I

II

The state diagram of above ASM chart (Fig. 7 .74) is given below (Fig' 7'75)'

Z=lFi1.7.75

Choose four p flip-flops and label their ouputs

diagram revels the input functions..

Dru=S'To+ZTt

D7,=STn

D,. T, + Z'T'

Dr, =7,

't'lrc logic diagranr is sltown in Fig' 7'76'

s'

7.

T.l

Ft,9.7.76

A flow chart of the operation is shown inFig'7 '77 '

7=O '

Tg, Tb ?n2 and 13. lnspection of the state

z'

T1

Initial Statc

A- 0C-- 0P* n

A <-Alll(l -- C.'rr

Slilft riglrt CAQC--0

In state 2n3, register s C, A and Q.r, lhilld inro one conlpositc registe r CAgani 'ir

contents are shifted once to the right to obtain a new partial produit.

The procedure for multiplication using the circuit shown in Fig. 7.73 andlig,7.74is cxptal e,as'follows: ' i'

c A a B

0

0

0

0

0

0

I

0

mml0l0

0l0l

lill0lllmttm

lll00lll0lll001 I

mlllmt

lmlllm

l0l0

l0t0

l0l0

l0l0

r0l0

l0l0

l0t0

l0l0

Initial value

Shift- First cycle

r1llriLJ

Add I Second cycle '

shift )Add ) Third cy.l" ,

-shift ,

,Add I Fourth cyclq.

)sfiift J

Trble 7.12

ru| {l

:+'L,lr- t

,!

,.t

tr.. -

ron

1;

|ffi t'i{rl

t)rrnrple 734, Draw a,t ASM ,n"n[)n'U'li"o nrultiplier ont! da.rigtr thc conrol logiculng one hot approoch, Exploln how lt di/fers from o convantlonal flow chart ?

(RG PY Bhopal, Dec,, 2007't

Solutlon. ThcASM chart of binary multiplicr is shown in Fig. 7.74. Initially, thc multiplier is

rr Q and the multiplicand is in B. Rcgistcr I and corry flip-flop C urc clearcd to zcro tnd thc

rqucnce counter P is set to a binary number 'a'cqual to number of bits in the multiplier. The(ontrol usc one extcrnal signal ',S' to start the opcrotion. If S - 0, no action occurs and systcm

tmains in an initial state ,S9 when S = l, control goes to state ln1.

AR._ MultiplierBR* MuttiplicandPp * Alt 0's

Pt--Px+ 8n

AR- Ar. - I

Multiplicand

Flg. 7.73 Block dlagram ol mulUpller c-lrcult.

Present state

Qr Qz

Next strte

oi a:Input conditions hfl-lX Inputs

NILIX I MIIX2

,s II

I

I0

I

E

0

00

0000l

s'.s

0

0

0I

It000 z'

z z'I 0 I I None I

I

II

I.l 00l E'

E E'

ffi

. - Errmple 733' Draw an ASM chartfof'f l,!i", ,ircuit that tnurtipries nvo binary nr^brrrl,by the repeated addition melhod.

Fore.g., 4 x 3'= 4 + 4 + 4 = l,2.

't'l

Tl/rris

0

I

E /

a. t.'lt-solutlon' The system consists of,fu".r:.gisters.-r{4,

f^ *.d p4 where multiplicand be in;register 84' the multiplier in register Ap and tf,. prooui in'registelpn:il; conhol *., onr l]external input 's to start thr oprr.tioo *a o5 rr;t* ;;;t z is the output of a zero detectioncircuit' Adder circuit adds tbe contents gf t^,g 4. 'ilr value in z ischecked by the z,,rcf:;detection circuit whenz{p becorrs zero after Ji,.n iifi, irgirt r;p is decremented by l. L

TheASMchartofcircuitisshown u'figl.tZ. il

NIUX I

I t,tuxz

3

{

a-r l.-ldntflf,f

".ll as.J'( -.;an

ching

Ii,

I

,J

I

l

,lI

l

:l

I

ir'u J

Example 131. Design the ASM chartfor JKflip-Iop.

Sotutlon. We know that characteristic equation of JK flip-flop is

Q(+l)= tOfO+RQ0

The ASM chart of JK flip-flop is shown belorv.

F19.7.69

Ilxnrnplc 7,32. A systcn contisting of two ragistars R 1

ancl R2 nui n fiip'llop E counts the rumbcr ol I I loaded

inro R 1 ancl sets R2 that nuntben Draw the ASI'r chart forthe syitents and design the control circuit MUX'

(RG PY BhoPal, Dec,, 2007)

Solutlon. The systcm consists of two registers R1 and

R2 and a flip-flop E. The control uses one external input 'ltoslart the operation and two stitus input 6 and Z. E is the

output of the flip-flop andZ is the output of a circuitlhatchccks contents of register R 1 for all 0's. Esbh bit from register

R1 is shifted one at a time to flip-flop 6. Tbe value in E is

checked by the conEol, apd each time it is equal to l, register

R2 is incremented bY l.

TheASM chart of circuit is shown in Fig. 7.70.

Q(ttl) - I

R1*lnputRr- Alll's

Rr<- Rt+l

F19.7.70

rT

I

@@Norv rve considcr that cnrcrgency vehicle is coming. I{ere we willglow red for NS as r*,eli s

for EW rvltcn enlergency vehiclc is present. Secondly, rve rvill allorv output )', so that u,e < ;rprovide atrdio sound, so that other witl come to know about entergency vehiite. At each switchingrve n'ill check per emergency signal (8"). Therefore, ASM chart will be

EW - RcdN.S - Crccn

EW - RedNS - Yellow

L

ftt,{t

t:L.

F19.7.68

re

()..

,ll1

'ts ,,l

in

)I 5,psi

n8nor

i

;

s ihee''tlsi- g.

ith"Lri ls

tlrvhq

s;'

tatllcr

:

iiI

r_t-l

I,iI

l)uring the data system designing, designcr should consider the fiollowing points. .

l. Cost: depending on the nature of the systerq the designer must sclect the most economicalsolution for the givcn systenl

L Efficiency : Data system should be eflicient, having low propagation delay i. e. fast responsetirne.

3. System should be reliable and must have some securiry measure to protect the sensitivedata in protected location.

4. The structure (hardware configuration) is modular, regular and independent of the particularcomputation.

The block diagram is shou'n in Fig. 7.67 which indicates that horv a digital system controltlrc physical systeft.

F19.7.67.

Exanrplc 7,30. Devalop ASM chartlor trottrc signal controller ut thc intt'r:;eclion. The

y*'n/rcd lights shoulds bc ONfor 30.tcc arul yellox, light should be ON for l0 scc. l'laka

ltnvislon for oil cntugancy vahiclc lo pass through hy stopping truttrc d rcquirad,(RGPV Bhopul, Junc, 2006)

Solutlon. First wc will tske scqucncc of traffic. Wq won't considcr cmcrgcncy condition.thcreforc our tralTic signolling schemc is os follows :

(a) EW - ReC 1' I 30t..NS - GreenJ

(D) sw -.Red :1 -NS -y.llo*J )tt'

(c) rw - Yellowl

NS -Red J)sec(.ft gw - Greenl ^^

NS - Red J ru sec

(e) rw - Yellowl -' NS-Red J)sec(rEw-Red l -

NS -Yruo*J )tt'

Now, continue from(o)

l. In nricroprogramming approach the overallspeed of the system is lou,.

2. Ir{icroprograttrnilng provides a rvcll strucfured control organization.

3. It is more expensive than hardwired (fixed network).

4. With nticroprogramming nuny additions and changes are rnade by simply changing thenucroprogram in the control tlremory. A small change in the hardwired (fixed nefwork)approach may lead to redesigning the entire system.

5. Microprogram control organization is more efficient in large, complicated systems.

7.8.- DATA SYSTEM DESIGNINGData systenr processes the data and produce the required output. Each dara systenl consists

of controller and data processor.

The relationship between control and the data processor i1 a data systenl is shorvn inFig.1.66.

l:rtcln.rl

--lnputs

controltcr is a sPccial scqucntial .,r.,1',0;t1;l6r..riu., input fronr coch coprponcnts of t6csystctll lttd outcr irttcrfacc ond gcncratc thc control signals thlt control thc opcration to bcpcrftrrntccl by thc data proccssor. Tltc data proccisor part may bc o gcncral-pfirposc proccssorunit' or it rrray consist of individual rcgistcrs ond associoted digital functions.

Design of a digital system can be dividcd into two categories, first part is design the dataprocessor which stores the data in the flip-flops or register and second part is design a controllerwhich control the corrcct operation of sequence to be performed Uy ttre data processor.

Before designing the data systerq designer should know very well, what the system worksand what is the need for sptern In general design a data system involves the following steps.

l. Given the word description of the requirement obtain an algorithm necessary for solving adesign problern Algorithm may be in the form of flow chart, ASM chart, state diagr"- ottable. orHDL.

Z From the algorithm determine the various components required for designing, such as thesize and number of flipflops needed to store the inf6rmation and the kind of operationalunit such as adder conparaton etc., which af necessary to perform the required processing:.'

3. Generate the timing diagnm which will conbol the sequence of different steps ofatgorithmA timing diagram clarifies the timing sequence and other relationships among thelariouscontrol signals in the subsystern

4. Synthesize the controller to generate the timing signats.

5. Test the system with appropriate test signals.

i:''!,

t

i

It*,I

!,j!,. IL'

,t

tlt!{t-l1"',I

L

lnputs

.Stiltu$ l0 for0litt ion

Outputs

l);ttit l'roc'csstlt

t$rN

i :'&in?' '

?.t

"t

i

I

rTI lll

'l

I

t:l'

7.7,6. I\{icroprogrammed controller. In a microprogrammed controller, control words are

lcld in a separate memory callcd the control memory. Each control rvord contains signals to

uctivate one or more miciooperations when these words are rctrieved in a sequence a set ofrrricroperations are activated that will complcte the desired task. The set of microoperations

lrrricroinstructions) for the control of a computation sequence is called microprogram.

Structure of a microgrammed controller. The structure of a typical morden

rrricroprogrammed control unit is shown in Eig.7.65.

Flg. 7.65 A mlcroprogrammod controllor'

ClvlBR (Control Menory Bttllcr Ragtsitri,'t'tt CMllR functions tltc sntttc as thc MBI{ of

rhc main mcnpry. It is bosicsttya taictr, on.l o.t os I buffcr for thc nticroitrstructiotts rctricvcd fronr

thc control rncmory. Each microinstnrction will hovc thrcc distinct ficlds

Conditiorr selects

Branch address fieldControl function field.

The condition select fie ld selects the external condition to be tested. If it is true, the output

of the multiplexer will be l. The output of the MUx is connected to the load / Inc input of the

microprogramcounter (MpC). If the output of the MUX is true, then load input will be active and

rhe MpC will be loaded with the uidrrs specilied in the branch address field of the

microinstruction. If the output of the MUX is false, then increment input t t"t I will be active and

the MpC will point to thc next microinstnrction to be executed. Aconhol function field gives the

values of the conhol signals.

MpC (Mtcruprogrsm Counter).. The tlpical functio'n ofthe MPC include incrementing the

current address by one, transmitting .n r*ir-ally specified address, generating a computed

'branch ad&ess, or speciffing an initial address.

Exlernal condirlon select MIJX.. This MUX selects one ofttre external conditiors according

to the contents of the condition select ficld of the microirutruction'

The conparison of a microprogramnrd controller with respect to a controller implemcnted

as a lixed network are as follows :

nr,.rnol fconrrol

[_

Controllrurtclirln

lricltl

Contrtll .Sign:rls

Exampfc 7.29. Design the ci,rtuol hgic c{Fig. 7.61 using pLA.

Solution. 'l'lrc statc lahlc corl(..3rr,:rrling to thc ASM chart of Fig. 7.61 is shown.rilhblc 7. 10.

'l'he I'l.A progranl rablc is strorvn in'lirblc Z. I | .

I

Table.7.l0

Prescnt State

Qr Qz

Ncxt State

Q*rQ'zInputsxy

OutputsTo Tt T2 T3

00000l0lllllltt0l0l0

000ll0ll00ltt000t0rl

0xlxxQxl0xltl00xl0tl

1000100001000t00000100010001001000t00010

l'lblc 7.1I

I'rotluct lcrnr . Input.r

l2 34h Qz .f,' t'

Ou(puts

123456Qf Qf ro r't r'2 r'r

I

2

3

4

5

6

7

8

9

l0

0000 0 l-0 I -00 I -lll0l I ltI I l0I 0 0-l0 l0l0 ll

t-ll

l-t-lll-

Itlll- I

l-l-l-

Ir r I -lThe block diagramof PLA conhol is shown in Fig. 7.64.

| .l22l

PT.A A3'5

46

F19.7.64

,lttrl

np Enffii-.1.--

tl

-)ToI

lr,

-,T.,rl-il-, _;r3

-l

I

I

to the next state and outputs in theflip-flops for the sequence register.

The following example demonstrates the procedure for designing the conrrol logic rvith aPLA.

Exanrple 7.28. Derive the PLA program table for the control x,hose st.tte tdble is gi .,en inTable.7.8.

Table.7.8

Present State Nert State Inputs Outputs

Qr Qz hQz .ryz ToTtT2 z

00

00

0l

0l

ll

ll

00

0l

tt

0t

00

0l

0xx

lxx

xlx

x0x

X X 0.

xxl

1000

1000

0100

0100

00 t0

00 r I

Solutlort. 'l'hc I'LA progrsnl tablc can bc obtaincd dircctly frorrr the statc tlblc witout thcnccd for sirnplilication proccdurcs. Thc PLAprogrom tablc is givcn iq'l'ablc 7.9.

Trblc 7.9

Product

ternr

Innuts Outnuts

I 2 3 4

v5(.QrQzx

t23456QrQzToTlT2z

I

2

3

4

5

6

00

00

0l

0l

ll

ll

0

I

l-

0

0

I

II

I

I

I l-

I

I

number of

;!

i

II,I

I

ilIII

I,ItIJ{It

I,le fronr

h I)[.Aitrons.

I

,1i lftfi, inputs

, ^lor-rt .fthe'om the

te tabte

itrcs no

tinus to

n't carc

n rdto'L.rt are

ui'alent

state table. The numbcr of states detennines the

L ,

I

NIUX2l

3

srI

Ft1.7,62

. 7 '7 's uslng P!4. 'l'hc dcsign ofa I'}LA control rcquircs tlat rvc obtain rhc storc tablc fror:tlrcASM chart of thc circuit.'Ihc biock diagramofrhc pl.l\controlis shown i1l;ig. 7.63.^I-heF tnlcthod is supcrior to o RoM if ttrc statc tablc contoins largc nunrbcr of don,t carc conclitioru.

Oulput$

Flg.7.6s.The state table gives essentially all the information rcqufued for obtaining the pLA prog{,:m

table' The PLA progftlm table is a list ofproduct terms, one for each row in the state table, infurand their corresponding outputs. For eacch product tenq the inputs are marked with l. 0 q-,-(dash)' A I in the input colurnn specifies u p.tt from the corresponding inputioilffil;lj;AND gate that forms the'product term. A 0 in the input column specifies a path from thc

. c-oresponding complement input to the input of the nNO gate. The ,X,s in the state ta' lc'designate don't-care conditions and inpry no connection for the pLA. A .-'(;;;J ililUconne-ction in the program table. The 0's in the output columrs also indicatc no connections tothe OR gates within the PL,A. ""1','

The conversion of the state table to a PLA program table is ycry e8sy. The don't clicconditioru in the input columrs and the 0's in the nextitate and output colu,urs are change<, ;o'-' (dash) i.e. no connection and all other entries remain the sanrc. rhr input to;;'ifiir;cquivalent to the prescnt state and inputs in the state table. The outputs ortm pu are equiva[enr

0

I

2

3

t

c .tfttr

1.l

I

I

:

\

_Ir.{- 'o,-)

-Tr- l-T'

-T1

i

II

't Jz)

.:

Flg.7.6l

Thc cquivalcnt ASM chart of Fig .7 ,60 hai four blocks-onc for coch statc. Fig. 7.61 shorvs att

SM chart for tltc statc diagrum of Fig. 7.60.

Trble 7.7

Prcscnt State

hQtNext Statc

Qr Qz

Input C6ndltlons MUX lnputs

Mtxl MT.D(2

0000

000l

x'x

0 r

0l0l

lll0

vv'

I v

llllll

00lll0

x'ryxy'

ry * xy'

=x

xy

l0l0l0

00l0ll

x'xy'xy

ry'+ry=x

x)'

I.r)gr( diagramofconEol unit is shown in Fig.7.62

The MUX inputs from the table are used in the conhol imptementation of Fi g.7 .59.

0

I

MUX I',

3

0

I

2

3

sr- so

MUX2

Ftg.7.S9If xnrrrplc 7,27, I'hc state liagrum o/ a contrcl unit is slrcrr,tt belox,.

t=lI=l

x=lI=0

Ftg.7.60(a) Draw the equlvalent ASM chart, leaving the state boxes empty.

(b) Design the control using nultiplexers,

Solution. (a)

(RGPI, Bhopal, June, 2007)-

I

xt

x.000

,A-aQ

I

,l

,'|1:Effi'rnntr0l

I

.l

peption

I,t

I

. 'isa'gister.

'r '' has

: .rlly)of the'r iionIt ,!the

L.Y, O

I

,

I

F19.7.58Solutlon. Tablc 7.6 gives the infornration for 0reASM chart ofFig. 7.58. The input conditioru

listed in the table arc obtained from the decision boxcs in the ASM chart. Thc two colunur undcrMUX inputs in the table specify the input logic that must be applied to MUX. The MUX input fo,cach present state is dctermined from the input conditions *tln the next state of the flip-flop isequal to l.

Trble7.6Present State

Qr Qz

Next Stete

Qr Qz

Input Conditlons MUX InputsMtxl MTIX2

000000

l00'lll

xx.' y'x'v

,+x'!*x* y

x'Y * x'Y'-- x'

0l0l0l

l00lll

xx'yx'y'

x * x'y'-x*'l'

x'Y * x'Y'=r'

l0l0

t000

r''x

t 0

llll

tl00

x'x

x' I

t

,Z=0

Example 7 '25' The state diagran, of a control unir is shorvtr in Fig. 7.56. Design tlte contrrib),the oneflip-flop per state nrethod. ' '6' "-"'

I

sotution. choose five Dflip-flops."iilot itneir outputs To,Tt,72, T3and ?"a. Inspecrionof the state diagram reveats the input hrnctions. ' -- - u' ' r " z" r

h=0D7t To + z' Tz

Drz = Tt

D7r=zT2

Dt't Tl + Ta '1'he logic diagranr is shown in Fig. 7.57.

F19.7.57

l"l:1.r-.u*rJiilti:lers. tn $r.:g:9_l-"qi. sares are reptaced by muttiptexer. rt is

H: : ::::',',: :ff: 3:,T1 ! ::l ^' " r i s ts or MUX ;;i il;;' ;'; ;:; J#"'ffi "d

j t*t t-1t-"11 level contairu a.register that hold the pt.r.niuinary srate value. *. intro ,:;:il::. rrv lrtla\r rgvgl lla,\

*:ffi liiffi:1?'i:::l*::""*"l*Trif-T:":,tTt:-:i"_'ry:F-i[-n;;;;;;ili,ffi il:i:i::T"_1fjj'^linputsandarsotlrheserectioiri",;;?;;;ffi i:ffi ;#il"iu{l11H ;t;T::Hl'"l"" 11e- f IrIl ;1n:1s The

iny uts f nn* a re de termine iffi ;,i, ffi ff .

L:Xffjrr:,t:gg:ru givin in'thosM chart. in order to crarify,r,, pror.i*"'.;fffi:.,'ilifo I lo wing design exanples.

Errmple 7.26. Design the control whose ASM chort is given in Fig. 7.5g using MC2X,rcglste4 and decoden

il,l6lII

II

-t

:l

iI

1l:l:,

a(

lr

ii-!Itt,'a

II

'''l q

liI

1III

1i9'EFtii r- !_;

j.!

controlr gular

,inbcre necd

I.l munl

srln of

It stale

n..nd is

tc ANDI ntot'arr1 wc

'I

I'I.-J

'I

\

rii .,iri*r,.. i ' .. 1 7'33 1

Dro=x'7'6-77Df, = x T(l

Dr'- = Tr^'z :u7, =), I2Dfo = TtDrr, : )rr2Di =TsD; = Tt+ Tr,'

The logic didgrarn is shorvn in Fig. 7.55.

clcar clk

F19.7.55

mQrQo QrQo

Ft,1.7.52The input filnctions to the D flip-flops can also be expressed as follorvs :

D1 : x'71Dg= x I T1.

rvhere To: Qt' Qo', Tl: Ql Q6 and Tz: Qt QzThe logic diagram of the conrrol unit is shorvn in Fig. 7.53.

7.7 3. Uslng onc fllp-flop per strtc. iiiir #ilt"d uscs one flip-flop per stare in rhc contrft I

scquential circuit. Eoch flip-flop represcnts o statc ond only one flip-flop is sct at any particul; i

time, white all others are clearcd. The advantage of this method is sirnplicity with which it can t . :

designed. The control unit logic can be derived directly from thc state diagram without the need l

of state or cxcitation tables. The rnain disadvantage of this method is 0rat it uses a maximu , ,

.nurnber of flip-flops. Considet some specific examples that demonstrate the detailed design 0.liconbol'units by this method. I

Example 7,24. A control unit has two inputs x ary! y and eight states. TIte controf rro;:ijdiagram is shown in Fig. 7.54. Design the control using eight Dltip-flops.

L

000t il t0

0

I

0 l 0 x

0 0 0 x

Dr = x'Qr'Qo

000t il t0

0

I

0 0 X

I I I X

Do=x+Qr'Qo

F19.7.53

t

*=9r- Y= iln"iI

Solutlon. Thc condition for setting a givcn flip-flop is specified in the state diagram and - .

i

obtained from the conditionspecified in the directed lines going into a given flip-flopstateAND'!(logical and) with the previots flip-flop state. Iftbere arc more than one directed tine going into ,'lstate, all conditions must be logicat Oifed. Using this procedure for the giveri st.i. Ai.t i*';,'obtain the input functions.

F19.7.54

ltr.l,lrl

rI rffi l-l:lrl

To = Qo' To = Qr'Qo

Fig.7.50The logic diagram of the control is shown in Fig. 7.51

F19.7.51

7,7,2, Uslng D fllp-flops snd dccodcr. Thc nuin advontage of this nrcthod is that wc con

drrcctly obtain thc input functions from the statc tablc without the nccd of an cxcitation tablc.'llris is bccsusc thc next state is the samc as thc input rcquirement for thc D flip-flops. Then,tnstead of using the flip-flop outputs as the present state condition, we nright as wcll usc the

output of the decoder to supply this information, for that insert a decoder at the output of thc flip-flops to obtain the necessary outputs. Now realize the conhol unit using gates, flip-Ilops and decoder.

Examplc 7,23, Design lhe contrcl unit whose state table is given in Table 7.3 using logicg,iltcs, Dflip-flops and decoder.

Solution.

Tl=Q:

Teble.7.5

Present StateSyntol

PrcsentState

Input NextStatc

Flip-tlops. Inputs '

Output

hQo x Qr Qo D1 Do To TtT2zTo

To

T1

T1

T2

T2

00000l0lllll

0

I

0

I

0

I

0

0

I

o0

0

0

I

I

I0

I

0

0

I

0

0

0

0

I

I

I

0

I

I

I

0

0

0

0

0000 001001000r00ll

The srate tabre corresponding to rhe AsM chart (Fig. trtl ,, shown in Tabre 7.3.Tablc. T-3

lablc. 7 lhc. excitatiorr rable ol.rhc nitnolrm

9r%

Joo'

simitarty, the ttuee sinplified outpur 0x1,1;1i *,To- Qo'Tt - Qt' QoTz'Qt

PresentState

Synrbot

PresentState

Input NextState

Output -

hQo .r Qt Qo ToTtT2 z

li iI000ltt0l000t

t000100001000 I 0'000t000tl

4 shorv

'Iirbte 7.4

0.0000t0ll. I

tl

I'rcsenl Stnte Ncrt Strte Flipfloplnpurs

4 Kr Jo Ko

oxoxoxtxlxxO0X;0xlxtxlx0

0

I

0

I

0

I

000tIt0t000l

000t il t0

0

I

0 I X x

0 0' x x

Jt = r'Qo

00 0t tt t0

0

I

x x I x

x x I x

Kt=l

000t il t0

0

I

X 0 I X

X 0 0 X

It = r'Qr

00 0t lt t0

0

I

0 X X x

I x x x

7.7,1. Uslng JK flip-flops. The following procedure can bc used for connoller dcsi:d.i,e.rhm'rt $el"ons

3en

r uits

)utl'ef3c,th€

Irl' iy a

r'.rry,r. -: ofdware

r notls not

l^vc a

v l,cr,

using JK flip-flops :

l. The first step is to assign binary values to each state in lhe ASM chart.

2. .Obtain the state table for a controller. A state table for a controller is a list of prescnt slnlcr.

inputs, their corresponding next states and ouputs. The inputs are taken frttttt llrc

conditions in the decision boxes of the ASM chart. The ouputs are equivalcnt to tlrpresent state of the connol.

3. Obtain the excitation table of the flip-flop inputs'

4. Find a simplified expression for ouput and the flip-flop inputs'

5. Realize the control unit using gates and flip-flops'

ln order the clarify the procedure, consider the following example.

Exarnple 7,22. Drav,an ASI{ cltart ancl state diagram to describe a sequence detcctttr tlrttt

detects a seqye,rce of " l0l ". Design the control unit using JK flip-tlop'

Solution. Figure 7.47 gives the corresponding state diagram for a given seqtlence dctce tor'

0rt) .. (\z----T1'l'o

ttv f* \

-*_-1.|r\ \i./ (Y()

o/()

' F19.7.47

l:ig. 7.48 givcs thc corrcsponding ASM chart for I givcn scquctlcc dctcctor'

vlt/0

; ttcd

l,-kccl

I

I: rory I

torrgcr I

rt ts of;1 ternletailed

QrQo'0

QrQo= 0t

0 QlQs= ll

F19.7.48

t'

Gencrally an algorithm rvill contain a number of procedural stcps which are rcsult-oriented i.e.depcndcnt on results of prcvious steps. A convenilnt method foi presenting hardware atgorithris a flow chart. Flow charts are uscful in the hardware design oidigital slystem. It convert thegiven word information to an information diagram that enumerates ih.. r.qu.nce of operation-together rvith the conditions necessary for their execulion. A special flow chart that has beerdeveloped specifically to define hardware algorithm is cailed an ASM chart.

Firntrvare algoritlinr. Firmware consists of programs that are included in digital circuit ,during their manufacture. Firmware is used u'hen ttre programs must be retained in case of pog,e. \failure and rvhen programs are not expected ro ue ctrariged. The microprogram facilitates thgirnplementation of hardlare and is therefore, called firmware to distinguistr i-t from software.

A microprogrammed computer has its centralprocessing unit intplemented primarily by aRoM rather than by discrete logic. Each nrenrory location in tlris Rolv{, c:rllecl a control nremorlholds a nricroinslrttctiott, the torvest leve[ instruction a conrpqtcr can exe,:r(c. A sequence ottticroinstructions is knot',rt as a nricroprogranr or finnrvare. A firnlvare is rpitlg,ay btt*,een hardrvareattd softrvare' Wc'cart cottsider nticroprogranrnring as softn'arc lha-t cap irrrpler'c.'t frrnctio's noprescttt in thc hardrvarc. Microprogran$ can be ctranged in trvo \\,ays. ll'rlrc ct'rptrolrrrcnrory is no,RoM. tltc ttscr catt rvrilc il llelv scqucncc of nricroiristnrctions inro it. 'l'lrc c.rrrputcr.ury lravc aprogl'atll tlt:tt catt altcr thc ttticroprograttt stureil in thc conrrol nrclrory. llsu:rlly,5or'cverttticr.Pr.gra.Ls ilrc clrl'gctl by clrnngi'g thc co'trol r'crrxrry.

Itt a ltorizotttllltticrtlittstruclion (l:ig.7.46), cach controtsigrral witlirr r6c CI,U is rcprcsc.tcr'b;,' nttt ltit in thc cotltrol lickl, In attotltcir lbrnr of nricroprogranrnring, callcct vcrtical or plckc<-rrricroprograttttttittg scvct'al cotttrol sign:rls arc cncodcct into a srrurllcr

'urrrbcr of bits.

vcrtical ttticroitlstntction tlttts ltas thc aclvarrtflgc of dccrcasing thc sizc of co'trol nlcnlor)j]lllf:L:'111.9:::1':rpl"ving cliso<lvarrtagc of-rlccrcascc ncxiuility, sincc it is no longcipossiblc to havc irrdividual

'cccss to cach corrtrol point.

Nlicroinst ruct ion address

Jump Condition

Systenr Bus Control Signals

Internal CPU Conrrol Signals

Microlnslructlon

(b) Verllcal Mlcrolnstruction

f

I{

:

I

T,T. coNTRoLtER DE'TGN Fis'7'46

''- |

system controlter is a^spccial sequential circuit that receives input frorn each component, or j

thc system and outer interface and ginerate the control signats that control the whole systern -The subsequent sectiors of this chapier deal with rp..inr r*amplc tbat demonstrate tbe detailed ,dcsign of conuol unit. ..-r ewr'rt'':rucls lrrq sgratle11 '-

(a) Hodzontal

tt

,!

,el :j

tt. ')I,:

--l

II

l:

t:i:--l J-;---

t.

II

hd

)"

r, r:nul:hnntlfan

Solutlon.

Ft,g.7.45

In thc Fig.7.45,

Count r nunlbcr of pcoplc in o room

ifx-lnoentry- 0 peoplc entcr the room

if y - I no onc leave the room= 0 people leave the room

M = Mode select

M :0 fer up counter.

M = I for down counter.

1,6. HARDWARE AND FIRIAWARE ALGORITHNilSThe most challenging and creative part ofthe design ii the establishment of design objectives

rnd the formulation of algorithms and procedures for achieving the given objectives. This task(rnnot be automated and require the mental reasoning of a lluman designer. Dcsigner cannot&vclop algorithm without.

.1. Thoroughly understanding the problem

2 Assuming initial conliguration of equipmont for implementing the procedure.

Tbe algori0rm is stated by a finite nunber ofwclldefined procedural steps. Thts an algorithmn o procedtue that specifies a finite sct of steps which if followed give the solution to a problern

Hrrdwrre rlgorlthnu Hardware algorithms arc used to specify thc control sequence and.hta processing tasls of a digital systern A hardware qlgorithm is a finite number of wclldefinedpocedural steps that specifies how to inplenrnt a problem with a given piece of equipnrnt.

Up-downcounlcr

Exanrple 7.20. Draw the ASM chart of a 2 bit up-tlown couttter *,ith eilcrnal reser inpur.Solution. when up is high, count sequence is up i.e. 0 - I -2-3-0..... and when up is low, thecountcr $'ill count-down" i.e.3 '2 ' | ' 0 - 3..... . As the counter must reset back to initial state .,00,,

when external reset input is high.

L

L

Erampfe 7,21, c'onstntct an ASM yTi;'if ".digital

,)src^ that counts rhe number ofpeople in a room' People enler the roomfrom one dooi with a photocell that changes a signalx from I to 0 when the tight is interruited. They leave the room from a second door with asimilar photocell with a signal y: Eoth x and y are synchrcn4ed with the clock, but thq maystay on or ofifor more lhan one clock'pulse piriod. Tie data-processorsubsystem consists ofonup-down counter with a display of lls contents.

Lint 3',,

tl.in[.5 i

o Att-to

l-t

.t

1.t

j

F19.7.43

Tlrc next statc and output equations using thc state sssignmcnt

Ss,AB -001 SyAB -01;.12, AB-ll;Sj,AB - l0;arcgivenby

Output Z = 18"N,linl 3

The next statc ofl (,,{+) is

A+ =Vgx+M+@lin& 2 lanl a linl I

= ZBX + ABX + ABX + ABX

= BX(Z+ 4+ ABV + N)

= BX+ AB

The next state of I (B+) is

n* = 7Ex + AEx +7ax + ABXlinl I lint t linl 2 linl I

= Ex(Z+ O+ BX(Z+ A)

=X(B+B): )(,

(ldernpotent law)

Norv to form SM chart from abovc state diagranr, for each states draw state boxcs. Now afiereach state boxes put the inputX in decisi,,n box. Put the output in conditionalbox in patl whereit will I and connect next state links. Fig. l.';J .''rorvs an SM chart for the state diagram given inFig.7.39.

The next-state and output equations using the state assignment

So, AB = 00; 51, AB = 0t;52, AB: I l; are given by following equations

Ouput Z : A BX (from link 4)

The next state of 8 (B+) is

r>+ = ABX+ABX+ABXu

link I lin! 2 lin! 3

= |EX + /gX + \AX + ABF (lndc.mpotent larv)

= 786+B)+ oXG+ el

=17+B)X'l'hc ncxt sratc ofl (ul+) is

'+ 47oX + ARX = IIXlinl I linl l

I;ig. 7.41 shows tlrc rcalization of SM clrarr.

ct(rcx

F19.7.41 (

.. . . ^ Ptltple 7.19. Draw the ASM chart of a sequence detector to detect the input sequencQ" I 10". Derive the next state and output equations by tracing link poths on the ASM tiort.

Solutlon. It

t

I

clock

I

0

F/ig.7.42

ilE;-.i,,1'1

r state

i'rillt

_l

f'l,lrj

I

.1

_t

:lII

II

I

FNcxt, rvc will realize the SM chart using D flip-flops and logic gates.

clock

Fig.7.38

Exanrple 7.18. A sequenrial cirruit has one input and one olttlrut, giles oulPut I wltttt ilr(,ceir.es input I followittg u .sting d tt'o or lltree const'culit'e irynl 0. I)tuv' ttntl rculi:t' tltc Sllchurt usittg Dflip-flo1ts ttnd logic gatas.

Solutiott.)

.S,,

|/0

vl

Link 2

0/(l

Link I i

IIIII

s2

LinkI

4:

F19.7.39

I

9i

Flg.7.40

v0

! Alt=g1

Fig.7.36Now to form SM chart front Fig. 7.36, foieach shtes drarv state boxes. Nowafter each starboxes put the inputxin decision box. Put thc ouput in conditional output box in path where it r,,i;I and connect next state links. r -- ----

output z=ABX(fromtink5) Fts'7'37' :

The next state ofl (l+) is

A' = TLx6omtink t) + ABV(from fir* +lSimilarly the next srate ofg (B+) is :

. a+ = lt4x + 4aj + 4px + laXlinl2 linlt ti*t fnit

= ZEx + 1ax + ZaX + ABX

= 7x(E + q+ BX(Z+ A)

,l..

tt,l'L

tI

L

I.l

'I

=7x+BX

-)

v,wrfiqput'l 'lnce

:

I

t't;).)iIt,l

;

ffi

Flg.7.Qs

Exanrple 7.17, A sequential circuit hasine'input x aircl one oulprtt z. Outpttt z : I , i/'total

nuntbcr of t in the input is divisible by 3.

' (a) Draw the equivolent state diagrant

(b) Convert the state diagram to SM charts'

(c) Realize the sM chart using a D tlip-flop aud logic gates.

I glven ,

i

(,i pul

| (Fig

Exemple 7.16. A sequence recognizer has h+'o inputs (x and y) andone output (z). If inputsequetrce of pairs xy = 11,00,10 the output v'ill be l. Draw the AStl chart of a sequence

recognizer.

' Solution.

Fig.7.33We rvill solvc thir problenr by first constructing a statc diagranr 'l'he statc diagranr for giver.

sequence recognizcr is shorur in Fig. 7.33.

Norv to forruASA{ clr:rrt for cach statcs draw onc statc box. Norv alicr clch stiltc boxcs pu

thc inputs in dccision box. I)ut thc output in conditional output box in paths rvhcrc it will I (Fig7.34). Conncct thc neet statc by link by inspccting statc diajrant as sltowrr in l;ig. 7.34..

F19.7.34

The conpleteASM chart is shown in Fig. 7.35.

I

L

I

-:, f-

t tl

,.|

y'os

phI

Flg. 7.32 (b).

ttce of pairs xy = 0l,0t.tt. 00 -r' -- YrY"e"ec 'selscquence of pairs xy = 01,0t,tt.00. (RGPV Dltopal, Jurte 2004

.::';fi:;-T..:'::::::."i::rl!, by nrst consrucrine a sratc diagranrthe state diagram for a sequence rccognizer.

. Now lo fornr sM chart' for caclt statcs ;:tJil. srate bo.xcs,

'rrr our'ut i^ rrrc srarc rr..x. r)uri'put i'ttccisitlrt bo'r aticr caclt statc bo.x an.l conncct trrc

'c.rt statc ti'k by inspcctirg srarc. graprrffl1lil'i;,i;,i.-ij i:!;l;itr'a

tro't rbrst:rrc^ i,;i;,"n in rrig ?3;i;;'\rrccor'prcr..tsr,,,

Fig. 7.31 gives

il

7.32 (a).

rI

I

t-I.t.L-

:'I

L,

(II

L

I

J

r-\(}\Ys ---

/ p D-;7t1l+ t 1

1o,/

,\,

--"1:{;.

;,t/o

1,r5

,.q6

tate

.t'I

I

lrIIr

a-

'm .,1 wl1Solution.

F19.7.29

The state diagram for given system is shown in Fig' 7'29'

S,.'

t7tl

F19.7.30

NowtoformsMchart,forcachstatedrawstateboxsndputinput in decision box after each stttc box and connect the next state

Ji"gra* The ASM chrrt is showu in Fig' 7'30'

the output in statc box' Put

link by insPccting thc state

Table 7.1 shows the transition table for Fig. 7 .26. Table 7.2 gives thetable for Tablc 7.1. Wc have madc the state assignment Q = 0 for S9 and Q =

corresponding stateI for 51.

Teble 7.2

Present state

oNert state (Q+), S

X1Y1=00 0l l0 llso

.Sl

So, o

sg, I

So, I

51, o

So,l

51, o

.11, 0

St, I

A state graph for a sequential machine is shown nFig.7 .27.

I t/0

lt/t0 l/0tu0

00/t

F19.7.27To drive SM chart frorn Mcaly state diagranr, fornt 2 statc boxcs for cach statc 56 and 51.

Aflcr caclt state box put input in dccision box and put corrditiorral output box in thc path whercMcaly outputs arc l. Fig. 7.28 givcs thc corrcspondirrg SM chart for a givcn circuir.

t

rIII

t'..

t

F19.7.28

00/00t/lt0/l

(

I

L

II

I

'',,wsynchronoussequentials7stemhg'tnoinputsXandYandoneoutputZ'',wh.en the sumfr the inputs b a nultiple of 3. the outpuit ls tnte, otherwise it is false. Driw th\,A{M chart that describet the above machine.

t,l'-.t

_Ll "l( .tYfl .i..

-rd''.

l

I

-.rut

I

i

t

III

I

.Ss:Initialstate - :

ifS= I then Rtelnput,{Ra + Input 8.

Go to 51.

rvhere, external input S is uscd to start the operation.

if S = 0 then go to S9.

.S1 : R,a ? Rl+ (2's complemcnt ofRg)

Borrow +- Conplemcnt of carry,

Go to 52.

52 : If (Bonow = 0) then go to Ss

If(Bonow: l) then' Rl € (2's conplement of R,a )

Go to Sg. ,Exarnple 1.13. A sequcntial circuit has oneflip-tlop Q ; ttt'o ittltut x, und y; and onc output,

S. lt cortsist of afitlt adder cirait connected to a Dflip-flop, as slnv'n in Fig. 7.'26. Drive the

stute tuble and slutc diagram of the scquential circuit.

Ft,9.7,28 .

Draw the equivalent ASM chart, leaving the state boxes empy'.

Solutlon.

Table 7.1

Present state

aInputs

.ryNert state

tOutput

.t

0

0

0

0

l.

t.

I

I

000ll0ll000ll0ll

0

0

0

I

0

I

I

I

0

I

I

0

I

0

0

t

)t)x

v

i

._J

II,II

-lII

L-l

[lxanrple 7.r2. Drart,art AStI rhrr,;:l:'f,!rr,,,, x,ittt 2.8 bit registc,rs R.1 artt! R6 ant!perfonns the subtrrtctiort opentrio,tt 2ls1,,f 2 s c,otnpletttertt nethol,Rl <- Rt- Ra &Gpy Bltrtlxtl, Jtrttt, 2003)Solulion.

l

i

InitillSrarc

Rrr* lnPutARs--lnpu B

fa*Ra + 2's complemenr of RuBorrow<- compternent of carry

Ftg.7.2S

1 t \'a - ,a !;,.ffi .tl'lll

Solution.

III

,lrl*I

TE z( + ? a^*? Ex

)

&-?TrtrzV$.

Qx

-"-\qx_Link 3

?Y=pqx

.Pa

F19.7.23

e' =Fg+Fx +QX

ed,\H 1F axdrTqX

oo\ -o\ o-l

.-,

F19.7.22

Using thc rcalization stcps givcn in scction 7.5, wc frnd that thc conditional outputT'- PQX

rincc thc o-nly link, path tlrrougM tttttt witfi PQ = I I and takcs thc X = I bronch'

Thcrc arc tluee link paths (lobelcd link 4, link 2, link 3), which tcnninatc in a state B that has

0 - l. Link I starts with a present slate PQ= 01, takcs X=}branch ond temrinates on a state Cin

ilrict e = l.Therefore, the ncxt-state equation for Q thts has 4 terms corrcsponding to the 4 link paths'

Epex +pox +PAx * IgGffi@riltrmrSimilarly, one hnk paYt,I l) terminate in a state cwith P = l, so

€;= PQX

Next state .quuffii of e can be simplified with k-rnap using the unused state assignment as

r don't care condition.

00 0l ll l0

0

I

0 rl 0. x

I 3l I x

@-Exarrple 7'r0. convert ile SM charr of Fig. 7.20 to state grapht.

o\

s,lrrtlo'' 'l'trc givcn sM clrart r,rr l ,,1',1 lolr-on.^for each sratc. J6 is rhc srarring srare.It has orrc irrpur ,\'ond output z uri o.,tprt is l onry in ,iot. s3.If 'll = 0 is statc sg' z = 0 and thc ncxt state is J9 itself, If k = l, / -0, thc next statc is J1 .If'li-0i'state s2'z=0andthcnextstateisJgwhile forx=l,z=0,thenextsrateis.s2.In {r, ifx= 0, the nctrvork returns to,s9 0therwise, thc next state is.s3.putput Z is placcd in the statc box J3, therefo re Z is i

;';3:rtb'otherwisc, thcnext','[iri itsetr. Fis.7,2r Jff:'**;:rffijil;ft*:l'jl I

I

rl(.

IL

r-7\

nplffi{' For the EM char, "rrTn;|fl make therottowing state assignntentfor the

A, PQ = 00; B, PQ = 0l ; C, pg - 11.Derive the nexr sh? and ourpir equati,r.uo,io,u oni.iirf),on rhe net*ork;;:o{;::'::^':!o::tu .on

the sM chsrt. sinptifi

tt

the equatiotu anc! thrn aron-ti;';;;'u-u"u,r oy rracng link paths on the i

logic gati.

Example 7.9. Convert the state g.aphs of Fig. 7. t 8 to SM chart.

-]-t. f,Vft

when't' 'arl

'!| .".r,

I

I

iii.a

i--_-i-t Itl

IIIII1IIII

o/ t

Fig.7.18Solution.

F19.7.19

Form 4 states boxes for cach state and after each state box put input in decision box and put

conditional output box in the path whereMealy ouputs are I . Fig. 7.19 shows an SM chart for thc

state graph of Fig. 7. I 8.

ill

i

-J

III

..)

'It, rt

Exanrple 7.8. obtain a s-late diagram for a Moore circuit which produces output'1, rrh,it detects rhe sequence l0l. ot,errapping scquences o* otioru"i.;i;;;;r;;,;r;';;;;:;:-for the givctr circuit.

Solution.

ltl

0

Fig.7.16

!IT.JT{I COP

-,(.

(

I

LFi,1.7.17

ff;li:':fil ;}1:1,:1:ll'*i"'^t"5*::?]:*''ne for each stare. rhe Moore sutpqis placed in the state box since it is tdependent of input. LFig. 7.17 shows an SM chart for the state diagram ofFig. 7.16.

i] Ii ,F[ii'i.

-l'

I solurII

i lotot!,, "-t

,r.. Fisl

. 1,.,^.1-

/@nnInsecondcase(Fig.7.l3(D))theoutputis l'= | if8= t, C= I orB =0'A = t or8:l,C-0'

r-lllcnce Y = BC+AE+ABe

= AE+BUe +C'l

= AE+ BQ+C)=tr+ BC

i ,frich is the same ouput function realized by the ASM chart of Fig.7 .13 (a). Hence X and Y are

i 14icolly equivalentI t^----

@DrawanASMcharttodescribeameaIystatemachinethatdeteclsasequence! --A@ffiCserrc a logical I at the output tluring the last state of the sequence.

i Solutlon. Figure 7.14 gives thc cdrresponding state diagram for a given sequence detector.

.'leaal r Ftg.7.14I

, i 'lb dcrivc SM cSart fronr Mcaly starc ctiagram, form thrcc statc boxcs for cuch statc l, B and

(.. Aftcr cach stntc box put input in iccisiorr box and put conditiorul output box in thc puth wltcre

lrtcrly ourputs arc l. fig. 7. f5 gir.r thc corrcsponding SM chori for I givcrt dctcctor.

F19.7.15

/

ffiSolutlon.

Output Q is alrvays I , so it is placcd in thc statc bo.rcs sincc it do not dcpcntl on i1put.7,12 shows thc rcquired SM block with two exit path.

Errnrpfc 7.6, Figurc 7,13 kt) and 7.13O), represeilts an ASM chartsfor tv'o boolc tit

function X ond Y show th,ot'thc twtt ore, tLWlty,cWtg&

1.,

1II

F:ft h -:',4-hJ.: In fint casc (Fig. 7.13 (a)) ftc output

x :i:i:,:,

(a)

F19.7.13

isX- lif A- l orifl -0,8 = I andC- I Hencc

[:xit Patlr 2

F19.7.12 An SM block

:l

Ouput Z is always l, i.e. it is not a function of input variables (A, B, C), thereforc.put the

',rrtput Z in state box. Ouput ll/ is I ifl A and B are both I else f l/ is 0.

lf C=l andA=0, )'= I andexitpath I istaken.OuputX= l, ifC= 0orA=0andcxitpath,l rs taken.

'onvert the state diagram of Fig. 7.10 to 4Sj!chart.s ,>\ ,/'rr

Solution.

Fig. 7.1 l shows an ASM chart for *, ,[i;Ht*m of Fig. 7. 10.

Example 7.5. Construcl an ASM btock that has 3 input l,ariables (A, B, C) 4 ttutlttrt

wriobles (P Q, R, S) aud 2 exit paths. For this block, output Q is alv'ays I, cuul P is I iJJ' I " 0.

tt A and B are 0 or if(A = I ond C J q,R = / and uit path 2 is taken. IfA and C ara I orJl-= 0 and B - l),.S = / and exit path.l ts taken.

tt'I

li'j:'.TIi 'i'!,t,',;i.[1','..'.'i'f f j13:T,q.l:::::r,rvir be .r ,regardrcss

rr,*,rruc or,?.,i';,i"i,1;;:;;1;;,,:,Ttk* 3,'ff::i,*"-rl':,j;lliiit'J"l;[:'ji:iiilJ],;i':I#,,, J:;:llTll"Ii3 :: l $ ;:,,; il ;::fi.),:,,: :;nH:ii:j:;,1,i,:

I .If D is 0 ttrcn outpuf will bc .l ,

Fig.7.8

llxnn:otc 7.3. Coust^tct un rn, ,,!?:! tly,t.has.J input *r,::!^tS, (A, B, C), 4 ourltuts (W, X,Y z), und 2 cxir rxttrn..t'",, ti,r'ii"i*' o:tr:r: z t, otrroy,r),

ynct ^w.t1

t ,/rA ant* are botrt r. rft'' :fif,

":.0

y- t artdcxttl,o,i,'itr.tuken. y'c-'ior,4 -0,x- iinae:itpattt 2 is takcti,

,,r,.ln""tl':; ill ;tS fJ

hg. z.e An sM Bto.k&lt M 2

I

)I I/ t'l/ r.-r

t

.l j

rti :

.!:'l

l..._,ffi rlif4. For each of these link paths, find a tcrm that is t when th'e link path is followed. For

example, to *ritc the cxpression for next statc of 8, we consider link path I n'hich is start in

stateZp(AB =01), takes theX= I branch, andends instate ZOUB = I l), so the next state

of8 has atermA'BX.

Link Path I

Fig.7.6

4. The expression for thc next state of Q is formed by OIting togetltc'r all the tcnl$ fotrnd in ,

stcp 3.

Sinrilarly, thc cxprcssion for output can bc rcad dircctty fronr the ASN'l cltlr t.

Find o sinrplilic4 cxprcssion for output and ncxt-strtc cquatiotrs rvith a t-tturll trsittg thc

unuicd statc ossignmcnt as n dott't carc condition'

7. Rcslizc thc SM chart using gotcs and flip-flops.

Errnrple 7,1, Obtalrt thc ASM ctnrtforlollowlngfitnctiott, i,f *'a Mil l,ut x'lnla c.tpres.siott

ln conditlon box.

Z=A+B'CSolutlon.

Flg.7.7

ASM chart for Z = A *B,C contain onlylne state box. Condition A + B'C is placed in the

decision box and Z in conditional output box.

Errmple 7,2, Draw flttjWhartforfoltowingfunction, deach input variable is placed

.{

:

t

ttIIIIi

IIa

I

I !'et.f: l.

I.. Iii

rbi;lil

| ',rl

..rI

I

v()ll

r l'

illg

I

I

l

''0'nd

5.

6.

I

.rlc

II

.l

l.rty.

J-r.l

t!I

in the decision box.

Z- AB' + C' D'

Similarly, Fig. 7.5 (c) shorvs that Z= | if AB t AC= l. Ilence, Z= A (B + C) = AB + )gwhich is the same ourpur funcrion rearized by the ASM chart of Fig. 7.5.

I,ff.,..,T# ili; l j l?l.T ?:,,.i: l j: t in c gnd jtiln _b_o1,

nrs t check,{ i f ,4 i s ze r o z rrirn b' iiJ''5 j,l'.',ii :' i i il'fi iilC= 0 then outnltf witl h. .oi Lo^^..^^ r :, rt= o,:n:n our:ur *rllo. '0' b..uur.-z{ is r and B i, urro o.'#J,xr,trtlTf;;*TJ.|*.,,!irf'Jl.

Tj:i:lffi;::'fi J;: {!! :i } I,i ! ! :,ld_n c ycond i tio n box Fi rs r check A B, ir A B is . li#H;"1.T:ili:Hi:*:':,i: jr".,,j*:i;+:;Tj:?\T;,');:TtrlXil1iffi ;.zero because both temu arezero.lf AC: l, Zwill be l.

-.In last case, we may pur

conditional output box.whofe boolean

"*pr"riion AB + AC incondition box and Z irJ

7.4. CONVERSION OF A STATE DIAGRAM TO AN ASAA CHART*,,."l|X,ll:ilff::*ilu|1ji:'T;"'diagram ormachine, bur ce rrair' *r., nrusr be ronowedexacrrv on..*it fitrr crcnned c;;il :'j: ftil;,il;i'ffT,',ilTifilifialil;;ff' ;.

Mealy ntacltirte' In casc of Mcaty nrachine, output is a frrrrctio'.f b,t' prcsc't statc arrcJltiii. Iror c.ttstructio' .fASv tr"n-ilnr Mcaly srarc diagr'n\ \r,c shourcilirilorv rtrc folowi'g

.

l. Rcprcscnt cach statcs by starc boxcs. j

2 Put input in dccision box a{lcr coch statc box.t ,xf tH,y

oulput 'ppc'r

in corrditional outpur boxcs sincc thcy depcnd o' botl r1c starc

4' Meary circuit output writtcn o'ry wrrcn it is cquar to ,r , i e., truc.5' Dcpending on varue of input connect the path to ncxt state box.fr{oore mochlne' ln case of Moore machine, output is a function of the present state onry.For conshuction ofAsrur crrirt n*'rta*r. rodilil *r rr,orta rorr"*,r,. fortowing steps.l. Represent each states by state boxes. 'v"vw

2 The Moone output are praced in the state boxes since they do not depend on the input.3. After each state box put the input in decision box.4' Depending on varue of input connect the path to next state box.

7,5. REAIfZATfON OF ASi,l CHARTSRealization ofASM charu u', ri-it., to the rnethods used to rearize state diagrarn ihefr1,-"rffif;:"ffj;" "n ut *'l

"i.ri", tn, or*i r#rq*,ion for a nip-nop e irgares and

l' The first step is to make a suitabre state assignment for...h ro,r.2 Search all the states for which e is one.3' For each of these states,

'nd at of the rink paths that read inro the stare.

t

I

I'iiiI,L,

[-rllLi

i

ftt'I

I

tl

I

-'lI

tlAIJ

tt'l.l

-1,l,l

IJ

)tl

cjil

t

I

I

;

II

Branch 2 fII

Fls.7.a (b)

7,9, EQUIVALENT AsM CHARTS ' I' ' ',

ASM charts arc not uniquc, it nray havc nrorc tltan onc cquivalcnt fornr Fig. 7.5 shorvs tlrrcc

cquivalentASM charts for conrbinutional nctwork Z-A $ ! q.

Flg. 7.5 Equlvalent ASM charts lor Zo A (8 + QASM chart for cornbinational network contain only onc state box. The output Z= | if A = |

arrd either I or Cequal to l, as shown in Fig. 7.5 (c).

Fig.7.5 (D)shows an equivalent ASM chart in which Z- | if either AB = | o: AC= l'

'i

(iii) cottctitiottat 'urptit bo-v. A.Fo,irli't"ffIl,ii!;- is sh.orv' i' Fig. 7.3 is a rectangurarbo'x rvith curved ends' It contain conditional oufput t;r;. il. conditionar ourpur crepcrcrs ,. borrr(he state of the systc'nt and the inputs. T}erefoie th. .on,litional output signals are solrretinrc.sknowrt as Mealy outputs. A conditional outpur nrusr follorv a tlecisitln bo.x.

(iv) AsM Btock.^sM 0,,.[?;';.,:;:lillTi[{f-i,firon, sratc box rvitrr onc or

',orcdccisiort boxcs and cortditionor Ci*.r associatcd ,"irhtthrt:;rl. an ntpiur".r. has onc crrrarccpath and one or ntorc cxit paths. nn nsrra chart consiri, oron. o, n.,or. iir',-.-r.o,*.ctcd blocks.Ilxccution ofsM block it t"q*"tii ia."r, whercas.*e.r,ion orinrrru.tlon ruirrrin sM brock isconcurrcntprocess., ., . . . r .f

_ _ -__ ,.,^e.rr,tc)

::]D,ffi'I;|r,Tj,;: j::*:j:n:n1b."_ wl$ true.and farse bra'ches. Boorc.ah condirionil;"'.;;';,Hffi:i:;dccisron box inrrcr fnllh.,, --r L^ rgnals. Thedccisron box must foilbrv and be associated *,ith a state box.

I

,, "

,,1,?fiff: ch and tink poth. Apat;'ft'"rrflfilrilTlck rrom enrrancc ro exit is rererred ro

Ili

L,;(l

tlt:I

I

(ltlnrlit ional()ulpui l.lsr

Basic element for branching is decision box. After decision box we get two exit path, true orfalse' Depending upon condition-one can branch itself upwarcl or don*+,ard.

I

.t

''ri -.-l

/ r-\/ to VHD|/

-tlrj

€.-1rt

IrlI

.,

i,

r,.i

'{

IIJ

n:--t

I

ttItIIl

i

!I

id

I

i.J

tII

,iI1I{A

III.5

II

rlilr.,D

q;l| _l

I

ATGORITHMIC STATE

7.1. Asn^ GHARTASM stands for ,Algorithmic state nuchinc' or sirnply state nnchine is the another name

l:rvcn to sequential netrvork. Sequential netrvork is used to control a digital systetn rvhich carries

frrr a stcp-by-step proceclure. Algorithnric srate nuchine charts (AsN'l chart) or state nrachine

e lnrts (SM charts) arc flow charr, uscful in hardrvarc design of cligital systenl. ASM chart rese nrblcs

r convcntional llorv chart, but it is dill'crcnt liorn flowclurt. ASM cltrtt cotttain inplicit tirrring

[rformation. It should bc notcct that ASM charts rcprcscnt physical ltardwarc and oft'crs scvcral

rrlvarttagcs.

l. opcration of a cligital systcnl con bc casily unclcrstitncl by irrspcction of thc sM chltrt'

2. ASM cltarts rcprcsctlt physicol lrardwarc

3. 't'hc AsM charts urc cquivolcnt to u stutc groph, oncl it lcads dircctly to u ltardwlrc

a. fittni"jl,, .on'b. dcscribcd rhc opcration of both combinational ond scqucntial circuits'

. ;: il;,;r*';;; .ori., to undcrstana ano cm bcconverted into sevcral equivalent fornr'

6. 'l'he AsM .t urt *uy be equivalcntly cxpressed as a state nnd output table'

' :#ilffi; a a.sqripti;" 6;r;;.in;*ion or.. aigtal svstem. It is an abstract description

r,r the ,u*rt,rru, iiilescribes what a syitem does, but not how it is donc'

The ASM chart can be use{'as ttb slarting point of thc hardware synthesis process' Any

givenASM chartrnay be implcmented in hardware in'more luo:1* ltt''aat

7.2. PRINCIPAL COMPONENT OF AN ASIA CHART

(f) stateDox. The state of the system irreprcsentedby a state box' It is a rectangular box' At

rhe top left-hand.o*., the name of rtui, is siro*, whili::*::ij,ltn, hand corner the state

.,rr,,,i"t "i;;i";;:wt,ttii,rtt state box, the output signals are listed'

Ij

:l../

Stote Assignnrcnt

OutPut Llstor Rcgister OPcntion

Flg.7.1 State box.