. . 2011 1This ToolBox presentation is the sole property ofFORE Systems, Inc. All Rights Reserved. / & . - . 2 (semiconductor) memory cell 0 1

(DRAM)DRAM (Dynamic Random Access Memory) (volatiles) T Bits :H (0 1) ( )

/ & 3. - . DRAM

Address line

/ & 4. - . MICRO DRAM OPERATION / & . - . 5 Write Address line (word line) Transistor (Voltage) bit lineHigh 1 low 0 address line (capacitor)

Read Address line Transistor bit line sense amplifier ( ) 0 1

DRAM OPERATION (Read one bit)

H address bus RAS row address latchO row address decoder sense amplifier ( WE off)

RAS : Row Access Strobe : Output EnableWE: Write enable onWE off / & 6. - . DRAM OPERATION (Read one bit)

5) H address bus 6) CAS column address latch7) O column address decoder sense amplifier 8) sense amplifier bit data bus ( pin)9) 10) , (memory refresh) 8 refresh bits onWE off / & 7. - . CAS : Column Access Strobe : Output EnableWE: Write EnableDRAM OPERATION (Write one bit) / & . - . 8

H address bus RAS row address latchO row address decoder sense amplifier (OE off)

offWE onRAS : Row Address Strobe : Output EnableWE: Write enableDRAM OPERATION (Write one bit)

5) H address bus 6) CAS column address latch7) O column address decoder sense amplifier 8) W sense amplifier bit data bus ( pin) bit 9) 10) , (memory refresh) 8 refresh bits offWE on / & 9. - . CAS : Column Access Strobe : Output EnableWE: Write Enable DRAM2-

ROWCOLCASRASRead/Write1 bit 1 Mbit1024 1024 / & 10. - .

/ & 11. - . 4M 4 bits DRAM

/ & 12. - .

/ & 13. - .

/ & 14. - .

/ & 15. - . (SRAM)SRAM (Static Random Access Memory)

(volatile) bits on/off Flip-flop ( ) (cache)

/ & 16. - . SRAM bit

Address TransistorData TransistorCross point / & 17. - . SRAM bit 1

/ & 18. - . Transistor offTransistor onCross point offCross point onSRAM bit 0

Transistor offTransistor onCross point offCross point on / & 19. - . SRAM write or read

ReadWrite / & 20. - . SRAM

Flip-flop 6 transistors2 () 4 (1bit) WRITE READ(1 bit)DATADATA / & 21. - . SRAM

WE_LOE_LINPUTLOWHIGHOUTPUTHIGHLOWERRORLOWLOW / & 22. - . SRAM8 4 bits

10110111Read signal011Basel Soudan0

0

0

0

0

1

0

0

1 0 1 / & 23. - .

/ & 24. - .

/ & 25. - .

/ & 26. - .

/ & 27. - . SRAM PACKAGE

/ & 28. - . RAM

/ & 29. - . DRAM / & . - . 30Fast Page Mode (FPM DRAM)Extended Data Out (EDO DRAM)Enhanced DRAMSDRAM Synchronous DRAMSDR-SDRAMDDR-SDRAM DDR2-SDRAMRDRAM (RAMBUS DRAM)

SDRAM VS RDRAMSDRAM8 bytes (64) bit wide data-busPC133SDRAM : 133MHz x 8 Bytes = 1064 MB/s = 1.1GB/s RDRAM2 bytes (16) bit wide data-busPC800RDRAM : 800MHz x 2 Bytes = 1600 MB/s = 1.6GB/s

/ & 31. - . Memory BandwidthMemory TypeClock Rate (MHz)Bus Width (bits)Peak BandwidthFP (1987)2564200MB/sEDO (1995)4064320MB/sSDRAM (PC66) (1996)6664528MB/s PC100 SDRAM (1998)10064800MB/sPC133 SDRAM (1999)133641.1GB/sPC800 RDRAM (1999)400x2161.6GB/sPC1600 DDR SDRAM (2000)100x2641.6GB/sPC2100 DDR SDRAM (2001)

133x2642.1GB/s

/ & 33. - .

(One-word-wide) (Wide)(Interleaved)

/ & 35. - . ( ) block in cache = N wordsCPU bus =1 WordMemory bus = 1 Word =

== N x ( ++ s ++ )

1 word1 word ( ) block in cache = N wordsCPU bus = 1 WordMemory bus = M Word =

== (N/M) x ( + s + )

M words (N-way interleaved) block in cache = N wordsCPU bus =1 WordMemory bus = 1 Word = Interleaved N banks

== + s + N x

block block block. . CellSelectWrite SignalData OutCellSelectData InRead Signal Wite Read 0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

1 0

01

ROW

COL

ADDRESS

16 x 1 bit memory

24

1 bit

C P U

SRAM MODULE

N x N words x M bitsDATAAddressWE_LOE_LWE_L : Write EnableOE_L : Output EnableCPUCACHEMAIN MEMORYCPU

MULTIPLEXER

CACHE

MAIN MEMORY

CPU MEMORYBANK 1CACHE MEMORYBANK 0MEMORY BUS MEMORYBANK 2 MEMORYBANK 30000100001001100Bank 000001100101011101Bank 010010101001101110Bank 100011101101111111Bank 11Memory address XX YYXX : Address in BankYY : Bank addressCPUCACHEMAIN MEMORYCPU

MULTIPLEXER

CACHE

MAIN MEMORY

CPU MEMORYBANK 1CACHE MEMORYBANK 0MEMORY BUS MEMORYBANK 2 MEMORYBANK 3