nanochip...applied materials, inc. nanochip technolog journal volume 10, issue 2, 2012 6 25...

volume 10, issue 2, 2012

BECAUSE INNOVATION MATTERS™

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© 2012 Applied Materials, Inc. All rights reserved.

Printed in the U.S. 6/12 2K

NANOCHIPTechnology Journal

IN THIS ISSUE• Cryo-Implantation in Ultra-

Shallow Junction Formation

• High Aspect Ratio Etching for 3D NAND

• Developing ReRAM for Future Memory Applications

PVD REFLOW ENABLES VOID-FREE COPPER FILL

http://www.amat.com

At the 2x nm node, the industry finds itself in the situation aptly described

by baseball icon Yogi Berra: “when you come to a fork in the road, take it.”

Transistor technology is advancing in multiple directions. While material

properties and physical barriers are driving the growing trend from planar

to 3D designs, much work is still being done to extend planar scaling and

capability to the utmost.

Conductor etch is advancing on both fronts. Developments in high-temperature

etching are extending 2D NAND Flash technology, while improvements in

critical etch CD uniformity and microloading control address double- and

quadruple patterning as well as high aspect ratio 3D architectures.

At the 2x nm node, void-free interconnect metallization becomes a major

challenge as ionized physical vapor deposition (PVD) cannot guarantee the

required coverage for electroplating. We present an innovative solution that

enables bottom-up copper fill through a PVD reflow solution, effectively

reducing via aspect ratios and facilitating the subsequent plating step.

Dopant activation and defect creation in the extension region, source/drain junction, and contact region can also

impede performance scaling at 2x nm and beyond. Our leading-edge cryo-implantation process, taking place at wafer

temperatures as low as -100˚C, combined with energy-pure dopant profiles is effectively addressing these challenges.

Emergent 3D NAND architectures heighten the requirements for high aspect ratio etching, demanding precise

control of both plasma characteristics and reactor conditions. A magnetically tuned very-high-frequency source,

combined with high-frequency bias and step-to-step temperature control enables all-in-one etching of both mask

and dielectric stacks for very high aspect ratio etching and extremely high tungsten selectivity.

With continued planar scaling of the contact length, the interface resistance between metal and semiconductor has

become a major challenge for CMOS performance and power scaling. We are studying metal-insulator-semiconductor

contact architectures to determine the most effective way in which to enhance current-carrying capability to match

state-of the-art NiSi contact architecture.

Although 3D NAND appears to be the leading contender for next-generation bulk-storage memory, other architectures

offer possible alternatives. Structural simplicity, cell scalability, switching speed, and compatibility with established

CMOS fabrication processes make ReRAM an attractive complement to 3D NAND for future non-volatile memory

applications at 1x nm and beyond.

We hope you find these articles thought-provoking springboards for discussion and collaboration in addressing the

multiple challenges we face in advancing the state of the art in semiconductor technology.

Cover: Innovative copper seed technology for the 1x nm node combines cold PVD deposition and high-temperature copper reflow. An iterative cycle of the two steps reduces feature aspect ratio for electroplating, facilitating void-free fill.

A MESSAGE FROMRANDHIR THAKUR TABLE OF CONTENTS

3 PVD Reflow Enables Void-Free Copper Fill

at the 2x nm Node and Beyond

7 Cryo-Implantation in Ultra-Shallow Junction Formation

at the 2x nm Node and Beyond

12 Advances in Conductor Etch

for the 20nm Node and Below

16 High Aspect Ratio Etching for 3D NAND

Enabling New Dimensions in Flash

21 Benchmarking Novel Contact Architectures

on Silicon and Germanium

25 Developing ReRAM

for Future Memory Applications

Randhir Thakur, Ph.D. Executive Vice President

General Manager,

Silicon Systems Group

3 4Volume 10, Issue 2, 2012 Volume 10, Issue 2, 2012Nanochip Technology Journal Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.

25 Developing ReRAM






HOME

Reflow Gap Fill

KEYWORDS

Barrier/Seed

Copper

Electroplating

Physical Vapor Deposition

PVD

Reflow

PVD Reflow Enables Void-Free Copper Fillat the 2x nm Node and Beyond

Reliable and complete filling of interconnect trench and

via structures with copper (Cu) is vital in microelectronic

fabrication. Beyond 2x nm, ionized physical vapor

deposition (PVD) of Cu barrier/seed layers cannot

ensure requisite coverage for electroplating, making

void-free gap fill extremely challenging. Augmenting room

temperature deposition with high-temperature reflow

alleviates this difficulty, creating bottom-up Cu fill of the

feature that reduces aspect ratio and facilitates plating.

Figure 1

Technology Node

3x 2x 1x

Asp

ect

Rat

io

Incoming Structure: ~3.5:1

3.8:1

4.5:17:1Conventional

3x 2x 1x

(Before Barrier/Seed)

(Ideal Coverage)1.5:1

Reflow

Cu metallization in today’s microelectronic fabrication

involves depositing the Cu barrier and seed layers by

PVD followed by Cu electroplating to fill the topography.

Each of these process steps requires careful optimization

that ultimately determines the success or failure of the

gap fill. Incremental enhancements of both barrier/seed

and electroplating processes have ensured void-free

Cu gap fill down to the 2x nm node. As interconnect

structures shrink further, even the most optimized

barrier/seed process, showing conformal coverage

without any overhang, increases feature aspect ratios

beyond levels manageable for electroplating (Figure 1).

Reflow of sputtered Cu is one of the most promising

approaches for resolving this issue in interconnect

metallization.[1-2] By enabling bottom-up Cu fill and

thereby reducing aspect ratio, it facilitates electroplating

and void-free gap fill (Figure 1).

Cu movement into narrow trenches and vias can be

achieved by augmenting deposition with subsequent

thermal reflow. Cu reflow is controlled by several

fundamental processes. Surface diffusion is driven by

capillary forces created by local gradients of chemical

potential, which in turn vary due to surface curvature and

geometry. Grain boundary movement accommodates

material flux, from high potential to low potential, and

from the convex side to the concave side. The wetting

properties of the underlying layer also play a role.[1-3]

To avoid lateral growth and agglomeration of Cu after

reflow, a selective deposition profile (thinner field

coverage and thicker bottom coverage) is essential as

it utilizes the above-mentioned phenomena to drive the

Cu downwards into the narrow structures, creating a

bottom-up PVD fill.

INNOVATIONS IN PVD CU REFLOW Pedestal heaters are commonly used for wafer heating

in a PVD deposition system. However, this approach

poses significant process limitations for PVD Cu reflow,

Figure 1. Aspect ratio of

interconnect trench after

Cu barrier/seed layers and

the benefit of reflow at the

1x nm node.

which requires two process temperatures—cold

deposition followed by high-temperature reflow. Instead,

reflow can be induced through backside wafer heating

using lamps, reflectors, and a wafer lift assembly

embedded in the wafer pedestal. Figure 2 (a-c) details

the process sequence of room temperature deposition

and high-temperature reflow.

The wafer enters the chamber cold and Cu deposition

occurs at room temperature. Innovations in the PVD

Cu deposition system (not discussed here) enable the

selective Cu deposition profile essential for achieving

bottom-up fill from the reflow step. Following deposition,

the wafer is raised to the reflow position using an

integrated pedestal lift assembly. Focused light, generated

through lamps and reflected through a set of reflectors, is

uniformly radiated at the backside of the wafer, heating it

rapidly. The wafer can be heated from room temperature

up to ~400˚C during this reflow step. Wafer temperature

governs the extent of Cu reflow (Figure 3a), as lower temperatures (50-200˚C) enhance surface diffusion of Cu along the feature sidewall to realize a moderate increase in bottom coverage.

Higher temperatures (~250-350˚C) enable mass move-ment of Cu from the field and sidewall into the feature. This movement is driven by enhanced diffusion and grain boundary grooving, resulting in a significant increase in bottom coverage. Even higher temperature (>400˚C) induces lateral growth and agglomeration. The above-mentioned temperature regimes also depend on the substrate layer for Cu reflow. Following reflow, the wafer is lowered onto the pedestal and electrostatically chucked to enable rapid cooling. The cycle of deposition, reflow, and cool-down can be repeated multiple times to gradually increase bottom coverage in features to the point of complete fill. Figure 3b shows complete Cu fill of 2x nm node trench structures achieved after three reflow cycles on Ta liners.

Figure 2. Process sequence

of (a) Cu reflow showing

(b) wafer position and lamp

status and (c) temperature

profile.

Figure 3. Reflow performance

on 2x nm structures.

(a) Effect of temperature

on Cu reflow on Ta liner.

(b) 100% bottom-up Cu fill

on Ta liner after 3X cycles.

Figure 3

1X Cycle 2X Cycle 3X Cycle

20% Fill 50% Fill 100% FillTemperature (˚C)

1000 200 200 400

Tren

ch O

peni

ng (

nm)

60Å TaN + 350Å PVD Cu Reflow @ “X” C

As DepPartia

l Reflow

Full ReflowAgglomeration

(>400˚C)

As Dep ~40˚C

Reflow T ~150˚C

Reflow T ~325˚C

(a) (b)Applied Materials internal data

Figure 2

ESC ESC

(Lamps O� – Wafer on ESC) (Lamps On – Wafer on Lift Pins)

ESC

(Lamps O� – Wafer on ESC)

Step 1: Selective Cu Deposition Step 2: Reflow Step 3: Cool-Down

Time

Tem

pera

ture

Room Temperature Deposition

Tem

pera

ture

Time

Temperature Ramp and Soak

Tem

pera

ture

Time

Cool

(a)

(b)

(c)

6Volume 10, Issue 2, 2012Nanochip Technology JournalApplied Materials, Inc.

25 Developing ReRAM




5 Volume 10, Issue 2, 2012 Nanochip Technology Journal Applied Materials, Inc.



HOME

Reflow Gap Fill Reflow Gap Fill

In addition to room temperature deposition followed

by thermally-assisted reflow, chamber architecture

accommodates deposition at higher temperatures (40-

400˚C), followed by thermally-assisted reflow. In the

latter scenario, lamps can be used to heat the wafer

prior to the deposition step. This technique makes it

possible to apply reflow on other liner materials, such

as cobalt and ruthenium, as shown in Figure 4.

Figure 4

Cobalt Liner Ruthenium Liner

(b)(a)Applied Materials internal data

200nm 200nm

Figure 5

Ave

Tem

p (˚

C)

Time (sec)

0 20 40 60 80

0

100

200

150

50

250

300

350

Dep Heat Soak Cool

MinMax

Full ReflowWindow on Ta

Temperature uniformity across the wafer is essential for

ensuring yield after reflow. Lamps (diameter and design)

and reflectors (shape, location, and surface reflectivity)

are key to optimizing temperature uniformity. Figure 5

illustrates the temperature profile of the wafer during

each step of the reflow process, as measured by a 17pt

thermocouple wafer. This measurement was done for a

room temperature deposition process with a reflow set

point of 325˚C. The temperature non-uniformity range,

measured after heat-up and soak, is less than 25˚C.

The figure also shows the temperature window for

achieving full Cu reflow on a Ta liner (2x nm node

trench structures).

DEVICE INTEGRATION AND MANUFACTURABILITY The impact of a high-temperature reflow process on

overall device performance was evaluated by line and

via resistance measurements. No significant difference

in resistance was found between test samples with

and without reflow (Figure 6). Performance, however,

is sensitive to the ion energy during the PVD Cu

deposition process. Low-energy processing minimizes

the intermixing of Cu and Ta during deposition. This

reduces electron scattering along the Cu/Ta interface

and maintains low line and via resistance.

High-volume manufacturability of the deposition

and reflow process was validated in a 10,000-wafer

marathon. Figure 7 shows stable thickness uniformity,

repeatability, and an in-film particle performance of

fewer than 10 adders at 0.09µm.

Figure 6

Perc

ent

Measurement

10 1000

Line RC (M2, 32nm) Via RC (65nm Vias)

(a)Applied Materials internal data

Low EnergyProcess

Cu (w/o Reflow)Cu Reflow




High EnergyProcess

99.9

99

9590

80

60

40

20

1052

.5

.1

Low EnergyProcess

High EnergyProcess

Perc

ent

Measurement

10 100 1000 10000

(b)

99.9

99

9590

80

60

40

20

1052

.5

.1

Figure 6. Comparable

(a) line resistance and

(b) via resistance with reflow

process. Device performance

is sensitive to the energy

during Cu deposition (with

and without reflow).

Figure 5. Temperature

uniformity of Cu reflow

chamber over the complete

process sequence (17pt wafer

thermocouple measurement);

process window for full reflow

on Ta liner exceeds 100˚C.

Figure 4. Reflow process

validation on alternative liners.

(a) Cobalt and (b) Ruthenium.

CONCLUSION The technology node shrink from 2x nm to 1x nm creates

significant gap fill challenges for PVD Cu barrier/seed

and electroplating. Reflow-based PVD Cu seed is

required to address Cu seed coverage challenges. A

cycle of deposition, reflow, and cool-down performed

in a single chamber demonstrated stable marathon

performance in achieving complete gap fill on a PVD

liner with extremely low defectivity. Line and via

resistance measurements were comparable with

baseline non-reflow PVD Cu samples. Independent

temperature control for each step of the deposition/

reflow cycle offered flexibility for successfully applying

this process to cobalt and ruthenium liners.

ACKNOWLEDGEMENTSThe authors acknowledge contributions from the

technology, engineering, and integration groups of the

Applied Materials Metal Deposition Products team.

REFERENCES [1] L.J. Friedrich, et al., “A Simulation Study of Copper

Reflow Characteristics in Vias,” IEEE Trans. Sem.

Manuf. 12 (3), 353, 1999.

[2] L.J. Friedrich, et al., “Study of the Copper Reflow

Process Using the GROFILMS Simulator,” J. Vac. Sci.

Technol. B 15 (5) 1780, 1997.

[3] W.W. Mullins, “Flattening of a Nearly Plane Solid

Surface Due to Capillarity,” J. Appl. Phys. (30) 1, 1959.

AUTHORSSree Kesapragada is a global product manager in the

Metal Deposition Products business unit of the Silicon

Systems Group at Applied Materials. He holds his Ph.D.

in materials science and engineering from Rensselaer

Polytechnic Institute.

Winsor Lam is a technology manager in the Metal

Deposition Products business unit of the Silicon Systems

Group at Applied Materials. He earned his B.S. in

chemical engineering from the University of California

at Berkeley.

Xianmin Tang is a principal member of technical staff

in the Metal Deposition Products business unit of the

Silicon Systems Group at Applied Materials. He received

his Ph.D. in physics from the College of William and Mary.

Mani Subramani is a distinguished member of technical

staff in the Metal Deposition Products business unit

of the Silicon Systems Group at Applied Materials. He

holds his Ph.D. in mechanical engineering from the

University of Rhode Island.

Keith Miller is a senior engineering manager in the

Metal Deposition Products business unit of the Silicon

Systems Group at Applied Materials. He earned his

M.S. in mechanical engineering from Purdue University.

ARTICLE [email protected]

PROCESS SYSTEM USED IN STUDYApplied Endura® Amber™ PVD

Figure 7

Thi

ckne

ss (

Å)

Non

-Uni

form

ity

%1s

Wafer Count

0 100008000600040002000

(a)

500

400

300

200

100

0

8

6

4

2

0

ThicknessNU%

Part

icle

Add

ers

Wafer Count

0 100008000600040002000

(b)

50

40

30

20

10

0

Mechanical (0.065μm)In-Film (0.09μm)

Figure 7. Process robustness

showing (a) stable thickness

and (b) defect trends over

10,000 wafers.

mailto:[email protected]


25 Developing ReRAM






HOME

KEYWORDS

Cryo-Implantation

Ultra-Shallow Junction

Junction Engineering

Strain Relaxation

Leakage

Carbon Implantation

Cryo-Implantation in Ultra-Shallow Junction Formationat the 2x nm Node and Beyond

At the 2x nm technology node, dopant activation and

defect creation in the extension, source/drain junction, and

contact regions become significant challenges that impede

the scaling of high performance. Among the latest implant

advances addressing these issues, cryogenic ion implant at

wafer temperatures as low as -100˚C is proving a versatile

and effective junction engineering and damage control

technique for enabling continued device scaling.

Scaling for smaller and faster devices, with the

accompanying trends to reduce diffusion and lower

thermal budgets, have driven advances in ion implantation

technology. Ultra-shallow junction formation in the

source/drain extension (SDE) requires extremely abrupt

profiles, aided by the elimination of energy contamination

in the implanted profiles as well as means to suppress

diffusion. Incorporating strain to independently optimize

performance of n- and p-type devices is a complex

process made easier and more effective by ion implant’s

precise placement of material-modifying species.

Contact area becomes so small that contact resistance

severely inhibits device performance, challenging

integration and process engineers to increase dopant

activation without incurring major process changes.

A major development in this field during early 2x

technology development has been the addition of wafer

temperature as a means of further improving junction

formation. Cryo-implantation, which involves implantation

at wafer temperatures as low as -100˚C, is now being

implemented in fabs of the most advanced device

makers. Extensively studied, this method is employed

in a number of device applications, showing significant

benefits in reducing crystal damage, improving junction

engineering, alleviating strain relaxation in SiGe (silicon

germanium), and reducing device leakage.[1-6]

REDUCING DAMAGEAt the 2x nm node, junction depths must be less than

15nm to minimize short channel effects (SCE). Junction

depth is driven primarily by the enhanced dopant

diffusion caused by the formation and evolution of

defects that advance into the silicon upon annealing.

Substrate temperature exerts a powerful effect on the

implantation process.[7] By cooling the wafer during

implant it has been demonstrated that fewer self

interstitials (target interstitials) are present at the

implant end-of-range (EOR), i.e., the depth just beyond

the peak of the implanted dopant profile. Lower tempera-

tures down to -100˚C are typically more effective.[8]

At these temperatures, the lattice energy is reduced

along with its ability to recover, thus accelerating the

rate of lattice disruption caused by implant. Under

these conditions, amorphization occurs at lower doses

and extends deeper with fewer self interstitials left

beyond the amorphous/crystalline (a/c) interface.[9]

The reduction of EOR defects formed upon annealing

significantly reduces dopant diffusion and deactivation.

Figure 1 compares transmission electron microscope (TEM)

images of silicon implanted with boron or carbon at room

temperature (RT) and at temperatures as low as -100˚C.

Cryo-Implantation

IMPROVING JUNCTION FORMATION The reduction in junction depth and gate pitch that has

accompanied advanced device scaling has required

balancing the need to increase the depth of the SDE

to lower resistance and the need for a shallow SDE to

improve device SCE performance. Conventional nMOS

contacts have been made using arsenic ion implants,

but the smaller contact areas at advanced nodes dictate

higher active dopant abruptness and concentration to

reduce series resistance.

Phosphorus is an attractive alternative as its activation

level and solubility are superior to those of arsenic,

but its lighter mass results in more channeling.

Pre-amorphization can suppress channeling,[10] but

inevitably leads to damage, which is less effectively

annealed as post-implant thermal budget decreases.[11]

Phosphorus also diffuses more rapidly than arsenic,

producing poor junction abruptness and the inability

to achieve ultra-shallow junctions for the sub-20nm

nodes. Introducing carbon at the junction reduces this

effect, but typically silicon must be fully amorphized

for the carbon to be effective.[12] However, traditional

pre-amorphizing implant can cause significant EOR

damage and high leakage.

Co-implanting the carbon at -100˚C removes the need

for pre-amorphization and enables very abrupt, low-

resistance junctions using phosphorus, as illustrated in

Figure 2. Using the implanted carbon plus phosphorus

profiles in Figure 2a, cryogenic carbon implantation

achieved an 8nm/dec abrupt junction as shown in Figure 2b.

Figure 2. Implant profiles

of phosphorous, boron,

and carbon after

(a) cryo-implantation

and (b) annealing.

Figure 1. Cross-sectional

TEM images for

(a) boron 2keV 3e15/cm2

at RT and -100˚C;

(b) carbon 5keV 1e15/cm2

at RT, -20˚C, -40˚C, and

-100˚C reveal thicker

amorphous layers and

smoother a/c interfaces

with cryo-implantation.

The effect is more evident

as temperature decreases.

Figure 1

(a)

(b)

A/C Surface

Silicon Surface

Silicon Surface

Crystalline Silicon

Crystalline Silicon

RT -20˚C -40˚C -100˚C

RT -100˚C

A/C Surface

Applied Materials internal data

Figure 2

(a) (b)

Con

cent

rati

on (

atom

s/cm

3 )

Depth (nm)

0 20 40 60 80

1018

1019

1020

1021

1022

No Anneal

Carbon(-100°C Cold Implant)

Con

cent

rati

on (

atom

s/cm

3 )

Depth (nm)

0 20 40 60 80

1018

1019

1020

1021

1022

P

B

P

B

C

1020°C RTARs 495ohm/sq

xjs ~ 8nm/dec


25 Developing ReRAM







HOME

Cryo-Implantation Cryo-Implantation

Figure 2. (c) Phosphorous

and boron profiles after

carbon-free implantation at RT;

(d) 11% increase in drive

current with cryo-implantation.

Figure 3. (a) X-ray diffraction

comparison of as-deposited

strain (black) and post-

silicidation strain (red) with

(bottom) and without (top)

a -100˚C carbon implant.

(b) Junction leakage is

substantially less after

germanium 10 keV cryo-

implants than germanium

15 keV RT implants.

For comparison, Figure 2c shows the broader

phosphorous profile and deeper junction formed without

cryo-implantation. Moreover, the 80nm gate pitch

nFETs (n-type field effect transistors) tested in this

study displayed resistance values 15% lower than

those doped with arsenic, inducing an 11% increase

in current (Ion

) for matched Ioff

(Figure 2d).

PRESERVING STRAIN, REDUCING LEAKAGE At advanced nodes, channel strain engineering

enhances carrier mobility in pMOS transistors. In

these devices, compressive strain is induced by SiGe

selectively grown in the source/drain regions.[2] For

maximum effect, the SiGe must retain the same level

of strain through multiple downstream process steps,

including implantation and annealing.

It has been demonstrated that strained SiGe relaxes via misfit and threading dislocation propagation after high-temperature dopant-activation annealing.[13,14] EOR defects, which commonly form around the a/c interface during annealing can serve as nucleation sites for dislocation formation or aid in the inter-diffusion of boron and germanium that, in turn, can accelerate strain relaxation.

Cryo-implantation reduces the number of EOR defects, which has the dual benefit of preserving strain and reducing the likelihood of junction leakage emanating from EOR defects. Results from one study (Figure 3a) showed that pre-silicidation strain decreased by approximately 7% in the absence of cryo-implantation, but was maintained when carbon cryo-implant was implemented.[6] In another (Figure 3b), 28nm CMOS

Figure 2 (continued)

(c) (d)

Con

cent

rati

on (

atom

s/cm

3 )

Depth (nm)

0 20 40 60 80

1018

1019

1020

1021

1022

No Carbon Implant1020°C RTA

Rs 455ohm/sq

I o� (

A/µ

m)

Normalized Ion

(au)

0.6 0.8 1.0 1.2 1.4 1.6 1.8

1e-11

1e-10

1e-9

1e-8

1e-7

1e-6

P

B

11% Up

nFET80nm Gate Pitch

Vg = Vd = 0.9V

AsCold C + P

Figure 3

(a) (b)

Cum

ulat

ive

ILJA (A/μm2)

1E-16 1E-101E-111E-121E-131E-141E-15

0%

100%

80%

60%

40%

20%Ge 15keV (RT)Ge 15keV (Cryo)Ge 10keV (Cryo)

(w/o C)

(w/o C)

(w/o C)

(w/o C)

NiSi Formation(480°C)

Fully Strained

NiSi Formation(480°C)

~7% Relaxed

As-Dep NiPtFully Strained

As-Dep NiPtFully Strained

No Implant Control

C PAI at -100°C

Figure 4. (a) Atom-probe

measurements from blanket

wafer studies show smooth

and agglomeration-free silicide

with cryo-carbon implant.

(b) Structured wafer silicide

resistance without implant (red),

with RT 1keV C 1e15 carbon

implant (green), and the same

carbon implant at -100˚C (blue).

structures in which p/n junctions were formed by in-situ doped epitaxial SiGe followed by germanium implants of varying energies revealed leakage two orders of magnitude lower using a 10keV germanium implant at cryogenic temperature.[4]

OPTIMIZING INTERFACES Cryo-implantation has also shown good results in improving nickel silicidation interface qualities. Nickel salicide has been used with SiGe stressors since the 90nm technology node to reduce source/drain contact resistance. However, such issues as controlling nickel diffusion; avoiding nickel piping (usually along implant-induced damage sites); and controlling agglomeration, particularly in the SiGe strained layer, make silicidation especially challenging, particularly in p-type structures.[15]

As germanium concentration increases beyond 25% to

enhance pFET channel stress, the nickel silicide/silicon

interface tends to become rough. A pre-silicide cryo-

implant mitigates this effect (Figure 4a).[6] In addition,

cryo-implantation enables pMOS depth and abruptness

requirements by trapping interstitials and limiting nickel

diffusivity. Figure 4b illustrates nickel silicide formation

at lower temperatures, with better thermal stability

and lower sheet resistance when preceded by a -100˚C

carbon implant. For nMOS, nickel diffusion during the

silicidation step can be reduced by using a silicon implant

at cryo-temperature to pre-amorphize the contact area.

Figure 4

(b)

Res

ista

nce

(ohm

s/sq

)

Wafer Temperature (°C)

100 200 300 400 500 600 700 800 900 1000

0

50

100

150

(a)No Ge Agglomeration

Cold Carbon Presilicide

Smooth NiSi

Ge Ni

RT Carbon

NiSi Formationwith No PAI

Cold Carbon

CONCLUSIONIon implantation technology has evolved on several

fronts in response to scaling challenges at the 2x nm

node and beyond. Cryo-implantation in combination

with energy-pure dopant profiles and special species,

such as carbon and germanium, is proving to be a

versatile and effective means by which to create ultra-

shallow junctions with minimal damage, improved

activation, and reduced leakage. With such advances,

high-current ion implantation has become a true

enabler of device performance and yield improvements

for the 2x nm node and beyond.

REFERENCES[1] S. Deshpande, et al., “Advanced Junction Formation

for Sub-32nm Logic Devices,” 10th International

Workshop on Junction Technology, IEEE, pp. 124-126,

2010.

[2] C.I. Li, et al., “Mitigating eSiGe Strain Relaxation

Using Cryo-Implantation Technology for PSD

Formation,” 11th International Workshop on Junction

Technology, IEEE, pp. 71-74, 2011.

[3] K. Yako, et al., “Cold (-100˚C) Carbon

Co-Implantation into High Phosphorus Doping

Source/Drain Extensions for Aggressively Scaled

NFETs,” 11th International Workshop on Junction

Technology, IEEE, pp. 77-79, 2011.

[4] C.L. Yang, et al., “Alleviating eSiGe Strain Relaxation Using Cryo-Implantation,” Electrochemical and Solid-State Letters, 14 (11), H467-H469, 2011.


25 Developing ReRAM







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Cryo-Implantation

[5] C.L. Yang, et al., “Benefits of Cryo-Implantation

for 28nm NMOS Advanced Junction Formation,”

Semiconductor Science and Technology, 27,

published online at http://iopscience.iop.org/0268-

1242/27/4/045003, 2012.

[6] A. Renau, “Device Performance and Yield—A New

Focus for Ion Implantation,” 10th International

Workshop on Junction Technology, IEEE, pp. 1-6,

2010.

[7] K. Suguro, et al., “Advanced Ion Implantation

Technology for High Performance Transistors,”

Proceedings Materials Research Society, Vol. 669,

J1.3.1-12, 2001.

[8] C.I. Li, et al., "Enabling Solutions for 28nm CMOS

Advanced Junction Formation," Inter. Conf. on Ion

Implant Technology, Kyoto, Japan, 2010.

[9] Morehead, et al., “Formation of Amorphous

Silicon by Ion Bombardment as a Function of Ion,

Temperature, and Dose,” Journal of Applied Physics,

43, 1112, 1972.

[10] B.J. Pawlak, et al., “Suppression of Phosphorus

Diffusion by Carbon Co-Implantation,” Applied

Physics Letters, 89, 062110, 2006.

[11] P.J. Timans, et al., “Advanced Thermal Processing of

Semiconductors,” 16th IEEE International Conference

on RTP, pp. 77-79, 2008.

[12] B. Colombeau, et al., “Ultra-Shallow Junction

Formation—Physics and Advanced Technology,”

Proceedings of the 17th International Conference

on Implantation Technology, Monterey, California,

pp. 11-18, 2008.

[13] F.T. Sanuki, et al., “Sophisticated Methodology

of Dummy Pattern Generation for Suppressing

Dislocation Induced Contact Misalignment on

Flash Lamp Annealed eSiGe Wafer,” VLSI Tech.,

pp. 156-157, 2009.

[14] M. Yu, et al., “Relaxation-Free Strained SiGe with

Super Anneal for 32nm High Performance PMOS

and Beyond,” IEDM Tech. Digest, pp. 1-4, 2006.

[15] J. Zelenko, et al., “Nickel Silicide Anneals

Modification Enables Scaling,” Semiconductor

International, March 2010.

AUTHORSTom Parrill is director of high-current implant marketing

in the Varian Semiconductor Equipment business unit

of the Silicon Systems Group at Applied Materials. He

holds his Ph.D. in materials science and engineering

from Northwestern University.

Benjamin Colombeau is a device technology manager

in the Varian Semiconductor Equipment business unit

of the Silicon Systems Group at Applied Materials.

He earned his Ph.D. in materials science and device

technology from Le Centre National de la Recherche

Scientifique, Toulouse, France.


PROCESS SYSTEM USED IN STUDYApplied Varian VIISta® Trident High-Current Implanter

with PTC II XP Cryo Option

KEYWORDS

Patterning

CD Uniformity

Shallow Trench Isolation

STI

Dual Frequency Bias

Intra-Cell Microloading

High-κ Etching

FinFETsCritical dimension uniformity requirements have become

more demanding in light of double and quadruple patterning

schemes. As feature sizes shrink below 20nm, they are

becoming more three-dimensional, which presents additional

challenges, such as achieving high aspect ratio etch with

minimal microloading (aspect ratio dependent etching or

ARDE). Further, the use in logic gates and memory stacks of

high-κ materials, whose etch by-products are less volatile,

presents additional challenges for next-generation etch

applications. Recent approaches for enhancing etch reactor

technology are showing promising solutions.

Integrated circuit manufacture is increasingly dependent

on advancing the state of the art in plasma etch technology,

with patterning and critical trench applications as the

key drivers. In patterning, 193nm wavelength immersion

lithography has been extended using double patterning

techniques (DPT) down to approximately 20nm. In DPT,

the CD budget is split between one etch step and one

spacer deposition. More recently, quadruple patterning

techniques (QPT) have been developed to achieve a

half-pitch of 16nm and below. In QPT, the CD range

budget is smaller than for DPT and split between

one etch and two spacer depositions, thus requiring

significantly higher etch uniformity.[1] We previously

reported on an inductively coupled plasma (ICP) source

design that overcomes inherent “M-shape” plasma

profile, significantly reducing CD variation from plasma

non-uniformities.[2] Subsequent development has

focused on extending best-in-class uniformity to the

extreme edge where discontinuities in the geometry

and materials can lead to variations in electric field

compared to the rest of the wafer.

Critical trench etching processes, such as shallow

trench isolation (STI) and combined STI/fin formation

for FinFETs now require profile and microloading control

for features with aspect ratios (AR) exceeding 15:1 at

the 20nm node and 20:1 at 15nm. These challenges

are exacerbated by small variations in CDs of adjacent

features created by the aforementioned advanced

patterning schemes. Control of intra-cell microloading is a

key issue and requirement in advanced IC manufacturing.

Conventional ICP etch systems utilizing a single frequency

RF bias (typically 13.56MHz) are limited in addressing

these issues. Experiments have shown that dual frequency

bias technology employing both 13.56MHz and 2MHz

RF power to the cathode (wafer) offers flexibility in

tuning the ion energy and angular distributions (IEADs)

needed for tighter AR profile and microloading control.

RF pulsing[3] enhances this IEAD control through its

ability to affect ARDE.[4]

High-κ/metal gate (HKMG) stacks were first introduced

for logic gate applications at the 45nm node[5] and have

been widely employed in logic designs from 32nm.

NAND Flash scaling challenges led to the introduction

of floating gate devices in which high-κ materials were

integrated into the inter-poly dielectric (IPD)[6] to

maintain the coupling ratio between the control gate (CG)

and floating gate (FG) while eliminating the CG wrap

around. For this gate structure, in which the high-κ

dielectric is significantly thicker than in logic gates,

high-temperature etching appears to be the only way

to maintain vertical profiles with minimal footing while

stopping on extremely thin tunneling oxide without

pitting in the substrate.

ADVANCED PATTERNINGThe tolerable CD variation for feature sizes below 20nm

is on the order of 1nm or less. Past development has

focused on gas distribution (center feed with directional

control) and plasma shaping to eliminate inherent

“M-shape” plasma non-uniformities associated with

conventional ICP sources.[2] With these improvements,

Advances in Conductor Etchfor the 20nm Node and Below

http://iopscience.iop.org/0268-1242/27/4/045003

http://iopscience.iop.org/0268-1242/27/4/045003



25 Developing ReRAM






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ICP-based conductor etch chambers, such as the one

depicted in Figure 1, provide excellent control of ion and

neutral species across the wafer. The focus has now

shifted to the edge of the wafer, where discontinuities in

material and geometry give rise to variations in electric

field that result in “roll-off’ of CD and etch depth.

Figure 1

ICPSource

DielectricWindow Gas

Nozzle

Substrate

Cathode

DielectricRing

ESC

We have found that extending the electric field out past

the edge of the wafer mitigates such variations and

results in tighter CD control. Figure 2 illustrates this

improvement for an advanced patterning scheme over

results obtained using a standard electrostatic chuck

configuration.

CRITICAL TRENCH ETCHEtching the silicon substrate for trench isolation has

been implemented in numerous generations of IC

manufacturing. As devices become more three-

dimensional, trench etching now includes buried word

line, buried bit line, combined STI/fin formation for

FinFETs, and memory core STI, in addition to standard STI

for transistor isolation. As we approach 20nm for memory

and 15nm for logic, the AR of the trenches (including

hard masks) is approaching 20:1.

The challenge for the etch process, therefore, is to propel highly directional and energetic ions to the bottom of the features to continue etching to the desired depth. One way to achieve this is to increase ion energy by using a low RF bias frequency. Figure 3 illustrates this effect, showing the ion energy distribution function (IEDF) measured using a low RF bias frequency of 2MHz compared to the IEDF using a traditional 13.56MHz frequency bias. At the lower frequency, ions are not only accelerated to significantly higher ion energies for the same bias

power, but are also narrower in their angular distribution.

The width of the angular distribution, W, is defined as:

where e is the electronic charge, ε is the ion energy, κ is Boltzmann’s constant, and T is the ion temperature. From this it follows that as ion energy, ε, increases, the width of the ion angular distribution, W, decreases, thus resulting in a more directional ion trajectory towards the wafer.[7]

Employing a dual frequency bias (13.56MHz and 2MHz) allows fine tuning of the ion energy distribution to achieve greater control over the etch, essential for high AR features. Figure 4 compares the bottom of an STI structure (with AR~20:1) etched with a 13.56MHz bias and a 2MHz bias. The feature etched with 13.56MHz bias exhibits a tapered bottom profile, indicating that insufficient ions reached the bottom of the trench, which will likely produce “etch stop.” In contrast, the feature etched using a 2MHz bias displays a more rounded bottom profile, indicating a wider etch front that enhances the ability to etch deeper—a capability crucial for etching even higher AR features at future technology nodes.

Figure 2. CD roll-off at the

extreme edge of the wafer

can be caused by discontinuity

of the electric field. Enhanced

coupling of bias RF power

to the edge can minimize

this effect.

Figure 3. Dual frequency

bias accesses a broader range

of ion energies, allowing more

flexible tuning for specialized

applications, such as high AR

trench etch. Shown are the

real-time IEDFs of a 5mTorr

Argon plasma measured with

two different bias frequencies,

both at 200W RF power.

Figure 1. ICP chamber for

conductor etching.

Conductor EtchConductor Etch

Figure 4 also illustrates another issue encountered in advanced patterning schemes: CD variation between adjacent features in densely spaced lines. In DPT schemes, the variation occurs in alternating lines as shown, while in QPT the CD variations have a more complex recurring regularity. Pulsed plasmas[4] have been shown to provide more effective profile control, especially when matching the profiles between isolated and dense lines. Pulsing the plasma (both the ICP and bias) results in a significant decrease in feature-to-feature loading observed in CW processes while retaining the etch front characteristics of the two frequencies (tapered at 13.56MHz while rounded at 2MHz).

HIGH-TEMPERATURE ETCHING Unlike patterning and critical trench etch processes that are performed within the conventional temperature regime (25-80˚C), satisfying advanced etch requirements for non-volatile materials used in HKMG requires much higher temperatures. Figure 5 illustrates an advanced planar NAND Flash stack as proposed by Parat[6] for sub-30nm half-pitch, which includes a high-κ IPD. Once the top layers have been etched, it is challenging to etch

the bottom layers while preserving the top profile. Since the AR in the cell area can be equal to or greater than 10:1, the ion energy must be increased for conventional etch processes. Etch by-products of high-κ films (e.g., HfO

2, La

2O

3, Al

2O

3) are non-volatile in the conventional

operating temperature regime. Thus, etching high-κ materials at low temperatures requires a high sputter yield (high ion energy) physical etch process that typically results in poor selectivity to the underlying tunnel oxide and source/drain structures, as well as an undesirable tapered profile and footing (Figure 5). These adverse side-effects significantly constrain the process window.

To achieve high selectivity and vertical profiles in high-κ materials requires a high-temperature chemical etch regime. At temperatures of 150-250˚C, little or no ion energy is required, resulting in near-infinite selectivity

between high-κ and silicon oxide films. Figure 6 illustrates

this effect, comparing HfO2 etch rates as a function

of temperature for three ion energy (DC bias) levels.

As expected, etch rates are higher at high DC bias;

however, etch rate dependence on DC bias is noticeably

Figure 4. Dual frequency bias

enhances etch depth capability,

while plasma pulsing minimizes

microloading.

Figure 3

Nor

mal

ized

IED

F

Energy (eV)

1000 200 300

1.0

0.8

0.0

0.2

0.4

0.6

13.56MHz

2MHz

Figure 2

CD

Bia

s

Radius (mm)

500 100 150

ESC with Enhanced Edge Coupling

Standard ESC Configuration

1nm

Figure 4

Dep

th (n

m)

Trench CD (nm)

2115 17 19 25 2923 27

200

190

180

170

150

160

Con

tinu

ous

Wav

e(C

W)

Puls

ed

13.56MHz 2MHz

Applied Materials internal data

Pulsing

Pulsing reducesloading for both

13.56MHz and 2MHz

2MHz

13.56MHz

13.56MHz - CW13.56MHz - Pulsed2MHz - CW2MHz - Pulsed

Figure 5

Footing with Conventional Etch

More Vertical Profilewith High-Temperature Etch

Hard Mask

Control Gate

High-κ IPD StackFloating Gate

Tunnel Oxide

Figure 6

Ln (H

fO2 E

tch

Rat

e)

1/T (K-1)

0.00250.00200.0015 0.0030 0.0035

8

7

2

4

3

5

6DC bias

226C˚ 127C˚ 60C˚

Strong dependence on DC bias atconventional etch temperatures

Low DC bias dependence (>40V)at high temperatures

92V45V0V

Figure 5. Conventional etch of

a typical NAND Flash HKMG

stack produces a tapered

profile and foot compared

with a near-vertical, foot-

free profile achieved with

high-temperature etch.

Figure 6. Blanket HfO2

etch rates as a function of

temperature at different DC

bias levels (BCl3/Ar chemistry,

900W source, 5mTorr).


25 Developing ReRAM






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Conductor Etch

weaker in the high-temperature regime compared with

lower temperatures, creating a wider process window.

The high selectivity process can be tuned to produce

near-vertical profiles with minimal or no footing, which

results in much lower word line to word line coupling.

From a device reliability standpoint, this could be a critical

requirement for better data retention and read/write

program cycles.

CONCLUSION Conductor etch applications face steep challenges as

devices scale to 20nm and beyond. Critical dimension

uniformity, microloading, and profile control requirements

are becoming more stringent in advanced patterning

schemes and three-dimensional architectures, as well

as in next-generation planar structures incorporating

high-κ films. Etch technology development is showing

good results in addressing these issues.

Enhancing RF bias coupling to the extreme edge of

the wafer can significantly reduce CD roll-off and etch

depth variation that can result from discontinuity of

the electric field. High AR trench etching benefits from

the broader IEDF created by a dual frequency bias and

from plasma pulsing. The former enhances etch depth,

while the latter improves CD control and minimizes

microloading. Planar NAND Flash devices present the

dual etch challenge of higher AR features and relatively

thick high-κ material. As NAND Flash scales beyond

20nm, high-temperature etching is proving instrumental

in obtaining the high selectivity and vertical profiles

essential for optimal device functionality and associated

device reliability.

REFERENCES[1] P. Xu, et al., “Sidewall Spacer Quadruple Patterning

for 15nm Half-Pitch,” Proc. of SPIE, Vol. 7973,

pp. 79731Q-79731Q-12, 2011.

[2] S. Banna, et al., “Overcoming Inherent Etch Signature

of Inductively Coupled Plasmas,” Nanochip Technology

Journal, Applied Materials, Inc., Vol. 9, Issue 1, 2011.

[3] A. Agarwal, et al., “Tailoring Ion Energy Distributions

Using Pulsed Plasmas,” IEEE Trans. on Plasma Sci.,

Vol. 39, No. 11, 2011.

[4] S. Banna, et al., “Pulsed Plasmas Solve Advanced

Etch Issues,” Nanochip Technology Journal, Applied

Materials, Inc., Vol. 9, Issue 1, 2011.

[5] K. Mistry, et al., “A 45nm Logic Technology with

High-κ + Metal Gate Transistors, Strained Silicon,

9 Cu Interconnect Layers, 193nm Dry Patterning,

and 100% Pb-Free Packaging,” IEEE International

Electron Device Meeting, pp. 247-250, 2007.

[6] K. Parat, “Recent Developments in NAND Flash

Scaling,” International Symposium on VLSI Technology,

Systems and Applications, pp. 101-102, 2009.

[7] M. Tuda, et al., “Numerical Study of the Etch

Anisotropy in Low-Pressure, High-Density Plasma

Etching,” J. Appl. Phys., 81, 960, 1997.

AUTHORSSamer Banna is a senior member of the technical staff

in the Etch business unit of the Silicon Systems Group

at Applied Materials. He holds his Ph.D. in electrical

engineering from the Technion-Israel Institute of

Technology, Haifa, Israel.

Ankur Agarwal is a senior engineer in the Etch business

unit of the Silicon Systems Group at Applied Materials.

He earned his Ph.D. in chemical engineering from the

University of Illinois at Urbana-Champaign.

Steve Lassig is a global product manager in the Etch

business unit of the Silicon Systems Group at Applied

Materials. He received his M.S. in materials engineering

from Rensselaer Polytechnic Institute.

Mayur Trivedi is a global product manager in the Etch


Materials. He holds his M.S. in chemical engineering

from San Jose State University.

Sumit Agarwal is a senior process engineer in the Etch


Materials. He earned his Ph.D. in materials science from

Brown University.


PROCESS SYSTEM USED IN STUDYApplied Centura® AdvantEdge® Mesa™

KEYWORDS

High Aspect Ratio

3D NAND

VHF Plasma

Etch

ARDE

Selectivity

Mask

High Aspect Ratio Etching for 3D NANDEnabling New Dimensions in Flash

As the planar 2D NAND technology node shrinks, the cost

of further advances (especially in lithography) becomes

prohibitive and significant material-related challenges

prevent scaling. This has expedited the need for 3D NAND.

Current 3D NAND architectures involve multi-layer stack

deposition, intensifying the demands placed on high aspect

ratio (HAR) etching, including very HAR (>50:1) etch

requirements, high throughput, and very high tungsten (W)

selectivity for staircase contact. Meeting these challenges,

magnetically tuned, very high frequency (VHF) plasma and

innovative wafer thermal management deliver >1.1μm/min

hard mask etch rates (ER), in-situ mask/mold etching with

vertical profiles, and stellar 500:1 W selectivity.

Conventional planar Flash memory technology is fast

approaching critical and prohibitive scaling limitations.

Some of these pertain to technical issues, such as

integration density beyond the 45nm node restricted

by large cell size and high applied voltages/fields for

program/erase operations. Others pertain to manufac-

turability, cost of scaling, and materials requirements.[1]

These fundamental limitations are inherently addressed

by the transition to a 3D architecture and, hence, make

3D NAND more attractive. Stacking cells vertically

creates a higher capacity/volume ratio in a smaller

physical space and also improves electrical performance

by shortening the interconnect between cells (which

also reduces power consumption). While the progression

of planar Flash is deterred by the cost of scaling

lithography, 3D architecture can enable enhanced

device performance using existing lower lithography/

technology nodes in conjunction with deposition and

etch requirements that are less expensive to realize.

For these reasons, 3D stackable NAND Flash memory

is a mere two to three years from full-scale adoption.

Most leading memory manufacturers expect to be in

pilot production within the next year and in volume

manufacturing within the next two years. Each

manufacturer is investigating different architectures

with different variations in the integration scheme:

gate-first/gate-last, transistor architecture, and storage

mechanisms. However, the common element is a

stackable device structure of alternating layers of

dielectric and conductor. The two key approaches are

an oxide-poly alternating stack and an oxide-nitride

alternating stack with wet etch removal of the nitride to

fill with tungsten. Given the greater vertical dimension

of the stack (AR>50:1) compared with planar Flash,

both approaches place stringent demands on deposition

and etch performance—in particular, on HAR etch.

3D NAND HAR ETCH CHALLENGESAs the aspect ratio of etch stacks increases, process

tolerances become extremely tight. Key challenges

include ER/aspect ratio dependent etching (ARDE)

improvement,[2-3] critical dimension (CD) uniformity,[4]

and CD profile improvements. Vertical profiles are

especially critical (i.e., high bottom to top CD ratio,

absence of bowing or bending, and distortion-free

bottom holes). In addition, for the staircase contact

architecture in 3D NAND, it is essential to avoid punch-

through of the gate W during the entire etch. This

implies that the W layer at the top of the staircase will

experience more than 300% over-etching, effectively

increasing the W selectivity requirement to >350:1. The

advent of 3D NAND has also increased the aspect ratio

of mask etching and overall mask etch requirements for

ER, selectivity, and deformation.



25 Developing ReRAM






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Supplementing the bias source with a VHF top source

increases the plasma density further and helps achieve

faster ERs. With VHF RF only, the plasma density is

greater at the center of the chamber. As HF bias RF

is added, the plasma spreads out toward the edge,

creating more uniform density distribution. As the bias

begins to dominate, the peak plasma density moves

out to the wafer edge. This plasma density modulation

through RF power application can be used as a means

of tuning on-wafer ER uniformity (Figure 2b).

ARDE is a fundamental challenge for very HAR etching

and is more pronounced with the alternating layers

of dielectric and conductor in the 3D NAND stack.

Etch depth capability depends on the incident fluxes

of fluorocarbon reactive species (including both the

ions and the neutral radicals) and the surface reaction

probability, or the net energy, at the bottom of the hole.

Enhancing ARDE as required in 3D NAND staircase

contact etch requires higher incident ion energy (driven

by higher LF RF bias power), as well as higher ion flux

and lower surface temperature to enhance the surface

reactivity on the bottom of the hole. Maintaining a

stable wafer surface temperature under high bias power

conditions is very difficult as the high thermal load from

the plasma can overwhelm conventional wafer cooling

systems. Figure 3 shows the effect on ARDE of the

active cooling system as a function of wafer temperature.

ER as a function of depth is better sustained at the lower

wafer temperature and also decreases more slowly with

depth at lower wafer temperatures. This emphasizes the

need for maintaining temperature stability throughout the

entire process step and avoiding higher temperatures

induced by plasma load.

Another challenge in 3D NAND staircase contact etch is

W erosion. It is proportional to an opposing combination

of surface reactivity to fluorine chemistries and the rate

of polymer deposition (passivation). Hence, controlling

polymer deposition is critical for achieving high W

selectivity. Higher wafer temperature facilitates high

selectivity by both decreasing the reactivity and increasing

the polymer mobility to ensure sufficient coverage at the

bottom of the hole. However, it is challenging to maintain

HAR etch capability at a higher wafer temperature and

polymer deposition rate; the latter can produce etch stop

as a result of polymer clogging at the mask sidewall.

Thus, preventing temperature creep with the plasma

thermal load is critical for staircase etch management.

Conventional wafer cooling systems are severely limited

in this respect and active wafer cooling is pivotal for

meeting W selectivity demands. Figure 3a details the

temperature maintained for each process step; Figure 4

shows the schematic of the staircase contact.

Transitioning to HAR Mask Etching

As advanced patterning film (APF) mask thicknesses

have grown to exceed 1μm, maintaining adequate mask

selectivity and integrity are substantially more difficult

yet vital for very HAR processes. Precise control of

polymer deposition and elimination of extra-reactive

species at the wafer surface can enhance mask

integrity, reducing deformation and profile bowing

while reducing ellipticity at the bottom of the hole.

Optimized gas flow during the process increases mask

selectivity and limits necking polymer deposition on

top of the mask, while scavenging species reduce

fluorine radicals at the wafer surface.

HAR EtchHAR Etch

Figure 3

(a)

ESC

Tem

p

Time (sec)

100 200 300 400 500 600

10

20

30

40

50

(b)

Etch

Rat

e (Å

/min

, Nor

mal

ized

)

Time (sec)

120 240

0.75

0.80

0.85

1.05

1.00

0.95

0.90

ACL 10C

ME 30C

OE 50C

35s

40s

High TempLow Temp

Figure 3. Effect of step-

specific active wafer

temperature control.

a) Stable temperature

control within each step

and from step to step.

b) ER decreases with depth

more rapidly at higher wafer

temperatures.

To deliver the necessary etch performance to meet the

above requirements, the plasma etch reactor must create

a very uniform high-density plasma, higher ion energy,

uniform neutral species distribution, and uniform wafer

temperature. Typically, multi-frequency capacitively

coupled plasma (CCP) sources have been used for HAR

applications, using a higher radio frequency (RF) power

to control ion density and radical fluxes, and lower

frequency to control ion energy distribution.[5-9]

HAR ETCH INNOVATIONSA triple-frequency capacitive-coupled etch system has

been developed that addresses the aggressive etch

performance requirements for 3D NAND technology

(Figure 1).

To generate uniform high-density plasma over the wafer

area, both high-frequency (HF) RF and low-frequency (LF)

RF are delivered to the cathode. To control dissociation

of the process gases, a VHF RF source is configured to the

top electrode. Multi-zone gas control and independent

gas injection are used to achieve uniform and tunable neutral species distribution. The top source electrode and reactor walls are maintained at elevated temperatures to manage polymer distribution and deposition. Step-to-step active wafer temperature control (Figure 1) enables constant temperature within a process step—even under high plasma-induced thermal loads—and step-to-step temperature tunability.

HAR Etching of Multi-Stack DielectricsOptimizing RF delivery and innovatively coupling different RF frequencies are crucial for achieving the ER, profile, and uniformity requirements in HAR etching. Applying HF bias power increases plasma density at the wafer level, while lowering the sheath voltage (Vrf) or plasma heating. Figure 2 shows the reduction in Vrf when using a higher frequency bias as compared to a 13.56MHz bias reference. Reducing the Vrf enables use of higher LF bias power—the primary means of increasing the ion bombardment energy—thereby promoting vertical profiles.

Figure 1. Schematic diagram

of the three-frequency CCP

etch chamber and active

wafer temperature control

system.

Figure 2. a) Vrf is lower for

the HF RF bias compared with

a reference 13.56MHz bias.

b) Plasma density uniformity

can be optimized through a

combination of VHF and RF

sources.

Figure 1

COLD HOT

VHF RF

HF RFLF RF

Figure 2

(a)

Vrf

(V

, Nor

mal

ized

)

Total Bias Power (W)

0 2000 4000 6000 8000 10000

0.0

0.2

0.4

0.6

0.8

1.0

1.2 LF/13.56MHzLF/HF RF

(b)

Freq

uenc

y

% Mix 60MHz

0% 100%

60MHz

162MHz

100% 162MHz Top

100% 60MHz Bottom

50%/50%


25 Developing ReRAM






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HAR Etch

plasma density and polymerization for the dielectric

etch process. HF bias improves plasma density and ion

energy control to optimize ARDE. Besides facilitating

precise polymer management to simultaneously

achieve very HAR etching and very high W selectivity,

step-to-step wafer temperature control enables in-situ

all-in-one etching of both mask and dielectric stacks.

ACKNOWLEDGEMENTSThe authors acknowledge contributions from the

technology, engineering, and product management

groups of the Applied Materials Dielectric Etch team.

REFERENCES[1] G. Atwood, “Future Directions and Challenges for

ETOX Flash Memory Scaling,” IEEE Trans. Device

Mater. Rel., Vol. 4, No. 3, pp. 301-305, Sept. 2004.

[2] T. Tatsumi, et al., “Control of Surface Reactions in

High-Performance SiO2 Etching,” J. Vac. Sci. Technol.

B 18(4), 1897, 2000.

[3] D. Keil and E. Anderson, “Characterization of

Reactive Ion Etch Lag Scaling,” J. Vac. Sci. Technol. B

19(6), 2082, 2001.

[4] T. Yagisawa, et al., “Modeling of Radial Uniformity

at a Wafer Interface in a 2f-CCP for SiO2 Etching,” J.

Vac. Sci. Technol. B 23(5), 2212, 2005.

[5] Z. DonkÓ and Z. Lj. Petrović, “Ion Behavior in

Capacitively-Coupled Dual-Frequency Discharges,”

J. of Physics: Conference Series 86, 2007.

[6] T. Kitajima, et al., “Effects of Frequency on the

Two-Dimensional Structure of Capacitively-Coupled

Plasma in Ar,” J. Appl. Phys. 84, 5928, 1998.

[7] T. Kitajima, et al., “Functional Separation of

Biasing and Sustaining Voltages in Two-Frequency

Capacitively-Coupled Plasma,” Appl. Phys. Lett. 77,

489, 2000.

[8] E. Abdel-Fattah and H. Sugai, “Electron Heating

Mode Transition Observed in a Very High Frequency

Capacitive Discharge,” Appl. Phys. Lett. 83, 1533, 2003.

[9] K. Maeshige, et al., “Functional Design of a Pulsed

Two-Frequency Capacitively-Coupled Plasma in

CF4/Ar for SiO

2 Etching,” J. Appl. Phys. 91, 9494, 2002.

AUTHORS Arvind Sankaran is a senior global product manager in the

Etch business unit of the Silicon Systems Group at Applied

Materials. He holds his Ph.D. in chemical engineering from

the University of Illinois at Urbana-Champaign.

Jong Mun Kim is a senior member of technical staff in the

Etch business unit of the Silicon Systems Group at Applied

Materials. He earned his M.S. in materials engineering

from the University of Han Yang, Seoul, Korea.

Chunlei Zhang is an engineering manager in the Etch


Materials. He received his Ph.D. in electrical engineering

from the University of Dayton.


PROCESS SYSTEM USED IN STUDYApplied Centura® Avatar™ Etch

Figure 4

W Selectivity Vertical Profile

Figure 5

Etch

Rat

e (Å

/min

)

Bias Power (W)

0 1000 2000 3000 4000

0

15000

10000

5000 Bias Only

1000W Source Added (162MHz)

Figure 6

CD

(N

orm

aliz

ed, n

m)

Pre 25°C/25°C 25°C/15°C

-2.00

0.00

2.00

4.00

6.00

8.00

10.00

12.00

Polymerization can also be reduced by low-temperature

etching. (This contrasts with the high temperature

requirement for W selectivity in dielectric etching.)

Active wafer temperature control enables consistent and

stable low temperatures even at high source powers

and plasma loads. Step-to-step control (Figure 3a)

allows for quick changes in electrostatic chuck (ESC)

temperature from process to process, thus enabling

in-situ, all-in-one plasma etch of mask and dielectric

stacks.

APF etching also requires high plasma densities. These

can be achieved by increasing the RF power to the

system. However, substantially raising bias power for

this purpose would lead to degradation of other mask

attributes, such as profile and selectivity. Here, VHF

tuning offers a distinct advantage, enabling high plasma

densities that significantly raise the ER and throughput

of the mask-open process (Figure 5) with no adverse

side-effects.

Typically, VHF sources create center-high plasma densities

and are prone to inherent density non-uniformities.

As noted above, adding HF bias power can help offset

this. However, for APF etching, high bias power is

detrimental to profiles. The addition of uniformity

tuning mechanisms, such as solenoid magnetic coils

and a charged species tuning unit, help to alleviate this

issue and achieve uniform CD and profiles during the

mask-open process.

Controlling uniformity of sidewall passivation is another

important component of uniformity tuning. Mask sidewall

protection is addressed by tuning wafer temperature using

a dual-zone ESC. Figure 6 shows the effect of tuning the

center and edge zones on wafer temperature and mask

CD bias uniformity.

CONCLUSIONTransitioning to 3D NAND architecture creates significant

challenges in dielectric etching, especially for HAR

etching. Addressing them requires precise control of

both plasma characteristics and reactor conditions.

Innovative solutions that combine a magnetically tuned

VHF source, HF bias, and step-to-step active temperature

control are proving successful in doing so. The source

enables high throughputs in mask etching, and high

Figure 6. Independent

temperature tuning on each

zone optimizes mask CD

uniformity.

Figure 4. Critical 3D NAND

staircase etch.

Figure 5. Adding VHF

source power increases

ER significantly, whereas

bias-only power stalls ER

at high bias powers.

HAR Etch



25 Developing ReRAM






HOME

MIS Contacts

Benchmarking Novel Contact Architectureson Silicon and Germanium

KEYWORDS

Contact

Interface Resistance

RC

n-Si

n-Ge

MIS Contact

Novel contact architectures to n-silicon (n-Si) and to

n-germanium (n-Ge) were benchmarked for the first time

against the state-of-the-art contact architecture to n-Si.

It was found that although the recently reported contact

architectures to n-Ge exhibit markedly improved performance,

more work must be done to match state-of the-art NiSi/n-Si

contact architecture in current-carrying capability.

With continued scaling of contact length in accordance

with Moore’s Law (Figure 1), interface resistance

between metal and semiconductor has become one

of the biggest challenges facing CMOS performance

and power scaling. Much work is therefore focusing on

methods to achieve next-generation targets for lower

external series resistance in CMOS devices.[1-4]

Figure 2 shows the state-of-the-art specific contact

resistivity and targets for future nodes. Prior studies

have demonstrated effective pathways to lowering the

interface resistance for p-MOSFETs [e.g., use of narrow

bandgap silicon-germanium compounds in source/

drain (S/D) regions in silicon channel transistors].[3]

In addition, the use of a germanium channel device

provides the inherent benefit of Fermi-level pinning

near the valence band for contacts to p-Ge S/D.[5-7]

Alternative contact architectures are now being sought

to improve the interface contact resistance (RC) to

n-Si (for silicon channel CMOS) and to n-Ge (for

germanium channel CMOS) by reducing the Schottky

Barrier Height (SBH or ΦB) between metal and n-type

S/D semiconductors. Metal-insulator-semiconductor

(MIS) contact architecture has been proposed to

reduce SBH by unpinning the Fermi level.[8-10] There

is a concern, however, that insertion of a high band

gap oxide results in large tunnel resistance and would

offset the positive effect of Fermi-level unpinning. It is

therefore necessary to benchmark the current-carrying

capability of the MIS contact architectures on both n-Si

and n-Ge with respect to the state-of-the-art solution.

Since J depends exponentially on ND, we propose to use

J vs. ND as a way to benchmark different MIS contact

architectures. The metric proposed here is most suitable

for benchmarking contact architectures of widely

varying maturities.

Figure 1. a) Resistance

components in a MOSFET.

b) Smaller contact length

requires lower specific

contact resistivity at the

metal/semiconductor

interface to prevent RC

from increasing.

Figure 1

(b)

Con

tact

Len

gth

(nm

)

Technology Node (nm)

130 90 65 45 32 22 15 11 81

100

10

RSDB

REXT/2

RSDEB

RSDES RCHANNEL

RPLUG

RC

(a)

Gate

Figure 3. Current density at

100mV forward bias through

NiSi/n-Si and Pt/Si/n-Si contact

architectures shows good fit

between model and data.

Figure 2. Contact resistivity

requirements for different

CMOS nodes. Symbols are

estimated values in this work.

MODELThe reference NiSi/n-Si and PtSi/n-Si current density

data were obtained from N. Stavitski, et al.[11] The

current density J for NiSi/n-Si and PtSi/n-Si systems

was calculated at a forward bias of 100mV by assuming

that the current is a linear relationship of voltage for

doping density >1018cm-3 in the forward bias range 0 to

100mV.[12]

In other words,

[1]

The J vs. ND data was fitted to the following

analytical model[13] using a ΦB = 0.55eV and standard

band structures parameters for silicon (Figure 3):

[2]

[3]

where

was calculated using Fermi-Dirac statistics

with Nilsson’s Approximation.[14]

[4]

This ΦB result should reflect high doping effects,

such as band gap narrowing.[15] The barrier height ΦB

obtained from fitting the J vs. ND data to the above

analytical model is consistent with numerical quantum

mechanical analysis done on the same data set.[12]

As shown in Figure 3, it is also consistent with values

extracted on nanoscale contacts for NiPtSi/n-Si contact

architecture with heavily doped S/D semiconductor

(2-3x1020cm-3).[16]

Figure 2

ρ C (Ω

-cm

2 )

Technology Node (nm)

32 22 15 11 8

10-9

10-8

nFET

pFET

ITRS

Figure 3

Cur

rent

Den

sity

, J (

A/c

m2 )

Semiconductor Doping Density (cm-3)

1014 1015 1016 1017 1018 1019 1020

10-2

100

102

104

106

108

PtSi/n-Si

NiSi/n-SiModel

State of the Art

BENCHMARKING RESULTSThe benchmarking studies reported here revealed that the

lower specific contact resistivity observed in MIS contact

structures as compared to metal-semiconductor (MS)

contacts can be attributed to modification of the MS

work function difference. This modification can result

from (1) dipole formation at the metal–insulator

interface; (2) reduction of insulator/semiconductor

interface charges due to attenuation of metal-induced

gap states (MIGS)[17]; (3) reduction of insulator/

semiconductor interface charges due to disorder-

induced gap states (DIGS)[18]; and/or (4) dipole

formation at the insulator/semiconductor interface.

Figure 4 shows that for silicon, the TaN/LaOX/n-Si

showed improvement over the NiSi/n-Si reference

system that has a SBH of 0.55eV.[9] For full validation,

however, the benefit demonstrated at low ND must

be demonstrated at ND ≈ 2-3x1020cm-3. In addition,

investigations should be conducted to determine

whether or not the result would be different if another

metal with a lower work function were substituted for TaN.


25 Developing ReRAM






HOME

MIS ContactsMIS Contacts

Using data from various sources, contacts to n-Ge were

also benchmarked using the J vs. ND plot in Figure 3.[8, 19-24]

Despite the remarkable improvement achieved by using

MIS architecture, as opposed to MS architecture, MIS

contacts to n-Ge still lag the state-of-the-art NiSi/n-Si

reference system.

These studies showed that inserting an insulator between

the metal and n-Ge causes the insulator energy barrier

to attenuate J. This is demonstrated by the TiO2/n-Ge[17],

AlOX/n-Ge[17], and MgO/n-Ge[19] data points below the

reference line in Figure 5. The most promising result was

Al/TiO2/n-Ge at a doping level of 1019cm-3 (Figure 5).[17]

CONCLUSIONRC is one of the biggest challenges facing CMOS

performance and power scaling. MIS contact architecture

has been proposed for improving the RC to n-Si and

n-Ge. To test the validity of this proposal, J vs. ND data

from several studies of MIS contact architectures were

benchmarked against the state-of-the-art NiSi/n-Si

reference. For silicon, TaN/LaOX/n-Si performed better

than the reference. In the n-Ge case, the most promising

result was Al/TiO2/n-Ge, which might be possible to

improve further by reducing DIGS.

ACKNOWLEDGEMENTSThe author thanks Jerry Gelatos, C-P Chang, and Balaji

Chandrasekaran for technical discussion, and Satheesh

Kuppurao, Sundar Ramamurthy, and David Kyser for

managerial support.

REFERENCES[1] A. Khakifirooz and D.A. Antoniadis, “MOSFET

Performance Scaling—Part II: Future Directions,”

IEEE Transactions on Electron Devices, Vol. 55,

No. 6, pp. 1401-1408, June 2008.

[2] Y-C Yeo, “Advanced Source/Drain Technologies for

Parasitic Resistance Reduction,” Extended Abstracts

of the 10th International Workshop on Junction

Technology, p. 1, 2010.

[3] S.E. Thompson, et al., “Forever, Continued Transistor

Scaling One New Material at a Time,” IEEE

Transactions on Semiconductors Manufacturing,

Vol. 18, No. 1, p. 26, February 2005.

[4] I. Ok, et al., “Parasitic Resistance Reduction

Technology,” Extended Abstracts of the 11th

International Workshop on Junction Technology,

p. 50, 2011.

[5] A. Dimoulas, et al., “Fermi-Level Pinning and Charge

Neutrality Level in Germanium,” Applied Physics

Letters, 89, p. 252110, 2006.

[6] J. Robertson and L. Lin, “Fermi-Level Pinning in Si, Ge

and GaAs Systems—MIGS or Defects?,” International

Electron Device Meeting (IEDM) Technical Digest,

p. 119, 2009.

[7] P. Broqvist, et al., “Defect Levels of Dangling Bonds in Silicon and Germanium Through Hybrid Functionals,” Physical Review B 78, 075203, 2008.

Figure 4. Benchmarking

of TaN/LaOX/n-Si contact

architecture[2] vs. NiSi/n-Si

reference.

Figure 5. Benchmarking of

various contact architectures

on n-Ge[1,7-10] vs. NiSi/n-Si

reference.

Figure 4

Cur

rent

Den

sity

, J (

A/c

m2 )


1014 1015 1016 1017 1018 1019 1020

10-2

100

102

104

106

108

PtSi/n-Si

TaN/LaOx/n-Si

NiSi/n-SiModel

State of the Art

Figure 5

Cur

rent

Den

sity

, J (

A/c

m2 )


1014 1015 1016 1017 1018 1019 1020

10-3

10-1

101

103

105

107

109

AI/TiO2

AI/AIOx

AI/S

CoFeB/MgO

ReferenceNiSi/n-Si

Ni

TiN/GeN

Co

Co/AIOAI/SiN

State of the Art

Ni

[8] M. Kobayashi, et al., “Fermi-Level Depinning in Metal/Ge Schottky Junction and Its Application to Metal Source/Drain Ge NMOSFET,” VLSI Technology Symposium Technical Digest, pp. 54-55, 2008.

[9] B. Coss, “Dielectric Dipole Mitigated Schottky Barrier Height Tuning for Contact Resistance Reduction,” Ph.D. Thesis, The University of Dallas, Texas, 2011.

[10] A. Roy, et al., “Specific Contact Resistivity of Tunnel Barrier Contacts Used for Fermi-Level Depinning,” IEEE Electron Device Letters, Vol. 31, No. 10, p. 1077, October 2010.

[11] N. Stavitski, et al., “Systematic TLM Measurements of NiSi and PtSi Specific Contact Resistance to n- and p-Type Si in a Broad Doping Range,” Electron Device Letters, Vol. 29, No. 4, pp. 378-381, 2008.

[12] Y. Ouyang, et al., “A Computational Study on Interfacial Doping and Quantum Transport of Silicide-Silicon Contacts,” International Nanoelectronics Conference (INEC), pp. 169-170, 2010.

[13] F. Padovani and R. Stratton, “Field and Thermionic-Field Emission in Schottky Barriers,” Solid State Electronics, Vol. 9, pp. 695-707, 1966.

[14] N.G. Nilsson, “An Accurate Approximation of the Generalized Einstein Relation for Degenerate Semiconductors,” Physica Status Solidi (a) 19, p. K75, 1973.

[15] H.P.D. Lanyon and R.A. Tuft, “Bandgap Narrowing in Heavily Doped Silicon,” International Electron Device Meeting (IEDM) Technical Digest, p. 316, 1978.

[16] K. Ohuchi, et al., “Extendibility of NiPt Silicide to the 22nm Node CMOS Technology,” International Electron Device Meeting (IEDM) Technical Digest, pp. 150-153, 2008.

[17] T. Nishimura, et al., “Evidence for Strong Fermi-Level Pinning Due to Metal-Induced Gap States at Metal/Germanium Interface,” Applied Physics Letters, 91, p. 123123, 2007.

[18] H. Hasegawa and H. Ohno, “Unified Disorder Induced Gap State Model for Insulator Semiconductor and Metal-Semiconductor Interfaces,” Journal of Vacuum Science and Technology B 4 (4), p. 1130, Jul/Aug 1986.

[19] J-Y Lin, et al., “Increase in Current Density for

Metal Contacts to n-Germanium by Inserting TiO2

Interfacial Layer to Reduce Schottky Barrier Height,”

Applied Physics Letters, 98, p. 092113-1, 2011.

[20] M. Iyota, et al., “Ohmic Contact Formation on n-Type

Ge by Direct Deposition of TiN,” Applied Physics

Letters, 98, p. 192108, 2011.

[21] D. Lee, et al., “The Influence of Fermi-Level Pinning/

Depinning on the Schottky Barrier Height and

Contact Resistance in Ge/CoFeB and Ge/MgO/

CoFeB Structures,” Applied Physics Letters, 96,

p. 052514, 2010.

[22] A.V. Thathachary, et al., “Fermi-Level Depinning at

the Germanium Schottky Interface Through Sulfur

Passivation,” Applied Physics Letters, 96, p. 152108,

2010.

[23] Y. Zhou, et al., “Alleviation of Fermi-Level Pinning

Effect on Metal/Germanium Interface by Insertion

of an Ultrathin Aluminum Oxide,” Applied Physics

Letters, 93, p. 202105, 2008.

[24] M.K. Husain, et al., “High-Quality Schottky Contacts

for Limiting Leakage Currents in Ge-Based Schottky

Barrier MOSFETs,” IEEE Transactions on Electron,

Vol. 56, No. 3, p. 499, March 2009.

AUTHORKhaled Ahmed is a distinguished member of technical

staff in the Silicon Systems Group at Applied Materials.

He holds his Ph.D. in electrical engineering from North

Carolina State University.




25 Developing ReRAM







HOME

Future ReRAM

KEYWORDS

Binary Metal Oxide

Filament

Non-Volatile Memory

NVM

MIM

ReRAM

Resistive RAM

As 2D NAND approaches its scaling limit, its successor is

the subject of vigorous debate. Will it be 3D NAND or will

other promising technologies establish a foothold? ReRAM

has been overshadowed by 3D NAND, but its scalability,

speed, low-power operation, endurance, and compatibility

with established CMOS fabrication processes could make it

viable in parts of the memory market at 1x nm and beyond.

NAND (“not and” logic gate) Flash has become the

leading representative of bulk-storage memory given

the advantages of its non-volatility and low cost per

bit. Although NAND speed is limited by fundamental

operational characteristics, such as Fowler-Nordheim

tunneling, its low-power operation has made it attractive

for incorporation into both mobile phone and tablet

products, two of the major semiconductor markets

today. However, the speed with which NAND has

scaled—one generation every 1.5 years—means that it

will reach its geometric scaling limit (expected at 10nm)

within the next 3 to 5 years.

In the research community, resistive random-access

memory (ReRAM) was seen early on as a promising

non-volatile memory technology that could succeed

NAND. ReRAM sandwiches a resistive change material,

such as a binary metal oxide (MeOX), between two

terminal electrodes. Its simple architecture, and the

speed and power economy with which it operates make

it ideal for information and communication technologies

that have been evolving in the expanding world of mobile

devices (Figure 1).[1]

Developing ReRAMfor Future Memory Applications

Figure 1. Different types

of memory will play a role

in advancing mobile and

computing technologies

rather than one “universal

memory.”

Figure 1

NOR-FlashNAND-Flash

Clo

ck F

requ

ency

(H

z)

Cell Area (F2)

100 50 10 5 1

10M

1G

100M

High-Speed Graphics: Games

High-Density Work Memory: PC

High-Speed MCU: Car

Parameter Storage: IC Tag/Smart-Card

Program Storage: Mobile Phone, PDA

Data Storage: DSC, SSD, USB Memory

Low-Power Work Memory: Mobile Phone

Front-End SoC: ASSP, ASIC

High-Speed MPU: Supercomputer

High-SpeedeSRAM

SRAM

eDRAM

eFeRAM DRAM

ReRAM

eSRAM

STT-RAM

EEPROMeFlash

PRAM

Source: Reference 1.

Figure 2. Diverse

configurations of ReRAM

are being studied based

on its attractive scalability,

retention time, and read/write

times.

Challenges persist in the rapid cost scaling that has been

achieved with NAND technology, creating a considerable

economic hurdle for ReRAM to clear. And once leading-

edge device makers proposed a 3D version of NAND, in

which the 2D NAND cell string was rotated 90˚ from

horizontal to vertical, intense industry focus shifted

away from ReRAM. Although 3D NAND solves some

2D NAND scaling issues, it still faces complex process

challenges, such as creating high-mobility silicon channels,

and the deposition and etch of extremely high-aspect-

ratio (>50:1) features. If these are overcome in the near

future, it will be more difficult for ReRAM to become

cost-competitive with 3D NAND. However, if solutions

prove more elusive, ReRAM may yet become the

technology of choice in portions of the memory market.

EARLY ReRAM ReRAM was initially studied as a candidate universal

memory that combined dynamic RAM (DRAM) speed

and NAND non-volatility. Its operation is based upon

the negative resistance phenomenon (also referred to as

hysteresis) observed in the 1960s in some material

systems.[2-4] These systems demonstrate reduced resis-

tance when a current is applied. If, in their original state,

they behave as dielectrics or insulators, the process of

dielectric breakdown converts them from high resistance

to low resistance. Therefore, they can be switched from

high to low resistance and vice versa using an electrical

field to break down the insulator and current to recover it.

The negative resistance phenomenon had not received

much attention for several decades until early 2000 when

an integrated device using this phenomenon as a switch

(or two-state device) was publicized in the literature.[5,6]

Subsequent publications investigated the possibility of

using the concept in a universal memory.[7] However,

ReRAM has not yet emerged in production in any form.

Nevertheless, several benefits make it very attractive.

The first is speed. Several studies have demonstrated

by careful measurement and device design that the

switching of a ReRAM bit can be as fast as a few

nanoseconds, three to four orders of magnitude faster

than NAND.[8,9] The second benefit is the low operation

voltage, which is about 1V (except for the forming

process). This is 20 times lower than NAND’s operating

voltage. The forming process is required to induce initial

electric breakdown in the insulator layer to allow the

formation of filaments that activate subsequent switching

from a low-resistance “On” state to a high-resistance

“Off” (reset) state. The third benefit is ReRAM’s better

endurance compared to NAND's, which degrades as

device size scales down. For these reasons, research

continues on integrating ReRAM in single-stack

embedded memory and stand-alone stacked memory

configurations, as shown in Figure 2.

Figure 2

IMD-3

M0

W/L

IMD-2

IMD-1

ILD

GATE

GND

TEC

BEC

TMO

i

M1 Bit Line

RE

Diode

SharedBit Line

TopElectrode

Word Line

BottomElectrode

Inner Electrode

OuterElectrode

ReRAM Material

(a)

(b) (c)

2 - ReRAM

F F F

Source: Reference 6. Source: Reference 10. Source: Reference 10.

1 Transistor/1 Resistor ReRAM Cell 1 Diode/1 Resistor ReRAM Cell Stack Array Vertical RRAM Crossbar Array


25 Developing ReRAM






HOME

Future ReRAMFuture ReRAM

ReRAM OPERATING MECHANISMIt is now widely accepted that the mechanism for MeO

X

ReRAM is filament based, as shown in Figure 3, in which a

dielectric layer (orange color) is sandwiched in between a

top electrode (TE) and bottom electrode (BE).[11] By means

of the so-called forming process, a conduction path in the

dielectric layer is first created by breakdown, which can

be achieved in many ways, such as time-dependent

dielectric breakdown or field-induced breakdown.

Figure 4

R (Ω

)

Ic (A)

10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1

101

102

103

104

105

106

107

RIc = 0.4V

NONONO

NOHfO

2

CuO


Forming occurs only once to initiate the change in

material resistance from a high-resistance state (HRS)

to a low-resistance state (LRS). When a voltage is

applied into the conductive path, a current is generated

along with local heating. In response to both heat and

electric field, the oxygen in the film or at the interface

starts migrating into the conduction path and passivating

the atoms inside it so that dielectric behavior is

re-established. In electrical terms, this is called the

“reset.” When another field is applied, at the opposite

polarity, the oxygen is released again and through

electric field-induced migration (soft breakdown) the

conduction path is re-opened. This is called the “set.”

Filament theory has several notable characteristics.

One is the relationship between the operating current

and outcome state resistance. As shown in Figure 4, the

input energy (i.e., current) determines the resistance of

the output state.[12] This relationship has been confirmed

within several material systems, and careful device and

characterization system designs. It will be an important

factor in guiding future ReRAM product development.

APPLICATION CONSIDERATIONSSeveral key considerations affect the choice of ReRAM

applications. The first is operating current (typically

10 to 20µÅ for small devices in the 10 to 20nm range).

This results from filament formation in which

re-arrangement of oxygen atoms creates a highly

conductive path. As filament size can be as small

as a few nm (smaller than the device size), current

density is extremely high and local temperature can

be very high, posing the risk of further interaction

between materials around the filament.

The second consideration is reliability. Just as a typical

dielectric film can wear out, the ReRAM switching layer

is susceptible to wear from repeated switching between

high-resistive and low-resistive states. In addition, the

fast response of the filament is also inherently sensitive

to circuit parasitic capacitance. A peak current created

by capacitive discharge can greatly exceed the input;

this exerts tremendous force on the filament, which

Figure 3. The ReRAM

mechanism is based on

filament formation and rupture

created through electric

field-induced migration and

the corresponding electrical

processes of forming (initial

HRS to LRS), reset (LRS to

HRS), and set (HRS to LRS).

Figure 4. In filament-based

operation, the resistance of

the output state is determined

by the input energy.

will eventually need higher input energy to continue

operating. This issue can be addressed by an algorithm

that increases voltage over the bit lifetime, but this

complicates the circuit and degrades speed.

The third consideration is uniformity as related to

filament initialization, as well as filament size over the

cell lifetime. Both are highly random. Filaments are

defect- and cell-structure sensitive, being initialized

from defects at the electrode/insulator interface or

within the bulk of the insulator (e.g., a grain boundary).

These atomic-level defects form during processing and

are randomly distributed, which also inherently leads to

operational instability of the filament.

FABRICATION CHALLENGESSuccessfully commercializing ReRAM depends on its

integrability into existing baseline technologies at a

competitive cost. Fortunately it offers good compatibility

with established CMOS processes. Nevertheless, many

uncertainties and challenges face device makers tackling

this new technology.

One of these is simply the wide range of binary MeOX

materials from which to choose in fabricating the

metal-insulator-metal (MIM) cell. Among these NiO2,

TiO2, and HfO

2 have been extensively studied, and good

scaling behavior of ReRAM has been demonstrated in

a HfOX-based memory.[8] Expertise developed in high-κ

materials for CMOS gate and DRAM fabrication is

very useful in designing ReRAM structures. In general,

ReRAM’s fast response speed derives from oxygen

vacancy diffusivity near the filament; hence, ionic

motion of the material is a key consideration. At this

point, though, no one material has been definitively

identified as the best candidate for the MeOX layer.

Equally numerous are the number of possible electrode

materials (e.g., TiN, TaN, Si for the bottom; Hf/TiN, Ti/TiN

for the top), each of which raises specific interface

sensitivities that must be thoroughly analyzed. For

example, precise control of the MeOX interface will be

crucial to avoid unintentional oxygen diffusion from the

oxide memory element to the metal electrode, creating

an unwanted insulating layer. And different metals will

produce different film orientation, grain dimension, and

interface roughness that will affect filament formation.[13]

Further, the work function of the metal electrode also

needs to be considered as the On/Off resistance can be

modulated by a barrier created between the dielectric

and electrode, and, more importantly, between the

filament and electrode.

As a practical matter for bringing the technology to

production, several aspects of ReRAM development must

be greatly refined. Identifying the best materials systems

from fundamental considerations is highly desirable;

to date, reproducibility of results has been an issue as

deposition, integration, and cell operation techniques

vary. Stability of these systems with respect to memory

endurance is another critical factor in selection. And,

of course, cost will be a major determinant in guiding

choices. Moreover, as shown in Figure 2, ReRAM is being

investigated in the context of multiple architectures

that will ultimately have to converge.

Array implemention raises further issues. For example,

current technologies have not yet realized fast, low-

power, and stable operation simultaneously in these

devices. Also, unipolar switching is needed if ReRAM

is to be integrated in crosspoint array structures with a

selector diode for high-density mass storage.[14] Switching

is called unipolar when the set/reset switching operations

can be obtained using the same voltage polarity, and

bipolar when set and reset operations need opposite

voltage polarity. However, unipolar operation requires

higher current than bipolar operation. It is also less

stable; reset energy can actually perform the set

during operation.

In addition, for low-power operation, the forming

voltage must be low. Fortunately, this can be relatively

easily achieved in various oxide thin films by reducing

their thickness. Carrying this notion to its conclusion,

forming voltage can ultimately become comparable

to the set voltage, eliminating the forming process.[15]

The resultant lower switching power will translate into

faster switching speed.

Thermal management inside and outside the ReRAM

device will be a major challenge in developing high-

density 1D1R (one diode, one resistor) ReRAM arrays.

Investigating thermal properties in a heterostructure of

metal and (semiconducting) insulator layers will push

today’s leading-edge metrology to expand into 2D and

3D measurement.

Figure 3


TE

BE

Forming

TE

BE

LRS

TE

BE

HRS

Cur

rent

(A

)

Voltage (V)

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

10-7

10-6

10-5

10-4

10-3

Reset

Set

Forming


25 Developing ReRAM






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CELL OPTIMIZATIONOptimizing the ReRAM cell will require attention

to achieving low forming and reset voltages, low

programming current, high endurance, and a large On

and Off window for the resistance state. Scaling will lead

to a phase-out of the forming process, because forming

voltage decreases linearly with decreasing oxide thickness,

while maintaining the same programming current.

Several studies have also demonstrated successful use

of low-resistance oxides (e.g., oxygen deficient TiO2) to

effect a forming-free process. In the reset process, ionic

motion of oxygen vacancy dominates in electrochemical

removal of the conducting path, but accompanying

tunneling and ohmic currents consume most of the

reset power. To address this, the device structure must

include a high work function metal to suppress the

tunneling current.

Optimizing endurance will require tight control of oxygen

movement at the interface between the electrode and the

oxide layer. One method of addressing this is to add a

second, easily oxidized metal layer at the interface to serve

as an oxygen reservoir and prevent oxygen penetrating

into the electrode during the resistance switching.

The On and Off window of the resistance state in

ReRAM is larger than in other emerging non-volatile

memories (e.g., spin transfer torque). Both this and

the capacitance of the MIM structure will require

refinement.

APPLICABLE PROCESS TECHNOLOGIESFrom the film stack processing standpoint, avoiding

oxidization of the metal during thin film growth is crucial.

Therefore, tightly controlled chemistries and process

conditions will be critical. A less reactive oxidant

source, such as water, should be considered for binary

oxide deposition. Uniform growth of films 2 to 10nm

thick is typically required, for which current atomic

layer deposition (ALD) processes are well suited.

In addition, today’s chemical vapor deposition (CVD)

and radio-frequency physical vapor deposition (RFPVD)

processes can be readily tuned to control the composition,

crystalline structure, surface morphology, and

stoichiometry of the MeOX insulating films and metal

nitride electrodes that, in turn, determine ReRAM

performance and endurance. They operate in

appropriately low pressure regimes for minimizing

film damage and offer deposition rate control that

enhances uniformity, while in-situ cleaning processes

facilitate the required oxidation-free surfaces.

While each layer in the MIM stack is critical, other

aspects of integration are equally important. For example,

if the MIM cell is to be defined by a reactive ion etching

process, the quality of the cell sidewall will vitally affect

performance. This is especially important in the 1D1R

structure (center image of Figure 2), in which the device

size is on the order of 10 to 20nm and the aspect ratio

of the structure is extremely high. Specially designed

passivation will also be needed to reduce the charge or

interface state that can affect memory properties, such

as data retention.

Chemistry and plasma power will have to be carefully

controlled to minimize damage of the stack during

etch, and post-etch cleaning will also be essential. The

chemistry of the latter will have to be constituted to

avoid unintended chemical reactions with the cell. And,

as aspect ratios become more aggressive, new cleaning

techniques, such as gas chemical vapor cleaning, and

thermally-assisted surface chemical reaction and volatiles,

will be required to preserve the structural integrity of

minute features at the 1x nm node and beyond. Finally,

a dielectric layer with low charge trap states will have

to be applied to passivate the sidewalls. CVD and ALD

will be key in fulfilling deposition requirements at these

ultra-small small geometries.

As the integration scheme transitions to a more cost-

effective structure (such as that illustrated on the

right in Figure 2) processing requirements will become

topographically sensitive. Both CVD and ALD will be

used initially in achieving the requisite uniform film

deposition, but as features become more challenging

and uniformity requirements more stringent, ALD will

be the only capable method.

Cluster processing will be essential for creating film

stacks comprising tens of pairs of metal and dielectric

layers with optimized interfaces and high process

throughput. And etching 40nm contact openings at

aspect ratios exceeding 50:1 through stacks of both metal

and dielectric films will be exceptionally challenging, as

the different processes will have to be carried out in one

system using a range of chemistries and source powers.

Future ReRAMFuture ReRAM

CONCLUSIONStructural simplicity, cell scalability, and switching

speed make ReRAM an attractive complement to 3D

NAND for future non-volatile memory applications.

However, much materials and interface characterization

remains to be done to arrive at an optimized materials

system for the ReRAM cell and the most effective array

structure for achieving the desired low-power operation

for mobile devices. Fortunately, once these issues have

been resolved, ReRAM fabrication will be feasible using

established CMOS technologies, such as ALD, CVD,

and RFPVD.

REFERENCES[1] H. Akinaga and H. Shima, “Materials for ReRAM,”

presented at SRC/NSF/A*STAR Forum on 2020

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Oct. 20-21, 2009.

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in Thin Anodic Oxide Films,” J. Appl. Phys., 33,

p. 2669, 1962.

[3] K.L. Chopra, “Avalanche-Induced Negative Resistance

in Thin Oxide Films,” J. Appl. Phys., 36, p. 184, 1965.

[4] F. Argail, “Switching Phenomena in Titanium Oxide

Thin Films,” Solid State Electron. 11, p. 535, 1968.

[5] W.W. Zhuang, et al., “Novel Colossal Magnetoresistive

Thin Film Non-Volatile Resistance Random Access

Memory (RRAM),” IEDM, p. 193, 2002.

[6] I.G. Baek, et al., “Highly Scalable Non-Volatile

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[7] D.B. Strukov, et al., “The Missing Memristor Found,”

Nature, Vol. 453, p. 80, 2008.

[8] B. Govoreanu, et al., “10x10nm2 Hf/HfOX Crossbar

Resistive RAM with Excellent Performance, Reliability

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[9] C. Hermes, et al., “Analysis of Transient Currents

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[10] H.S. Yoon, et al., “Vertical Cross-Point Resistance

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[11] Larcher, et al., “Physical Modeling of HfO2 RRAM

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[12] D. Ielmini, “Modeling the Universal Set/Reset

Characteristics of Bipolar RRAM by Field- and

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[13] A. Lamperti, et al., “Study of the Interfaces in

Resistive Switching NiO Thin Films Deposited

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[14] M.J. Lee, et al., “2-Stack 1D-1R Cross-Point Structure

with Oxide Diodes as Switch Elements for High

Density Resistance RAM Applications,” IEDM,

p. 771, 2007.

[15] I-S Park, et al., “Resistance Switching Characteristics

for Non-Volatile Memory Operation of Binary Metal

Oxides,” Jpn. J. Appl. Phys., Vol. 46, pp. 2172–2174,

2007.

AUTHOREr-Xuan Ping is a managing director in the Silicon

Systems Group at Applied Materials. He holds his Ph.D.

in electrical engineering from Iowa State University.

ARTICLE CONTACT [email protected]


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