𝑔𝑚 𝐼𝐷based two-stage amplifier...

IOWA STATE UNIVERSITY Department of Electrical and Computer Engineering

𝑔𝑚 𝐼𝐷 based Two-Stage Amplifier Design

Chongli Cai

9/10/2014


Motivation• Id/(W/L) VS VG is sensitive to Vbs


Motivation• gm/Id vs VG is also sensitive to Vbs


Motivation• But gm/ID vs ID/(W/L) has fixed shape

Let’s look at the gm/Id curve of the model we are using in the lab

• With a certain current density,the gm/id value is fixed regardless of Vbs


Design Tradeoff: 𝒈𝒎 𝑰𝑫 and 𝒇𝑻

Moderate Inversion

Weak Inversion

Strong Inversiongm/Id

fT

Vod

• Weak inversion: Large gm/Id(>20S/A), but small fT• Strong inversion: Small gm/Id(<5S/A), but large fT

L=0.6um L=1.2um L=1.8um


Product of 𝒈𝒎 𝑰𝑫 and 𝒇𝑻

Vod

(gm/Id)*fTModerate Inversion

Weak Inversion

Strong Inversion

• The product of gm/Id and fT peaks in moderate inversion• Operating the transistor in moderate inversion is optimal when we value speed

and power efficiency equally. But not always the case !

L=0.6um

L=1.2um

L=1.8um


Why 𝒈𝒎 𝑰𝑫 is important ?

• gm/id curve is generated from SPICE simulation, which is linked to the actual measurement data

- Better match to the fabricated one

• gm/id value does not rely on any model equation- Avoid the design uncertainties

• gm /id Value has fixed shape regardless of transistor length

• gm/id curve is valid all over the transistor operating range

• gm/id method can reduce the design and optimization effort a lot- Once selecting one point from gm/id curve, with another design parameter the third

parameter can be easily determined- Example:

m

D m

D

g

I g

I

d

du

I W

I L

d

du

W

IL

I


How 𝒈𝒎 𝑰𝑫 related to Design Specification ?

1M 2M

3M 4M

5M

6M

7M8M

cC

LC

inV

inV

outV

biasI

DDV

ssV

• Design SpecificationGBW, SR, phase margin, power and area .etc

1

5

m

c

c

gG BW

C

ISR

C

1

1

6

6

2

1 1

3

3

o o

m c

m c

L o L c c o

m

m

g gp

g C

g Cp

C C C C C C

gp

C

6

1

3

2

2

m

c

m

m

gz

C

gz

C

1 190 tan [ ] tan ( )

| p 2 | 1

G BW G BWPM

z

1 1 1

1 1

21 1( ) * ( ) ( )

2 2

m D m

D c D

g I gG BW SR

I C I 1

6

2D

I

c

D

II

L c

IS R

C

IS R

C C

1 11 11 1 1 1 1 1

2

6 6 6 6 6 6

g / g /90 tan [( )( )( )] tan [( )( )]

g / I I g / I I

L o L c c om D D m D D

m D D c m D D

C C C C C CI I I IPM

C

• You will not gain more benefits on making M6 much larger• It is better to select the gm/id value of M6 to make it

operating in the moderate inversion. So it is valid to assume 𝐶o1 is smaller than 𝐶𝐿 in the design.

The PM can be simplified as

1 11 1 1 1 1 1

6 6 6 6 6 6

g / g /90 tan [( )( )( )] tan [( )( )]

g / I I g / I I

m D D L m D D

m D D c m D D

I I C I IPM

C

1 1

6 6

g /: k

g / I

m D

m D

IN ote

1 11 1

6 6

90 tan ( * * ) tan ( * )I I

D L D

D c D

I C IPM k k

C


How 𝒈𝒎 𝑰𝑫 related to Design Specification ?

1M 2M

3M 4M

5M

6M

7M8M

cC

LC

inV

inV

outV

biasI

DDV

ssV

• Phase Margin = 60˚

1

1

2m

D

g G BW

I SR

1

6

2D

I

c

D

II

L c

IS R

C

IS R

C C

1

6

2 21

6

(1 )( )1

tan 303

1 ( )( )

L D

c D

L D

c D

C Ik

C I

C Ik

C I

with the condition of I IISR SR 1

6

(1)2( )

cD

D L c

CI

I C C

2 21 1

6 6

3 (1 )( ) 1 ( )( ) (2 )L D L D

c D c D

C I C Ik k

C I C I

• k is determined by the gm/Id value of M1 and M6 you choose• Id1/Id6 can be determined in terms of total power consumption• Once k and current ratio are chosen, then Cc is determined • You need to use (1) to check the validity of the calculated Cc from (2)• You need to keep observing the parasitic cap at gate of M6 to make sure it is small

1 11 1

6 6

90 tan ( * * ) tan ( * )I I

D L D

D c D

I C IPM k k

C

1 1

6 6

g /k

g / I

m D

m D

I


Design Guideline

1M 2M

3M 4M

5M

6M

7M8M

cC

LC

inV

inV

outV

biasI

DDV

ssV

Amplifier Design Procedure

Step 1: Choose 𝑔𝑚1/𝐼𝐷1

Step 2: Choose 𝑔𝑚6/𝐼𝐷6

Step3: Choose 𝐼D1/𝐼𝐷6

Step 4: Calculate Cc

Step 5: Check the validity of Cc

Step 6: Size M1 & M6



1

1

1( )

2

m

D

gG BW SR

I

1 1

6 6

g /k

g / I

m D

m D

I

1

62( )

cD

D L c

CI

I C C

2 21 1

6 6

3 (1 )( ) 1 ( )( )L D L D

c D c D

C I C Ik k

C I C I

1

62( )

cD

D L c

CI

I C C

1

1

1

( ) D

du

IW

L I 6

6

6

( ) D

du

IW

L I

Gain-Bandwidth RequirementSR Specification

SR and Power Specification

PM Specification

SR Specification


Design Example – Specification

Specs Specification

Supply Voltages +/- 2.5V

Load Capacitor 2pF

Total Current <=100uA

DC Gain 75dB

Gain-bandwidth-product 25MHz

Phase Margin 60˚

Slew Rate 25MV/s


Design Step 1 to Step 5

1M 2M

3M 4M

5M

6M

7M8M

cC

LC

inV

inV

outV

biasI

DDV

ssV

Target: GBW=25MHz; SR=25V/us

1) In this case, GBW and SR are choose to be barelyon the design target

2) Choosing k = 1 , then

3) Choosing

4) Calculate Cc=443fF

5) Checking

1

1

2 * (2 * * 25 )12.56

25

m

D

g

I

1

1

1( )

2

m

D

gG BW SR

I

• You can choose the gm1/id1 to make GBW and SR barely satisfy the target

• For SR is barely at target value, choosing a large gm1/id1 can result in GBW over-designed

• For GBW is barely at target value, choosing smallgm1/ id1 can result in SR over-designed

6

6

12.56m

D

g

I

1

6

0.1D

D

I

I

1

6

( 0 .1) ( 0 .1)2( )

cD

D L c

CI

I C C

Valid

Final Value will be slightly larger due to parasitic caps

Pick-up point in moderate inversion region


Design Step 6NMOS

PMOS

gm/Id

VEB

gm/Id

VEB

6

61

6

75( ) 38

1.97du

I A W

LI A

1

11

1

7.5( ) 16

0.471du

I A W

LI A


1M 2M

3M 4M

5M

6M

7M8M

cC

LC

inV

inV

outV

biasI

DDV

ssV

Design Step 7 & 8

• M3 and M4 need to have over-drive voltage in the range of 200mV to 300mV

• For the Top three transistors M5-M7, the over-drive voltage is set to be 300mV~400mV for the purpose of reducing current mismatch, and the Vds need to be large (usually Vds>=1.5*Vod )


Simulated Result

The design is essentially “right on” the target without any tweaking

Specs Specification Simulation

Supply Voltages +/- 2.5V +/-2.5V

Total Current <=100uA 90uA

DC Gain 75dB 77dB

Gain-bandwidth-product 25MHz 25MHz

Phase Margin 60˚ 61˚

Slew Rate: SR+/- 25MV/s 22.37/25.9 MV/s


Loop Stability Simulation

• Using stb analysis in close-loop

V=0


Slew Rate Simulation


Conclusion• The key advantage of gm/Id based design is that it allows you

to transition from hand analysis to Spice simulation without much of modelling uncertainties

- Because we are incorporating the relevant simulation data into

into the design process.

• The simulation result of gm/Id based design can match the fabricated circuit well

- Because the gm/id directly carries on the device measurement

information


Questions?

𝑔𝑚 𝐼𝐷based two-stage amplifier...

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