© h. heck 2008section 4.11 module 4:metrics & methodology topic 1: synchronous timing ogi ee564...

© H. Heck 2008 Section 4.1 1

Module 4: Metrics & MethodologyTopic 1: Synchronous Timing

OGI EE564

Howard HeckTsetup Thold

clk

in


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Where Are We?

1. Introduction

2. Transmission Line Basics

3. Analysis Tools

4. Metrics & Methodology1. Synchronous Timing

2. Signal Quality

3. Source Synchronous Timing

4. Recovered Clock Timing

5. Design Methodology

5. Advanced Transmission Lines

6. Multi-Gb/s Signaling

7. Special Topics


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Contents

Synchronous Memory ElementsOperationTiming Requirements

Bus OperationClock Skew & JitterTiming Analysis – Setup and HoldManufacturability ConsiderationsSystem Timing EquationsSummary


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Synchronous Memory Elements - Operation

Operation A data signal (in) that is present at the input to the flip-flop is

“latched” into the flip-flop by the rising edge of the input clock signal (clk).

On the next rising edge of clk, the data signal is released to the output of the flip-flop (out).

Edg

e T

rigge

red

Flip

-Flo

p

outin

clk


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Synchronous Memory Elements - Timing

Timing Valid data must be present for a minimum amount of time

prior to the input clock edge to guarantee successful capture of the data. This is setup time, Tsetup.

Data must remain valid for a minimum amount of time after the input clock edge to guarantee that the proper value is captured. This is the hold time, Thold.

Tsetup Thold

clk

in


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Synchronous Bus Operation

We use the clock to control the transmission of data from the latch in the source (a) to the latch in the destination (b).

clk

D QCLK

D QCLK

a b

FR

OM

CO

RE

TO

CO

RE

We have 1 full clock cycle to get the data from a to b.

The next clock pulse causes the destination latch to capture the data that was transmitted on the interconnect

The initial clock pulse causes the source latch to release the data onto the interconnect.


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Synchronous Signaling Sequence

1. Initial (driving) clock pulse transmission from clock generator to source.

clk

D QCLK

D QCLK

a b

FR

OM

CO

RE

TO

CO

RE

Tdrv_clk(a)(1a)

Tprop_clk(a)

(1b)

a) Tdrv_clk(a) = delay of the clock buffer circuit connected to the

source (a).

b) Tprop_clk(a) = delay of the interconnect that between clk & a.

CLK @ A


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2. Data transmission from source to destination.

clk

D QCLK

D QCLK

a b

FR

OM

CO

RE

TO

CO

RE

Tdrv_clk(a)(1a)

Tprop_clk(a)

(1b)

Tdrv

(2a)

Tprop

(2b)

Tsetup

(2c)

a) Tdrv = delay of the output buffer circuit for the data signal.

b) Tprop = interconnect delay between source and destination.

c) Tsetup = delay of the input buffer plus the flip-flop setup

requirement.

CLK @ A

Data @ B

Data @ A


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3. Second (receiving) clock pulse transmission from clock generator to destination.

clk

D QCLK

D QCLK

a b

FR

OM

CO

RE

TO

CO

RE

Tdrv_clk(a)(1a)

Tprop_clk(a)

(1b)

Tdrv

(2a)

Tprop

(2b)

Tsetup

(2c)

Tdrv_clk(b)(3a)

Tprop_clk(b)

(3b)

a) Tdrv_clk(b) = delay of the clock buffer circuit connected to b.

b) Tprop_clk(b) = delay of the interconnect between clk & b.

CLK @ A

CLK @ B

Data @ B

Data @ A


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Clock Skew

What happens if the clock signals at the source and destination are not in phase? What if the clock arrives at the destination before it reaches

the source? Vice-versa?

What are the sources of uncertainty in the phase relationship between different clock signals?


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Clocks Skew Clock Skew: pin-to-pin variation in the

timing of input clock at each agent (source & destination, in our example) on a bus.

The net effect of clock skew is that it can reduce the total delay that signals are allowed to have for a

given frequency target. require larger minimum signal delays in order to avoid logic

errors. (We’ll cover this in more detail shortly.)

Clock skew is caused by: variation between the clock driver

circuits in a given part (Tdrv).

variation in the loading between different agents on the bus (CL).

variation in interconnect characteristics (Z0, d ).

CLK @ A

CLK @ B

Data @ B

Data @ A

Z0,d

Z0, d

CL

CLTdrv

TdrvClo

ck D

rive

r

b

a


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Clock Jitter

What it is: Cycle-to-cycle variation in the clock period.

IDEAL

JITTER

ACTUAL

Tcycle - Tjitter Tcycle + TjitterTcycle Tcycle + Tjitter Tcycle - Tjitter Tcycle - Tjitter

Pulse Width(Ideal)

Pulse Width(Actual)


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Clock Jitter – Causes & Effects

The net effect of clock jitter is that it can reduce the total delay that signals are allowed to have for a given frequency target. i.e. jitter can reduce the clock cycle time, as illustrated by the

diagrams on the previous page.

Clock jitter is caused by: noise in the system that affects the response of the clock

driver circuits. noise in the system that affects the transmission

characteristics of the signals.

Since they affect the operation we must consider clock skew and jitter in our timing analysis.

CLK @ A

CLK @ B

Data @ B

Data @ A


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Skew & Jitter Example 100 MHz bus

Min clock period = 10 ns

Given: Max skew = 250 ps Max edge-edge

jitter = 250 ps.

CLK @ A

CLK @ B

0.25 ns

0.25 ns

10 ns

9.5 ns

Calculate the minimum effective clock period: minimum effective period =

minimum period – maximum skew – maximum jitter min effective period = 10.0 ns – 0.25 ns – 0.25 ns = 9.5 ns

Therefore, maximum allowed for silicon plus interconnect delay is 9.5 ns.


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Setup Timing

We need to constrain the data delay such that it makes the trip from source to destination in time to meet setup requirements – while accounting for clock uncertainty.

T T T T T T Tm in setup cycle drv setup prop skew setup jitterarg _ _

For a rigorous derivation see Appendix A.

CLK @ A

CLK @ B

Data @ B

Data @ A

Tdrv

Tprop

Tskew

Tsetup

Tjitter

Tcycle

[4.1.1]


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Hold Timing

We need to constrain the data delay such that it does not arrive at the destination until the hold requirement is met – while accounting for clock uncertainty. T T T T Tm in hold drv prop hold skew holdarg _ _

CLK @ A

CLK @ B

Data @ B

Data @ A

Tdrv

Tprop

TholdTskew

[4.1.2]


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Manufacturability Considerations

Sources of variability in silicon: manufacturing process (e.g. silicon gate length) operating temperature (MOS speed as temp ) operating voltage (MOS speed as voltage )

Impact: variability leads to a range of values for driver and receiver timings

Example: Pentium® Pro GTL+ timings Minimum driver valid delay = 0.55 ns Maximum driver valid delay = 4.40 ns Maximum receiver setup time = 2.20 ns Maximum receiver hold time = 0.45 ns

Sources of interconnect variability: Manufacturing variation (Z0, r)

Trace length variation (e.g. 144 signals for FSB)


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Revised Timing Equations

The setup equation defines the minimum clock cycle time (max frequency) in terms of the maximum system delay terms. We want Tmargin_setup 0. Excessive system delays can be handled by increasing cycle

time, at the cost of reduced performance. The hold equation defines minimum system delay

requirements to avoid logic errors due to hold violations. We want Tmargin_hold 0. Minimum delay violations cannot be fixed by increasing cycle

time. Why?

Product specifications must comprehend the expected variation.

We need to modify the setup & hold equations:Setup T T T T T T Tm in setup cycle drv setup prop skew setup jitterarg _ ,min ,max ,max _

Hold T T T T Tm in hold drv prop hold skew holdarg _ ,min ,min _

[4.1.3]

[4.1.4]


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Example: Pentium® II Processor 100 MHz Host Bus Timings

GTL+ Interface Signals

SYSTEM SETUP CALCULATION (2)

Rising Edge

Path Tco,max (1) Tsetup (1) Clock Driver Skew Clock Driver Jitter PCB Clock Skew

Driver Receiver Predicted Target Predicted Target Predicted Target Predicted Target Predicted Target

DeschutesDeschutes 3.45 3.50 1.70 1.75 0.18 0.18 0.25 0.25 0.23 0.23

Deschutes440BX 3.45 3.50 1.70 3.20 0.18 0.18 0.25 0.25 0.23 0.23

440BX Deschutes 3.55 3.85 1.70 1.75 0.18 0.18 0.25 0.25 0.23 0.23

Falling Edge

Path Tco,max (1) Tsetup (1) Clock Driver Skew Clock Driver Jitter PCB Clock Skew


DeschutesDeschutes 3.45 3.50 1.70 1.75 0.18 0.18 0.25 0.25 0.23 0.23

Deschutes440BX 3.45 3.50 1.70 3.20 0.18 0.18 0.25 0.25 0.23 0.23

440BX Deschutes 3.55 3.85 1.70 1.75 0.18 0.18 0.25 0.25 0.23 0.23

SYSTEM HOLD CALCULATION (3)

Rising Edge

Path Tco,min (1) Thold (1) Clock Driver Skew PCB Clock Skew Tflight,min


DeschutesDeschutes -0.21 -0.20 0.83 0.85 0.18 0.18 0.23 0.23 1.45

Deschutes440BX -0.21 -0.20 0.40 -0.10 0.18 0.18 0.23 0.23 0.50

440BX Deschutes 0.70 0.80 0.83 0.85 0.18 0.18 0.23 0.23 0.45

Falling Edge

Path Tco,min (1) Thold (1) Clock Driver Skew PCB Clock Skew Tflight,min


DeschutesDeschutes -0.21 -0.20 0.83 0.85 0.18 0.18 0.23 0.23 1.45

Deschutes440BX -0.21 -0.20 0.40 -0.10 0.18 0.18 0.23 0.23 0.50

440BX Deschutes 0.70 0.80 0.83 0.85 0.18 0.18 0.23 0.23 0.45


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Synchronous Timing Summary

Synchronous memory elements require a stable data signal for a minimum amount of time prior to (SETUP) & after (HOLD) the input clock.

Hold and setup conditions determine the minimum and maximum system delays.

Setup and hold conditions can be analyzed by constructing timing loops in the timing diagrams.

Component delays exhibit variation across process and environmental conditions. Interconnect delays contain variations due to design and process.

Redefining driver and interconnect delays in terms of system and “spec” loads allows manufacturers to specify and test component delays.

System timing equations provide a key tool for examining trade-offs during system design.


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References

S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience), 2000, 1st edition.

W. Dally and J. Poulton, Digital Systems Engineering, Cambridge University Press, 1998.

R. Poon, Computer Circuits Electrical Design, Prentice Hall, 1st edition, 1995.

H.B.Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, 1990.

H. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, PTR Prentice Hall, 1993.

S. Dabral and T. Maloney, Basic ESD and I/O Design, John Wiley and Sons, New York, 1998.


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Appendix A: Tco & Flight Time

Return to main contents.


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Device Specs and Test Loads

Device specifications vs. system conditions The manufacturer guarantees that the parts meet the values

in the timing specifications when driving into the “spec load”. The spec load is typically equal to the load presented to the

device by the test environment. This spec load is generally not the same as the load

presented to the device by the system interconnect.

65

10pF

Spec Load System


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Impact of Spec Loads

Since the spec load is NOT equal to the load on the device when placed in a system: An output buffer will have a different delay in the system

than in the test environment.

To deal with this: define new timing terms & change the way we break the timings into separate

components.


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Flight Time

Time

Vo

ltag

e

Threshold

Clock Input to TransmittingChip

Driver Pin intoTest Load

Driver Pin intoSystem Load

Receiver Pin

Tdrv Tprop

Tco Tflight


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Define Tco (time from clock-in to data-out) as the

delay from the input clock to the output data when driving into the test load.

Define Tflight (flight time) as the delay to the

receiver minus the Tco. By defining the timings in this way, the flight time

accounts for the propagation delay of the interconnect PLUS the difference between the driver delays when driving test load vs. the system load.

Flight Time Explained

Notice: We defined Tco and Tflight this way to guarantee the

overall system timings remain the same.

flightcopropdrv TTTT


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Another Perspective

TestLoad

Tco

TflightTco

Problem: systempropco TTT

Solution: systemflightco TTT

SystemTprop

Tsystem


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Revised Timing Equations

The system designer relies on the synchronous timing equations help her/him define the working flight time window (min-to-max), given the component timing specs.

Ultimately, the equations provide a tool for the bus design team. Use them to evaluate design trade-offs in order to achieve

system performance (frequency) targets.

Setup jittersetupskewflightsetupcocyclesetupinm TTTTTTT _max,max,min,_arg

Hold holdskewholdflightcoholdinm TTTTT _min,min,_arg

[4.1.5]

[4.1.6]


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Appendix B: Synchronous Timing Equation Derivations



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Setup Timing Diagram & Loop Analysis

CLOCK@ clk input

Tprop_clk(a)

Tdrv_clk(a)

Tcycle

CLOCK(b)@ clk output

t

CLOCK(b) @ b

CLOCK(a) @ a

CLOCK(a)@ clk output

DATA @ b

DATA @ a

Tdrv

Tprop

Tmargin

Tjitter

Tprop_clk(b)

Tdrv_clk(b)

Tsetup

0 __arg__ aTaTTTTTTbTbTT clkdrvclkpropdrvpropinmsetupjitterclkpropclkdrvcycle [4.1.1a]



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Setup Timing Equation

Define Clock Delay

0 __arg__ aTaTTTTTTbTbTT clkdrvclkpropdrvpropinmsetupjitterclkpropclkdrvcycle

T T Tclk drv clk prop clk _ _

bTaTT clkclksetupskew _

T T T T T T Tm in setup cycle drv setup prop skew setup jitterarg _ _

Setup equation

Simplify

[4.1.1a]

[4.1.2a]

[4.1.3a]

[4.1.4a]

– Clock Skew



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DATA @ b

DATA @ a

Hold Timing Diagram & Loop Analysis

Tdrv_clk(b)

Tprop_clk(b)

Tdrv_clk(a)

Tprop_clk(a)

Tprop

Tdrv

CLOCK(a) @ a

CLOCK(a)@ clk output

CLOCK@ clk input

CLOCK(b)@ clk output

CLOCK(b) @ b

Tmargin_hold

Thold

t

0___arg__ bTbTTTTTaTaT clkdrvclkpropholdholdinmpropdrvclkpropclkdrv



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Hold Timing Equation

Hold equation

T T Tclk drv clk prop clk _ _

aTbTT clkclksetupskew _

0___arg__ bTbTTTTTaTaT clkdrvclkpropholdholdinmpropdrvclkpropclkdrv

T T T T Tm in hold drv prop hold skew holdarg _ _

DefineClock Delay

Simplify

Clock Skew

[4.1.5a]

[4.1.6a]

[4.1.7a]

[4.1.8a]


© h. heck 2008section 4.11 module 4:metrics & methodology topic 1: synchronous timing ogi ee564...

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