0041a bjt bias prob answers.pdf

Introductory Electronics Notes 41-1 Copyright © M H Miller: 2000The University of Michigan-Dearborn revised

BJT BIAS PROBLEMS

Problem 1)Estimate the collector current for each transistor in the diode-connected transistorbiasing circuit. shown. Compute and compare the collector currents over atemperature range -50˚C to +50˚C.

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AnswerEstimate the Q1 collector current, and so also the Q2 collector current as(10–0.7)/10 = 0.93 ma.

*Bias IllustrationVCC 1 0 DC 10RM 1 2 10KQ1 2 2 0 Q2N3904RL 1 3 4.7KQ2 3 2 0 Q2N3904.LIB EVAL.LIB.PROBE.DC TEMP -50 50 .1.END

The first plot compares the Q1 and Q2 collectorcurrents over the specified temperature range. Thereis about a 20 µa variation in current, about a 2%absolute change. The next plot shows the relative change between the two currents (normalized to theQ2 collector current.); this is less than 0.1%.


Problem 2)The current-mirror biasing circuit discussed above is redrawn to theright. Compute the circuit performance and compare with the estimatesmade before.

Answer*Current mirror illustrationRM 1 0 5KQ1 1 1 2 Q2N3906Q2 3 1 2 Q2N3906RL 3 0 5KQ3 3 0 4 Q2N3904RE 4 5 10KV+ 2 0 DC 10V- 5 0 DC -10.LIB EVAL.LIB.PROBE.DC TEMP -50 50 .2.END

PSpice computes the transistor currents as shown; estimated values calculated also are tabulated:

NAME Q1 Q2 Q3MODEL Q2N3906 Q2N3906 Q2N3904IC(computed) -1.83E-03 -2.15E-03 9.27E-04IC(calculated) -1.86E-03 -1.86E-03 9.3E-04

Note the influence of the Early Effect on the Q2 current. The computed value of Vo is 6.1 volts,while the estimated value calculated is 4.65 volts. The difference is primarily the consequence of theEarly Effect increase in the Q2 current. Nevertheless the calculation using the simpler model providesa meaningful estimate of currents. At least as important the simpler model also provides a usefulindication of the relative importance of various components in determining the currents. The computed value of Vo over a -50˚C to +50˚C temperature range is plotted next.


Problem 3)Given the circuit shown: estimate the collector current. Use thePWL model analysis above, which provides the relation

AnswerEstimate VBE as 0.7 volt. (Recall that the collector current will change an order of magnitude forroughly a 50 mv change in junction voltage, two orders of magnitude for a 0.1 volt change. Since thebase supply voltage is 4 volts an uncertainty in VBE of as much as 0.4 volt results in only a 10%change in the value of the numerator. Similarly with a minimum ß of 99 the second term in thedenominator is 0.15 KΩ compared to the first term value of 3.3 KΩ. Ignoring the second termentirely changes the denominator by less than 5%. The emitter current estimate of 0.96 ma is largelyindependent of the transistor parameters VBE and ß. A PSpice computation of the collector currentover a 100˚C temperature range is plotted below.

Problem 4)

Estimate the collector current in the PNP bias circuit shown.

AnswerReplace the BJT by the simplified PWL model described above; use

nominal transistor parameter values ß ≈120, VBE ≈ 0.7v. Note that the biasingarrangement reduces the influence of theBJT parameters in establishing the currentvalue, and so 'typical values' from manufacturer's specifications maybe used with some confidence.As described before replace the biasing resistors by their Theveninequivalent 33K||82K = 23.5K, and the Thevenin voltage(82/(82+33))10 = 7.13v to obtain the equivalent circuit as shown.Avoid the not uncommon careless topological error of confusing thePNP transistor with a NPN transistor.

Write a base-emitter loop equation as was done for the NPN configuration discussed above; againavoid the topological error confusing the emitter and collector. Solve for IC = 120IB=0.91 ma. APSpice analysis provides the collector current 0.935 ma.


Problem 5)

a) Use the expression for the emitter current derived before for the circuit shownto derive the expression to the right for changes due to variation of VBE and ß.Interpret the expression in terms of the design guidelines discussed.

b) Evaluate the following argument. Suppose the collector current consists of a DC component and asinusoidal component, i.e., ICQ + A sin (ωt). The average power provided by the source, ICQVCC, isconstant, and this is the same whether the AC signal is present or not. But the energy expended in theresistor increases since the average value of the sine-squared is not zero. Conservation of energy thenrequires the collector dissipation to be smaller with the AC signal present than in its absence. Thus thetransistor operates cooler with a signal than without! Hence for safe operation with maximum AC signalthe power rating for the transistor should be such that it is able to operate safely in the absence of an ACsignal.

Answera) The first term is the effect of a variation in VBE, and to minimize the per cent change in IE makethe variation small compared to VS-VBE. The second term is the effect off a change of ß, and tominimize the per cent change in IE make the denominator, in particular the second term, largecompared to 1.b) Maximum transistor dissipation occurs during the absence of a signal.

Problem 6)Design the transistor circuit for a ±0.1 ma variation about a nominal collector current of 1 ma. Assume arange of temperature variation of –50˚C to + 50˚C.

Answer The variation in VBE over a 100˚C temperature range is about 0.2 volt (≈ 2 mV/˚C). To besomewhat more conservative (and suggestive) write VBE = 0.65 ± 0.15 volt, allowing a bit for athreshold voltage different from 0.7 v. The current is may vary ±10%. Suppose we (arbitrarily)allocate 5% to variations in VBE, allowing the remaining 5% for ß variations. Then set VBB to aminimum of 20 times the 0.15 volt variation, or 3 volts. The numerator term then will be constrained.

To limit the effect of a ß variation the second term in the denominator is madesmall compared to RE. If we simply neglect this term we can estimate RE ≈(3-0.65)/1 = 2.35KΩ. This is not a standard value, so use a standard 10%tolerance value of 2.2KΩ. (This will tend to make the current higher than1ma; a choice of 2.5KΩ would make it smaller.)

To limit the influence of ß make RB/(ß+1) small compared to RE. If it is made less than 5% of RE forthe minimum value of ß expected then it will have less than a %% influence. Hence using a minimumvalue for ß of 100 (see manufacturers specifications) make RB = (101)RE/20 = 11.1 KΩ. Use a


standard 10% tolerance value of 10 KΩ.

A PSpice computation of collector current over the temperature range is plotted below for the nominalß and for ±50% values.


Problem 7)Assume (subject to verification) that the Q2 base current can beneglected compared to the Q1 emitter current. (Why ?) Calculate thevoltage at the collector of Q2. Assume 2N3904 devices.

Answer

The voltage across the 220Ω is less than that across the 680Ω,and hence both emitter currents are roughly in proportion to theresistors. With a ß > 100 the base currents will be an order ofmagnitude or more greater than the emitter currents.

Neglecting the Q2 base current (compared to the Q1 emittercurrent) allows the Q1 biasing to be treated independently of Q2. Hence

Determine IE(Q2) from the Q1 emitter voltage.

To substantiate the approximation used verify that the Q2 base current, ≈ 5.13/121 = 0.04 ma is smallcompared to the Q1 emitter current.

For comparison a PSpice operating point computation provides IE(Q1) = 4.3 ma and IE(Q2) = 9.98ma.

Problem 8All the transistors in the symmetrical circuit shown are identical(Use 2N3904). Determine the collector voltage of Q2. Suggestion:Determine the collector current of T3 first, and take advantage of thesymmetry of the Q1, Q2 circuitry.

Answer

Use the simplified PWL transistor model. This model neglectsthe Early Effect, and so the Q3 current can be estimated withoutexplicit knowledge of the collector voltage.

Because of the symmetry, and supposing some uniformity in nature, the collector current of Q3 isdivided equally between Q1 and Q2, i.e., IE(Q1) = IE(Q2) = 4.7 ma. Since IC(Q2) ≈ IE(Q2) the Q2collector voltage is estimated as 9 - 4.7 = 4.3 v.

For comparison a PSpice operating point computation provides the following data:

NAME Q1 Q2 Q3MODEL Q2N3904 Q2N3904 Q2N3904IC 5.39E-03 5.39E-03 1.08E-02


Problem 9Calculate the emitter current in the circuit shown. Comment: Circuitdesigners who do not verify assumptions they make are often surprised.

AnswerAssume, subject to verification, that the transistor is biased in normalforward mode, i.e., emitter forward-biased and collector reverse-biased.Replace the base biasing resistors by a Thevenin equivalent voltagesource of 9(3.3/(3.3+6.8)) = 2.94v, in series with a resistance of3.3||6.8 = 2.22KΩ. Use a nominal ß of 120 and a VBE of 0.7v toestimate the emitter current as (2.94-0.7)/(1+(2.22/121)) = 2.2 ma.

But since the collector current is essentially equal tot he emitter currentthe voltage drop across the 5.6KΩ collector resistance would be 12.3v,making the collector negative! The assumed reverse-biased state of thecollector diode is inconsistent, and the calculation is invalid. The actualcollector junction state is actually forward-biased, i.e., the transistormust be operating saturated. The PWL model in this case is as shownto the right (both diodes ON). Solve (for example) for the node voltageV = 2.2v, and so the emitter current is 1.5 ma, and the collectorcurrent is 1.2 ma. A PSpice analysis computes a collector current of 1.3 ma, and an emitter current of1.6 ma.

Problem 10Anticipate (and later verify) that both transistor base currents are smallcompared to the current in the base biasing resistors. ( That current will beroughly 10/(68+15+18) ≈ 100 µA. Neglecting the collector-emitter voltagedrops indicates that the transistor collector current will be less than10/(3.9+1) ≈ 2 mA. With ß ≈ 120 the base currents are estimated to be lessthan 20 µA.) Estimate the collector current of T2. Improve the collectorcurrent estimate by a recalculation using the base currents estimated from thefirst calculation, rather than neglecting them.

AnswerNeglecting the base currents the voltage at thebase of Q1is 10(18/(18+15+68)) = 1.78v.Estimate the Q1 emitter voltage to be 1.08v, andthe Q1 emitter current as 1.08ma. Estimate thebase voltage of Q2 to be 10((15+18)/(18+15+68))= 3.27v, and so the Q2 emitter voltage isestimated to be 2.57v. Finally the Q2 collectorvoltage is estimated to be 10 -(3.9)(1.08) =5.79v.

A PSpice netlist is shown on the right and thecomputed currents and node voltages are below.These computed results should be compared tovalues calculated as described in the problemstatement.

Cascade BiasingRB3 6 4 68KRB2 4 2 15KRB1 2 0 18KRC2 6 5 3.9KRE1 1 0 1KCV 6 0 DC 10Q2 5 4 3 Q2N3904Q1 3 2 1 Q2N3904.LIB.OP.END


NODE VOLTAGE(1) .9338 (2) 1.5973 (3) 2.3707 (4) 3.0331 5) 6.4118 (6) 10.0000

NAME Q2 Q1MODEL Q2N3904 Q2N3904IBC 6.73E-06 6.98E-06IC 9.20E-04 9.27E-04BE 6.62E-01 6.64E-01BC -3.38E+00 -7.73E-01CV 4.04E+00 1.44E+00

Problem 11Calculate the collector voltage of Q2. Assume 2N3904 devices. Refer to thediscussion above for simplifying suggestions.

AnswerNeglect the base current of Q2 relative to I, the collector current of Q1,and write the loop equation as described above:

9 = 3.3I + 0.7 + 47(I/120) + 0.7

to determine I ≈ 2.06 ma. The estimate the Q1 collector voltage as 9 -(2.06)(3.3) = 2.2 v. The Q2 emitter voltage then is ≈1.5 v, and the Q2emitter current is 1(1.5/1) + (1.5 - 0.7)/47 = 1.52ma. A PSpicecomputation gives the collector current of Q1 as 2.1ma and the collector current of Q2 as 1.36ma.

Problem 12Determine the Q2 collector voltage for the complementary pair' biasingconfiguration shown. Assume 2N3904 and 2N3906 devices.

AnswerNote that the Q2 emitter current is about the same magnitude as theQ1 collector current. The Q2 base current should be negligiblecompared to the Q1 collector current (an assumption to be verified),and if this approximation is applied calculation of the Q1 biasing is independent of Q2. Determine thatthe Q1 emitter current is 1.15ma. The Q1 collector voltage then is 8.21v, and so the Q2 emitter currentis estimated to be 2.0ma. The currents are consistent with neglecting the base currents.

Node voltages and device currents computed by PSpice are shown below.

NODE VOLTAGE(1) 3.2453 (2) 8.1928 (3) 2.5773 (4) 12.0000 (5) 8.9131 (6) 4.5061

NAME Q1 Q2MODEL Q2N3904 Q2N3906IC 1.16E-03 -2.05E-03


Problem 13A forward-biased junction operates over large current ranges with small voltagechanges. The bias circuit shown takes advantage of this to reduce sensitivity tosupply voltage variations. I0, assumed to have been made large compared to thebase currents, is (approx.) (VCC - 2VBE)/R0. This current biases Q1 so as toprovide a voltage VBE across R1, so that the Q2 emitter current is approximatelyVBE/R. And VBE is relatively insensitive to changes in VCC. For R0 = 8.2KΩ, R =470Ω, and VCC = 10 volts estimate the Q2 collector current. Assume 2N3904devices. Use PSpice to step VCC from 0 to 10 volts, and plot IC(Q2) vs VCC.

AnswerAssuming a nominal value of 0.7 volt for VBE the Q2 collector current would be approximately0.7/.47 = 1.49ma. This assumes that VCC is sufficiently large to forward-bias both emitter junctions,i.e., VCC > 1.4v. A netlist is shown to the right and the PSpice computations are plotted below.Junction Voltage BiasRO3 2 8.2KQ1 2 1 0 Q2N3904Q2 4 2 1 Q2N3904R1 1 0 470VCC 3 0 DC 10V+ 4 0 DC 10.DC LIN VCC 0 10 .1.PROBE.OP.LIB EVAL.LIB.END


Problem 14) Calculate (approximately) the transfer characteristicVout vs. Vin for the circuit shown, for -1v ≤ Vin ≤ 1v. Compare thecalculated prediction against a computed plot.

AnswerUseful approximate information can be obtained from not much more than inspection of the circuitdiagram (with the PWL BJT model in mind as a guide). Suppose for example Vin is such that thetransistor is operating in the normal forward active mode. An upper limit on the collector current isobtained by ignoring the collector-emitter voltage drop; IC <1 0/5.6 = 1.8 ma. The base currentmore than likely will be negligible compared to the other currents the base node; assume this to makeestimates (subsequently verifying the adequacy of the approximation from the estimates). Neglectingthe base current, and allowing for a nominal 0.7 volt emitter junction voltage drop [Vout - 0.7]/10 ≈[0.7 - Vin]/1.8 or Vout ≈ 4.59–5.56Vin. The voltage gain, i.e., the slope of this line, is -5.56.

When the transistor is just cutoff the emitter junction voltage is 0.7v, and the transistor draws nocurrent. Hence

The transistor saturates when the current drawn through the 5.6KΩ collector resistor reduces Vout to(roughly) 0.7 volts.

The estimates are superimposed on a PROBE plot of the transfer characteristic.


Problem 15) Calculate (approximately) the transfercharacteristic Vout vs Vin for the circuit shown, for 0 ≤ V in ≤10v. Compare the calculated prediction against a computed plot.

Answer Assuming normal operating mode the 2N3906transistor is (approximately) a DC current source with a collectorcurrent of

Note that 22||68 = 16.6K and the ß term in the calculation of the emitter current is relatively small ifß >>16.6/2.2 = 7.56.

The PNP current splits between the 5.6K load and the NPN collector; the latter transistor also is assumedto operate in normal mode for the present calculation.

Saturation of the NPN transistor occurs when the collector-emitter voltage of Q1 is approximately zero,i.e.,

This condition occurs when Vin ≈ V(3) ≈ 2.7v.

With Q1 saturated increasing Vin increases the Q1 emittercurrent but decreases the collector current. Hence V(4) ≈ V(3)≈ Vin begins to increase. Eventually Q2 will saturate but we donot consider that region of operation further; it is not a region ofparticularly useful operation.

At the other extreme the NPN device is cut off for Vin ≈ 0 ( ormore nearly a few tenths volt), and Vout ≈ (1.27)(5.6) = 7.1v.

An estimate for the transfer characteristic is as drawn to theright.

* Inverter IllustrationVIN 1 0 DC 0RIN 1 2 1KQ1 4 2 3 Q2N3904RE1 3 0 2.2KRB21 5 0 68KRB22 7 5 22KQ2 4 5 6 Q2N3906RE2 7 6 2.2KVCC 7 0 DC 15RL 4 0 5.6K

.LIB EVAL.LIB

.OP

.DC VIN 0 15 .05

.PROBE

.END


A computed characteristic (PSpice netlist follows) is plotted below.

0041a bjt bias prob answers.pdf

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