1530 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 7, JULY 2006

A Cellular-Band CDMA 0.25-m CMOS LNALinearized Using Active Post-DistortionNamsoo Kim, Vladimir Aparin, Kenneth Barnett, and Charles Persico, Member, IEEE

AbstractThe theory of a linearization method using activepost-distortion (APD) is explained for low-frequency and high-fre-quency applications. The low-frequency cancellation is explainedin power series format and the high-frequency cancellation isexplained in Volterra series format. The method is utilized for acellular band (869894 MHz) CDMA low-noise amplifier (LNA),which is implemented in 0.25- m CMOS process. The LNAachieves 1.2 dB NF, 16.2 dB power gain, and +8 dBm IIP3 whileconsuming 12 mA current from 2.6 V supply voltage. It shows13.5 dB of IM3 product reduction with 0.15 dB NF penalty incomparison with an LNA which does not use the APD method.

Index TermsIM3 cancellation, linearity, low-noise amplifier(LNA), RF CMOS.

I. INTRODUCTION

I N A CDMA receiver (Rx) system, the linearity becomes acritical parameter due to so-called cross modulation distor-tion (XMD) [1]. Once the signal-to-noise ratio (SNR) is de-graded at the low-noise amplifier (LNA) by XMD, designing thefollowing stages may be difficult in terms of the linearity per-formance of the mixer and the phase noise requirement of thevoltage-controlled oscillator (VCO). Therefore, having a highlylinear LNA can alleviate the performance requirement of theother blocks, which will return low power consumption and lesssilicon area.

There have been some efforts to improve the linearity perfor-mance of the LNA for CMOS technology [2], [3]. The modifiedderivative super-position (MDS) method is very attractive be-cause it can increase linearity significantly with wide DC op-erating range [2]. The MDS method uses two input field-ef-fect transistors (FETs) biased at different operating regions. Themain path needs to be biased at the saturation region to havenegative polarity of the second-order derivative of transconduc-tance. In contrast to that, the auxiliary path needs to be bi-ased at the linear operating region to have positive polarity ofthe second-order derivative of transconductance. The penaltyof using the MDS method is that the subthreshold-biased FETgenerates more noise than the saturation-region biased one [2].The additional input parasitic capacitance from the auxiliarypath FET is another penalty as well. Another technique usingfeed-forward cancellation is introduced in [3]. This method isuseful for differential application but requires an additional ex-ternal power splitter which would be a cost increase.

This paper describes a new linearity improvement tech-nique using post-distortion. The active post-distortion (APD)

Manuscript received October 21, 2005; revised January 24, 2006.The authors are with Qualcomm, San Diego, CA 92122 USA (e-mail:

nkim@qualcomm.com).Digital Object Identifier 10.1109/JSSC.2006.873909

Fig. 1. Schematic diagram of APD method.

method does not need to have a subthreshold-biased FET oran additional external power splitter. This paper is organizedas follows. Section II explains the low-frequency theory of theAPD method in power series format. Section III explains thehigh-frequency theory of the APD method in Volterra seriesformat. Section IV shows the noise figure (NF) effects of usingthe APD method. Section V describes the LNA design andshows measured results. Section VI concludes the paper.

II. LOW-FREQUENCY THEORY OF APD METHODThe simplified schematic diagram of the LNA using the APD

method is shown in Fig. 1, where and form the mainsignal path, and and form the auxiliary path used fordistortion cancellation.

At low frequency, where the memory elements, such as ca-pacitor and inductor, do not play a role, we can assume the de-generation inductor as a short. From the conventional rep-resention of time-invarying memoryless nonlinear system, thedrain current of can be modeled by the following powerseries:

(1)where is the small-signal transconductance, is the first-order derivative of , is the second-order derivative of andhigher order derivatives of . For the small-signal and weaklynonlinear case, nonlinearity higher than third order can be ig-nored. Assuming that is linear, the nonlinear gate voltage for

( ) and the drain current of can be expressed by(2.1)

(2.2)

0018-9200/$20.00 2006 IEEE

KIM et al.: CELLULAR-BAND CDMA 0.25- m CMOS LNA LINEARIZED USING ACTIVE POST-DISTORTION 1531

Fig. 2. Low-frequency cancellation.

where and are the ratio of transconductance betweenand and between and , respectively. Inserting (1)and (2.1) into (2.2) and combining with , we can find thetransconductance and third-order nonlinearity of the outputcurrent:

(3)

As can be seen, the gain loss is directly related to the andratio. The third-order nonlinearity term consists of the

third-order nonlinearity and the second-order nonlinearity.With given width and power consumption, we can solve equa-tions to make the third-order nonlinearity zero. The value ofneeds to be optimized to prevent too much gain loss. Let ,then the solution brings in our specific application.Since the transconductance is dependant on bias condition, thecancellation is fairly dependant on bias conditions with fixedand as shown in Fig. 2.

III. HIGH-FREQUENCY THEORY OF APD METHODSince the application is for CDMA cellular band, which is

around 900 MHz, the memory elements will affect nonlinearityperformance with frequency dependency. The simplified equiv-alent circuit for such a high-frequency application can be de-picted as in Fig. 3, where is the input matching element,

is gate-to-source capacitance of , is gate-to-sourcevoltage across , and is source degeneration inductance.The nonlinearity we will consider is only from and ; inother words, the cascade devices are assumed to be linear de-vices.

In high-frequency applications, the second harmonicwith second-order nonlinearity will contribute to the third-orderinter-modulation distortion (IMD3) due to memory elements.Conceptually, it can be explained that the at the sourcenode of the input device can mix with at the gate node suchthat IMD3 is generated.

The nonlinear output current of the APD method can be ex-pressed in weakly nonlinear region by the Volterra series expres-sion [4]

(4)

Fig. 3. High-frequency equivalent circuit of APD method.

where is the Laplace transform of theth-order Volterra kernel and the operator means that

each spectral component of is to be multiplied by themagnitude of and shifted by the phase of

. To derive the Volterra kernels, the fol-lowing assumptions are made.

All parasitic capacitances are negligible except . All DC resistances related to source and drain node are zero

including degeneration inductance. of are zero, i.e., body effects are negligible. The input signal is small enough such that the LNA oper-

ates in the weakly nonlinear region.Based on the above assumptions, a simplified high-frequencyequivalent circuit is shown in Fig. 3. The gate-to-source voltageof the input device of main path can be expressed as a functionof :

(5)This nonlinear voltage will generate nonlinear current, , andthat current will generate another nonlinear voltage, , whichwill drive and generate nonlinear current to be cancelledwith . The third-order nonlinearity cancellation mechanismis shown in Fig. 4. The nonlinearity generated by can bedescribed by:

: second and third-order nonlinearity generated byand attenuated by ;

: second-order nonlinearity of incorporating withsecond-order nonlinearity of and second-order har-monic;

: third-order nonlinearity of .By adjusting and values, the amplitude and phase of thesenonlinearity can be optimized such that the maximum IIP3 canbe achieved. The mathematical expression for , , and for

and for can be derived by using nominal VolterraSeries analysis.

(6)(7)

1532 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 7, JULY 2006

Fig. 4. Cancellation mechanism of APD method at high frequency.

(8)(9)

where

(10)

(11)

(12)

Inserting (10), (11), and (12) into (6), (7), (8), and (9) and as-suming conjugate match at and

to be much smaller than and , we can derive thethird-order inter-modulation distortion (IM3) of the output cur-rent:

IM3

(13)

As in the low-frequency case, (13) can be solved with givenwidth and power consumption for maximum IIP3 performance.To show the high-frequency effects, (13) is solved with samevalue as in low-frequency case, and the plot is shown in Fig. 5. Itis clear that the low-frequency solution is not any more optimumfor high-frequency application due to second-order nonlinearitycooperating with second harmonic.

IV. EFFECT OF APD METHOD ON NOISEUnlike the MDS method, the APD method does not require a

subthreshold-biased FET which will cause noticeable increaseof noise figure. The noise from will be the same as inthe conventional inductively degenerated LNA. In the APD

Fig. 5. High-frequency cancellation at 880 MHz.

method, the additional noise contribution from the cancellationpath needs to be considered. The gate-induced noise fromat output can be expressed as

(14)

where

(15)

where is total gate-to-source capacitance related toand , is Boltzmans constant, is absolute temperature,is the bias-dependant constant which is 4/3 in the long-channeldevice, is drain-source conductance with zero , and

is gate-to-source capacitance of . The drain currentoutput noise of can be derived as

(16)

where is a bias-dependant constant, usually 2/3 in a long-channel device. Since is equal to in a long-channel device,(16) could be true if we assume no short-channel effects. As canbe seen from (14) and (16), increasing minimizes the noisefigure performance penalty which agrees with less gain loss.

V. LNA DESIGN USING APD METHODAND MEASURED RESULTS

As described in Sections II and III, the transconductanceratios of and need to be optimized to get the best can-cellation effect with reasonable power consumption and gainloss. The designed LNA has the same architecture as in Fig. 1with additional attenuation modes achieving 8 dB and 20dB gains. The designed LNA has electrostatic discharge (ESD)protection diodes at input and out pad as well. The simplifiedschematic of the LNA designed for CDMA cellular bandapplication is shown in Fig. 6. The main path input device sizeand degeneration inductance were chosen to have optimumnoise figure performance with high power gain. After that, theauxiliary path input device and cascade device were sized basedon and ratio to reduce noise penalty and gain loss.

The LNA is manufactured with 0.25- m Si CMOSfour-metal one-poly (4M1P) process and packaged with

KIM et al.: CELLULAR-BAND CDMA 0.25- m CMOS LNA LINEARIZED USING ACTIVE POST-DISTORTION 1533

Fig. 6. Simplified schematic of designed LNA.

Fig. 7. Measured performances at 880 MHz.

BCC 32 pin. The measured results show that the LNA has16.2 dB power gain, 1.2 dB noise figure, and 8 dBm IIP3while consuming 12 mA current from 2.6 V power supply.The measured power gain, noise figure, IIP3, and power con-sumption are shown in Fig. 7 along with various gate voltages.The measured IIP3 performance with various power levels aremeasured and shown in Fig. 8. The input and output returnlosses are measured less than 10 dB, shown in Fig. 9. TheLNA was measured with cancellation path on and off to showthe auxiliary path effects. The gain difference is around 1.3 dBwhile the noise figure difference is around 0.15 dB, whichmeans the power gain is 17.5 dB and the noise figure is 1.05 dBwith cancellation path off. The IM3 cancellation is about13.5 dB, which improves IIP3 performance to 8 dBm from

2.25 dBm when cancellation is off. The LNA is designed tohave optimized IIP3 and noise figure performance with 10 mAcurrent consumption and to reduce 20 dB of IM3 distortion.But the other effects such as body effect and short-channeleffects, which are assumed to be ignorable, seem to causethe offset between designed and measured performances. The

Fig. 8. Measured IIP3 curve at 880 MHz.

Fig. 9. Measured input and output return loss.

additional advantage of this approach is that whenever highIIP3 performance is not required, the auxiliary path can beturned off and the current consumption can be reduced untilit has the same gain and noise figure performance as in thecancellation-path-on case. The designed LNA shows that it canachieve 16 dB power gain, 1.2 dB noise figure, and 2.5 dBmIIP3 with 5 mA current consumption.

VI. CONCLUSIONWe have analyzed a CMOS LNA using the APD method to

increase linearity performance. The theory of the APD methodis explained for low- and high-frequency applications and thenoise figure effects caused by the APD method are investigatedas well. The LNA is implemented for CDMA cellular bandapplication and shows good agreement with analytical results.The measured results of the APD method shows that it can im-prove linearity performance with small noise figure and gainloss penalty.

1534 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 7, JULY 2006

REFERENCES[1] V. Aparin and L. E. Larson, Analysis and reduction of cross-mod-

ulation distortion in CDMA receivers, IEEE Trans. Microw. TheoryTech., vol. 51, no. 5, pp. 15911602, May 2003.

[2] , Modified derivative superposition method for linearizing FETLOW-noise amplifiers, IEEE Trans. Microw. Theory Tech., vol. 53,no. 2, pp. 571581, Feb. 2005.

[3] Y. Ding and R. Harjani, A +18 dBm IIP3 LNA in 0.35 m CMOS,in IEEE ISSCC Dig. Tech. Papers, Feb. 2001, pp. 162163.

[4] S. Mass, Nonlinear Microwave Circuits. Norwood, MA: ArtechHouse, 1988.

NamSoo Kim received the B.S. degree in semi-conductor science from Dongguk University, Seoul,Korea, in 1998, and the M.Eng. degree in electricalengineering from Information and CommunicationUniversity (ICU), Daejon, Korea, in 2000.

From 2000 to 2001, he was involved in the designand testing of CMOS RF ICs in the Micro-ElectronicResearch Center at the Electronic and Telecom-munication Research Institute (ETRI). From 2001to 2002, he was with Ashvattha Semiconductordesigning SiGe BiCMOS RFICs for GSM receiver

systems. Since 2002, he has been with Qualcomm, San Diego, CA, designingRFIC products for CDMA systems.

Vladimir Aparin received the Diploma of Engineer-Physicist degree (with honors) in electronics and au-tomatics from the Moscow Institute of Electronic En-gineering (MIEE), Moscow, USRR, in 1989, and iscurrently working toward the Ph.D. degree in elec-trical engineering at the University of California atSan Diego, La Jolla.

From 1987 to 1992, he was involved in the designand testing of high-speed analog and digital GaAsICs, in the device modeling and characterization atMIEE. From 1992 to 1996, he was with Hittite Mi-

crowave Corporation designing GaAs and Si BiCMOS RFICs for communi-

cation systems. Since 1996, he has been with Qualcomm, San Diego, CA, de-signing RFIC products for CDMA systems. He is a coauthor of nine patents andmany technical papers.

Kenneth Barnett received the B.S.E.E. andM.S.E.E. degrees from the Georgia Institute of Tech-nology in Atlanta, in 1990 and 1992, respectively.

In 1992, he joined the Motorola Paging ProductsGroup, Boynton Beach, FL. While there, he helpeddevelop small antenna structures for paging products,worked on systems for tracking and rangefinding forlocation based paging systems using time of arrivaltechniques, and developed low-voltage, low-power,low-phase-noise integrated VCOs for paging prod-ucts. In 1999, he joined Qualcomm, San Diego, CA.

While there, he has worked on numerous projects related to highly integrated TXand RX chips for CDMA and WCDMA applications. He is currently workingon RF CMOS IC implementations for digital video standards such as DVB-Hand MediaFLO.

Charles J. Persico (S85M91) was born in 1960in Schenectady, NY. He received the B.S. degree inelectrical engineering from Union College, Schenec-tady, in 1985 and the M.S. degree in electrical engi-neering from Syracuse University, Syracuse, NY, in1987.

In 1985, he joined GE Avionics Systems workingon advanced radar systems. He has also worked atHoneywell Space Systems on various satellite elec-tronic systems. In 1991, he joined Philips Semicon-ductor and was involved in RFIC design for various

cellular standards. In 1995, he joined Qualcomm, San Diego, CA. Currently,he is Senior Vice President of Engineering at Qualcomm, responsible for RF,analog and mixed-signal IC design/ product/test engineering. His research in-terests include RF systems and RF/analog IC design as applied to cellular anddigital broadcast standards.