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    The original analog signal filtered by an anti-aliasing filter to remove any high-frequency

    components

    The signal is sampled and hold and then converted into a digitalsignal

    Next the DAC converts the digital signal back into ananalog signal. Note that the output of the DAC is not as "smooth" as the original

    signal.

    LPF returns the analog signal back to its original form (plus phaseshift introduced from the conversions)

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    Figures from CMOS Circuit Design,Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    NYQUIST CRITERION

    Defines how fast the sampling rate needs to be to

    represent an analog signal accurately.

    This criterion requires that the sampiing rate is at least

    two times the highest frequency contained in the

    analog signal.

    In our example, we need to know how quickly the weather

    can change and then take samples twice as fast as that value.

    The Nyquist Criterion can be described as

    Fsampling 2.Fmax

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    Figures from CMOS Circuit Design,Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Sample Mode

    the time required for the S/H to track the analog signal within a specified toleranceis known as the acquisition time

    if the input changes very quickly, then the output of the T/H could be limited by theamplifier's slew rate

    The amp stability is extremely critical. If the amplifier is not compensated correctly,and the phase margin is too small, then a large overshoot will occur. A largeovershoot requires a longer settling time for the S/H to settle within the specifiedtolerance.

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    Hold mode

    pedestal error occurs as changing its voltage.

    Droop, the leakage of current from thecapacitor due to parasitic impedance,

    Figures from CMOS Circuit Design,Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Aperture error The aperture time actually varies slightly as a result of noise on

    the hold-control signal and the value of the input signal. Aperture uncertainty/jitter -> sampling error

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    Figures from CMOS Circuit Design,Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout, and Simulation, Copyright

    Wiley-IEEE, CMOSedu.com

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    Figures from CMOS Circuit Design,

    Layout and Simulation Copyright