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Accuracy Limitations of Pipelined ADCs

Patrick J. Quinn

XilinxCitywest Business Campus

Logic Drive, Dublin, Ireland

Arthur H.M. van Roermund

Eindhoven University of TechnologyDepartment of Electrical Engineering

5600 MB Eindhoven, The Netherlands

Abstract In this paper, the key characteristics of the main

errors which affect the performance of a switched capacitor

pipelined ADC are presented and their effects on the ADC

transfer characteristics demonstrated. Clear and concise

relationships are developed to aid optimized design of the

pipeline ADC and error bounds are derived.

I. INTRODUCTION

Previous authors [1],[2],[3] have presented generalized anal-yses of the switched capacitor (SC) pipeline but a more compre-

hensive analysis is needed to aid its exact design. The analysis in

this paper includes, for instance, a model for capacitor mismatch,

slewing behaviour and an exact choice of capacitor sizing based

on the ADC resolution and hence noise specification.

The lowest resolution stage, using redundant-signed-digit

decoding and delivering one effective output bit, is the most

effective for achieving high throughput with high accuracy and

low power [1],[2]. The ideal transfer gain of the converter stage

is 2, while the residue equation is

, (1)

where data bits Di have values of 0 (for falling within), or -1 (for falling below ) or +1 (for

going above ). In reality, the residue voltage is affected

by a number of non-idealities associated with practical imple-

mentation which cause deviations from the ideal linear ADC

transfer characteristic. Familiarity with the effect a particular

error can have on the ADC transfer will help identify the source

of any serious errors should they arise in fabrication. The most

important errors are explored and quantified in the following sec-

tions, while the effects the errors have on the ADC transfer char-

acteristics are illustrated. Error bounds are derived to ensure the

ADC specification is met.

II. CONTEMPORARY PIPELINE ADC STAGE

The typical implementation of a SC pipeline ADC stage (1-bit

effective output) is depicted in Fig. 1 and is based on charge transfer

techniques [2],[3]. In the bottom path, the sub-ADC (just 2

comparators with thresholds set at ) reacts instanta-

neously to the analog input signal to produce a coarse digital

representation. The resultant digital code is output to a digital

decoder, while at the same time it is converted back to its

gained-up analog equivalent by the equally coarse multiplying

DAC (MDAC). The MDAC performs the level shifting, analog

multiplication by 2 and sample-and-hold buffering needed to pro-

duce the stage analog residue. On clk1, theVin is sampled on toC1

andC2 in parallel, while at the same time the sub-ADC determines

whether it falls into the top, middle or bottom of the ADC reference

range. At the end of the clk1, Vin is completely sampled on to C1

and C2, while the output of the sub-ADC is latched and held. On

clk2,C1 is switched and placed across the amplifier, closing its neg-

ative feedback loop, while at the same time only one of the input

switches ofC2 is closed by the sub-DAC using only one of clock

signals top, mid, bot, connecting C2 to either +Vref, 0, or -Vref. By

choosing C1 = C2, a nominal transfer gain of is

achieved. Note that the analysis which follows can be applied to

other implementations of MDAC, for instance, reference [2].

III. LUMPED ERROR MODEL

Each ADC pipeline stage is specified such that all accumulated

errors at the end of the conversion process remain inside 1/2LSB.

Although 1LSB is enough for monotonicity, 1/2LSB is specified

to be safe. The total fractional error is the accumulation of all

errors from theNS stages referred back to the ADC input, i.e.

, (2)

where is the net fractional stage error. Usually 1-bit redun-

dancy is employed per stage for redundant-signed digit

decoding [1] so that for a K-bit stage, K-1 bits are effectively

resolved and the stage gain factor becomes . Hence

. (3)

The magnitude of the largest allowed total input referred voltage

error is

2i iout in i ref

V V D V = -

iinV4refV iinV 4refV- iinV

4refV+

4refV

2 11 2C C+ =

Fig. 1 Contemporary single-ended SC charge transferimplementation of pipeline ADC stage (K=2)

2

2

(AnalogResidue)

C1

C2clk1

clk2

clk1

clk1

Vref

4

Vref4

Latches

and

Clkgen

top

mid

bot

Vref

Vref

top

mid

bot

bMSB bLSB

MDAC

Sub-ADC

Vini

Vout i

tot

e

1

1

i

i

j

j

NS

totGi

ee

==

=

ie

12KiG

-=

( )12

1

i

K i

NS

tot

i

ee -

==

19560-7803-8834-8/05/$20.00 2005 IEEE.

Authorized licensed use limited to: TEXAS INSTRUMENTS VIRTUAL LIBRARY. Downloaded on August 05,2010 at 05:46:57 UTC from IEEE Xplore. Restrictions apply.

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. (4)The magnitude of the total voltage error should be less than 1/2

LSB to reliably guarantee monotonicity, i.e.

. (5)

Alternatively, each individual stage should be designed to have

a total voltage error less than 1/4 LSB of the total effective reso-

lution of the remaining stages. Note that this is approximately at

the level of the quantization noise error of the remaining stages,

which is . Assuming each stage i isK-bits, the

total fractional output error is specified as

. (6)

The stage error arises from the addition of all the errors from var-

ious static and dynamic sources. Usually, the stage is

designed such that the dynamic and static errors add up in roughly

equal measure. Hence, for the usualK=2-bit stage, the following

conditions are set for of each stage in order to ensure a

robust design:

. (7)

The various sources of static and dynamic errors are described in

the following sections.

The worst-caseINL can be evaluated from the standard devi-ation (stot) of the total equivalent input error. The error should be

obtained for the expected worst case code transition, for instance

when crosses . Assuming a Gaussian distribution for

the voltage difference between the actual and ideal transfers,

theINL can be obtained as the expected value of :

(8)

IV. LIMITATIONSON STATIC ACCURACY

A. Offset Errors

There are two basic forms of offset which have different

effects on the ADC transfer. Firstly, there is input offset which

adds up with the input signal to the stage. This offset is due mainly

to the amplifier and to a lesser extent to the switches. The transfer

function in this case is of the form:

, (9)

where the offset gets multiplied up by the stage gain. The second

form of offset is that due to the comparators which has the effect

of shifting either one or both decision levels of the sub-ADC.

The total offset from all sources must remain within the

bounds of to avoid saturating the following stage and

causing missing codes. This requirement is not dependent on the

required accuracy of the whole ADC, nor indeed accuracy of each

individual stage. The offset accumulates according to equation

(2) though, so that some low offset ADC applications may need

some kind of active offset cancellation mechanism.

In Fig. 2, the effects of input offset going beyond are

shown. The grey curves show the ideal and the black the non-ideal

transfers. Consider Fig. 2(a),(b), where the input offset goes beyond

: the ADC transfer characteristic shows a single wide code

for when the stage output voltage exceeds +Vref, followed by miss-

ing codes, the number of which depends on how much the stage out-put voltage exceeds +Vref. In Fig. 2(c),(d), the input offset goes

under , in which case the ADC characteristic first has

missing codes followed by a single wide code. In Fig. 3, the separate

effect of sub-adc comparator offsets exceeding in stage

2 are demonstrated for both the top and bottom comparators.

B. Capacitor mismatch gain errors

The generalized transfer function of the ADC stage including

capacitor mismatch errors is

, (10)

tot tot ref V Ve e

( )212 2 21

2

ref

N

N

VLSBtot ref

tot

Ve

e

=

fi

1 12 1/4LSB

( )

( )

1

1 1

214 2

1

2

ref

N K i

N K i

V

i ref

i

Ve

e

- -

- - +

fi

Fig. 2 Effects of excessive input offset on ADC transfers

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

(d) ADC transfer with stage 1 offset=-5Vref/16

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

(c) Stage 1 transfer with offset=-5Vref/16

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

(a) Stage 1 transfer with offset=+5Vref/16

ideal

non-ideal

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

(b) ADC transfer with stage 1 offset=+5Vref/16

widecode

missingcodes

Fig. 3 Effects of excessive stage 2 compr offsets on ADC transfers

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vo

ut

Vref

(c) After stage 2 with top comp offset = -3Vref/8

(d) ADC with stage 2 bott comp offset = -3Vref/8

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

out

ref

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vo

ut

Vref

(b) ADC with stage 2 bott comp offset = +3Vref/8

(a) After stage 2 with bott comp offset = +3Vref/8

( )se ( )de

s d,e e

( )22

N i

s,de- - +

inV 4refV

e

e2

22

2

1

2

2

tot

tot

tot

INL E e d

e

s

p s

p

e e e

s

-

-

= =

=

( )2i i inout in off i ref

V V V D V = + -

4refV

4refV

4refV+

4refV-

4refV

( ) ( )22 1 1ci iout in i ref cV V D V D= + - + D

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where represents the mismatch of nominally equal capacitors

C1 andC2. The capacitor matching requirement for the i-th 2-bit-

stage is

, (11)

An important observation with this kind of gain error is that there

is always an exact mapping of input values to output values, irre-

spective of :

. (12)

This suggests a very effective way of calibrating out capacitor

mismatch errors by extrapolating between these correctly

mapped points.

The effects of capacitor mismatch errors in stage 1 are illus-

trated in Fig. 4 Positive capacitor mismatch errors (Fig. 4(a),(b))

cause a series of wide codes and negative code jumps resulting

in non-monotonicity. Negative capacitor mismatch errors (Fig.

4(c),(d)), on the other hand, cause a series of narrow codes and

positive code jumps, resulting in missing codes. Fig. 5(a),(b)

show the result of positive capacitor mismatch in stage 2. Here

again there are wide codes corresponding to the six transition

points from the ADC input to the second stage output. Further-

more, there are also two sets of missing codes at which

are the transition points of the previous stage. A similar scenario

exists for negative capacitor ratio errors (Fig. 5(c),(d)), except

that wide codes are replaced by narrow codes and negative and

positive code jumps are interchanged.

C. Amplifier Gain Errors

The OTA, in a switched-capacitor configuration of any stage

i along the pipeline, must linearly amplify the input voltage by a

factor of 2 over the full scale range of -Vref to +Vrefto within amaximum error of . As a result of the sampled-data oper-

ation of the stage, only end values count at the end of sample clock

periods. Hence, only DC gain variations around count,

since the differential OTA input always settles back to around 0V

as the output end value is reached. The OTA DC gain has an effec-

tively even characteristic and the DC gain doesnt vary much

around whether the outputs end up at 0V or at .

The stage transfer, including OTA gain error , is

, (13)

. (14)

In general, the DC gain requirement for stage i is given by

. (15)

To take an example, say the SC ADC stage of Fig. 1 is

designed as the first stage in a 12-bit pipeline ADC. The feedback

factor is . With nominally, , so

that the amplifier DC gain is required to be !

An important observation with this kind of gain error is that

there is always an exact mapping of the zero crossings irrespec-tive of DC gain error, be it linear or non-linear, i.e.

.

IV. LIMITATIONSON DYNAMIC ACCURACY

A. Linear and Non-linear Settling Constraints

The stage amplifier slews when the step voltage at the ampli-

fier differential input goes beyond the maximum linear input

range of which corresponds to it delivering its maximum

currentIto the load. The dynamic settling error caused by

the amplifier not settling out in sample period Tis

(16)

. (17)

Note is that proportion ofVstep which the amplifier

input sees through capacitor division before it starts to react. This

error (16) must be no larger than the required stage dynamic set-

tling error, . The effect of combined finite set-

tling time and finite slew rate is shown in Fig. 6. The limited

settling time produces a similar effect to limited DC gain in the

sense that end values are not achieved within a sampling clock

cD

1

1

3 2N iC

s - -D

Fi . 4 Effects of sta e 1 ca mismatch errors on ADC transfers

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

(a) Stage 1 transfer with positive c (c) Stage 1 transfer with negative c

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

(b) ADC transfer with stage 1 positive c (d) ADC transfer with stage 1 negative c

allwide

code

s

missingcodes

cD

{ } { }0 0in ref ref out ref ref V V , , V V V , , V - + - +

4refV

( )22 N i- - +

0inVD =

0inVD = refV

Fig. 5 Effects of stage 2 cap mismatch errors on ADC transfers

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

(a) After stage 2 with positive c in stage 2 (c) After stage 2 with negative c in stage 2

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

(b) ADC transfer with stage 2 positivec (d) ADC transfer with stage 2 negative c

missing codes atstage 1 transitions

0Ae

( ) ( )0

2 1i iout in i ref A

V V D V e= - +

0 0

1wherefb

A A be -

210 2

fb

N iAb

- +>

1

1 2

C fb C C b += 1 2C C= 12fbb =

( )0 dB 84dBA >

{ }4 40 0ref ref V VinV , , - +

2 onVsettlee

2

2 2

,

,

on

on on

step

Vnstep

settleV Vn

stepV

e V

e V

g

g g

e-

-

= >

( )2here and 1stepslew onVT t

slew Vn t

g

tt

-

= = -

Vstep

( )22

N i

settlee- - +

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interval. This is a linear effect though, unlike limited slew rate

which is input level dependent. This is clear from Fig. 6, where

large input levels up to cause a tapering off effect leading

to poor INL and harmonic distortion. Note again that the zero

crossings are correctly mapped despite the non-linear distortion.

B. Thermal Noise

The output noise power produced by a single ADC stage,

such as Fig. 1, has 3 constituents:

, (18)

with the amplifier (OTA) noise sampled only in the write

phase and the noise produced by the switches in

both the read and write phases. The thermal noise power of the

OTA, referred to the output, is given by

, (19)

where is the noise power spectral density of a differ-

ential pair and is the noise excess factor depending on OTA

architecture used. The amplifier input noise power is multiplied

by , which is the noise power gain from stage input

to output. For an essentially first order amplifier settling

response, the amplifier noise bandwidth is

, (20)

with the linear settling time constant and the total

effective load capacitance. Hence, the amplifier noise power for-

mula can be reduced to

. (21)

For the SC ADC stage, the switch noise contributions for the read

and write phases can be calculated as:

. (22)

The factor 2 in (22) is for the differential case and

is the bandwidth reduction factor in the write phase Since noise

in the read phase is pre-sampled, it is not affected by the OTA band-

width. Generally, and withC1=C2, the ADC stage

output noise power for full Nyquist operation becomes:

. (23)

The equivalent input noise power for each stage is obtained by

dividing the stage output noise power by the signal gain up to that

stage. For similar stages, the power gain factor per stage is just

, and the total equivalent noise calculated back to the input is

.(24)

Substituting (23) into (24), the total input-referred pipeline ADC

noise power ends up as

. (25)

To ensure that the totalSNR is degraded by just 1.76 dB, the ther-

mal noise power is specified with respect to the quantization

noise power by . Hence,

. (26)

The minimum value ofC, based on noise considerations, can

be found for the SC MDAC pipeline stage of Fig. 1. Assuming

parasitic capacitance at the amplifier input is small compared

toC, then , which with ,

gives . is typically in the range of 1 (single-

stage OTA) to 2 (dual-stage OTA) - is chosen here.

The minimum value ofCis now defined by:

. (27)

For a 12-bit differential application with 1V signal range and full

Nyquist operation, . Note the importance of maximiz-

ing signal range for the sake of minimizing signal capacitance, sothat if the signal range is doubled to 2V, the capacitance is reduced

by a factor of 4 (C=3/4pF) for the same 12-bit performance.

III. CONCLUSIONS

A lumped error model was developed in this paper to account

for static and dynamic errors due to hardware imperfections in

fabricated pipelined ADCs. Errors arising, for instance, due to

imperfect capacitor matching, non-linear settling behavior and

noise were analyzed. The effects of various expected error

sources on the ADC transfer characteristics were described. It

was emphasized that familiarity with the effects specific errors

have on the ADC charactersictics can be a useful aid for debug-

ging hardware errors after ADC fabrication.

REFERENCES

[1] S. Lewis, Optimizing the stage resolution in pipelined, multi-stage,

analog-to-digital converters for video-rate applications, IEEE

Trans. Circuits Syst. II, vol. 39, Aug. 1992.

[2] P. Quinn, M. Pribytko, A. van Roermund, Calibration-Free High-

Resolution Low-Power Algorithmic and Pipelined AD Conversion,

in Analog Circuit Design, Kluwer Academic Publishers, ISBN 1-

4020-2786-9 (HB), 2004, pp.327-349.

[3] Thomas B. Cho and Paul R. Gray, A 10 b, 20 Msample/s, 35mW

Pipeline A/D Converter, IEEE J. Solid-State Circuits, vol. 30, no.

3, pp. 166-172, Mar, 1995.

[4] J. Goes, J. Vital, and J. Franca, Systematic design for optimization

of high-speed self-calibrated pipelined A/D converters, IEEE

Trans. Circuits Syst. II, vol. 45, Dec. 1998.

refV

-0.5-0.75-1 -0.25 0 0 .25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

(a) Stage 1 transfer with slewing in 1st stage (c) After stage 2 with slewing in 2nd stage

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

-0.5-0.75-1 -0.25 0 0.25 0.5 0.75 1

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

Vin Vref

Vout

Vref

(b) ADC transfer with slewing error in 1st stage (d) ADC transfer with slewing error in 2nd stage

Fig. 6 Effects of non-linear settling errors on ADC transfers

2 2 2 2

stage OTA C C read write N N N N s s s s = + +

2

ampNs

2 2,

C Cread writeN Ns s

( ) 22 16 1 13 1OTA OTA OTAm fb N e N gkT N B bs = + 16 13 mg

kT

OTAeN

2 21 fbG b=

14 4

fb m

OTA OTA Leff

g

N CB

b

t

=

OTA

tLeff

C

( )2 43 1OTA OTA fb LeffkT

N eCN

bs = +

( )21 2 1 2

22 22 andNOTA

C C Nread writefb swit

BkT kT kT N NC C B C C b

s s

+= = +

OTA switN NB B

OTA swit

N NB B

( )22 1 43 1stage OTALefffbkT kT

N fb eC CN

bs b + +

21 fbb

( )2

2

2 2 2 2 4 2

11

fb

tot stage stagefb

N N fb fb fb N b

bs s b b b s

-= + + +

( )22 1 431 1tot OTALefffbkT kT

N fb eC CN

bs b

- + +

2sD2 21

2totNs sD<

( )2

2 2

1 4 13 241 2

1NOTALefffb

kT kT FS fb eC C

Nb

b-

+ + <

1 2 2 L fbeff

C C C C b= + + 1 2C C C= =52Leff

C C= OTAe

N

2OTAe

N =

2

2

245N

FSC kT>

3 1pFC .>

1959


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