02 rn77262en10gla0 rn4.0 upgrade for rnc450 ppt

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RN4.0 Upgrade for RNC450

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eager

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The SF10E operation is controlled by PPC7 HW block. The block utilises PowerQUICCII communication processor MPC8280 version HiP7. This unit is backward compatible with SF10.

The unit has 10 Gbit/s nonblocking ATM cell switching capacity and provides the following interfaces:

8 hi-speed ports with 1.65 Gbit/s of usable bandwidth each. It is connected to all MX1G6 units and other hi-speed units via optical interface in the front panel. To implement port redundancy, it will require two of these ports.

Redundant HMS interface connected to HMS Slave node type B. It supports maximum speed of 1 Mbit/s.

1 x 10/100Base-T for hardware debugging purpose

UTOPIA level 2 redundant multiplexer port interfaces for ATM based DMX messaging

RS232 serial interface with RJ45 connector for HW debugging and service terminal interface.

Activity signals, _ACT_2N and _ACT_EXT, to interchange activity information between redundant units.

Synchronisation signal, FSYNC_2N and FSYNC_EXT, with 8 kbit/s of speed.

19.44 MHz system clock.

Unit power -48 V and HMS power +5V

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The NP2GE-B operation is controlled by PQ3CC HW block. The block utilises PowerQUICCIII communication processor MPC8568.

The unit has 2 x Gigabyte Ethernet interfaces for external connection. At the same time, it supports approximately 2.5 Gbit/s multiprotocols traffic.

This unit provides the following interfaces:

2 x 1000Base-T Ethernet with RJ45 connector.

2 x 1000Base-Lx Ethernet with LC connector. The connector is integrated to transceiver in Small Form Plugable (SFP) format. This transceiver unit transmits Class 1 laser. It can accommodate SMF or MMF (in short operation distance)

RS232 serial interfaces with RJ45 connector for HW debugging and service terminal interface.

Redundant hi-speed Switch Fabric port connected to SF20H unit (require BISFC)

19.44 MHz synchronisation and timing signals


Unit power -48V and HMS power +5V

2 x 10/100Base-T for Ethernet based control messaging (future implementation)

Duplicated 10/100Base-T for DCN connection toward SWU (ESA24 card)

Redundant signals, L1_alarm and L2_alarm, for Ethernet link logic alarm

Redundant signals, PIU_OK and PAIR_OK, for interworking of redundant NP2GE-B pair.

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GTPU and A2SU are exist as long as NIS1(P) is used as network interface

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CDSP-DH contains 4 DMPGs. The operation of each DMPG is controlled by PPC7 HW block which utilises PowerQUICCII communication processor MPC8280 version HiP7.

The DMPG has 2 Himalaya DSPs, which has 1200 MHz core speed and 256 MB external DDR2 memory each.

CDSP-DH provides the following external interfaces:

Four 10/100 Base-T Ethernet connected to each DMPG. They are used during R&D phase to debugging.

Four RS232 serial interfaces with RJ45 connector for HW debugging and service terminal interface, connected to each DMPG.

Multiplexer port interface connected to working and spare multiplexer units.

Two 19.44MHz timing and synchronisation signals, REF Clock A and REF Clock B, consecutively for active and redundant source.



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DSP pool reservation on CDSP-C is example only. The actual share depends on HW configuration.

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All connection to/from BISFx unit require intermediate cable with SFP connectors, CSB.

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The SF20H operation is controlled by PPC7 HW block. The block utilises PowerQUICCkII communication processor MPC8280 version HiP7.

The unit has 20 Gbit/s non-blocking ATM cell switching capacity and provides the following interfaces:

32 hi-speed ports with 1.65 Gbit/s of usable bandwidth each. It is connected to all MX1G6 units and other hi-speed units via optical cables (requires BISFA and BISFD). Port redundancy is implemented using two of these ports.



Redundant multiplexer port interfaces for ATM based DMX messaging


Activity signals, _ACT_2N and _ACT_EXT, to exchange activity information between redundant units.

Synchronisation signal, FSYNC_2N and FSYNC_EXT, with 8 kbit/s of speed.



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The MX1G6-A operation is controlled by PQ3CC HW block. The block utilises PowerQUICCIII communication processor MPC8560.

The unit has 1.65 Gbit/s ATM cell multiplexing/demultiplexing capacity to/from SF20H unit. It also provides the following interfaces:

20 multiplexer ports with 160 Mbit/s of speed each. It connects all tributary units to/from SF20H via optical cables (requires BISFB).


2 x 10/100Base-T for Ethernet based control messaging (future implementation). One of these interface also connected to front panel for R&D purpose.

Redundant hi-speed Switch Fabric port connected to working and spare SFU.


Redundancy signals, SWITCHOVER_A and SWITCHOVER_B, to exchange information between redundant MXU.



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The NP8S1-B operation is controlled by PQ3CC HW block. The block utilises PowerQUICCIII communication processor MPC8567.

The unit has 8 x STM-1/OC-3 interfaces for external connection. At the same time, it supports approximately 1.2 Gbit/s AAL2 connectivity (8*155.52 Mbit/s) for any AAL2 based traffic.

This unit provides the following interfaces:

8 x optical interfaces with LC connector. The connector is integrated to transceiver in Small Form Pluggable (SFP) format. This transceiver unit transmits Class 1 laser.

RS232 serial interfaces with RJ45 connector for HW debugging and service terminal interface.

Redundancy signals, SWITCHOVER_A and SWITCHOVER_B, to exchange information between redundant NPS1.

Redundant hi-speed Switch Fabric port connected to SF20H unit (require BISFC)


Duplicated 10/100Base-T for DCN connection toward SWU (ESA24 card)


Unit power -48V and HMS power +5V

19.44MHz reference clock output. The reference clock is extracted from interface to be forwarded to TSS3 plugin unit.

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02 rn77262en10gla0 rn4.0 upgrade for rnc450 ppt

Documents

unit power

redundant units

transceiver unit

baset ethernet

sf20h unit

speed units

rj45 connector

maximum speed