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SemiconductorInternational

Triple Well Applications ProfitFrom MeV Implant Technology

When implementing MeV triple wells, the key considerations arephotoresist outgassing and energy and dose capability.

John Ogawa Borland, Genus Inc., Ion Technology Division, Newburyport, Mass.

The application of triplewell structures pro-

vides important advan-tages to several differentCMOS devices. Theyinclude memory (DRAM,flash and SRAM) andembedded CMOS tech-nologies with memory andlogic on the same chip.

Because of marketforces, more and morecompanies are looking tonon-DRAM products forthe future.' Of the estab-lished flash manufactur-ers, most have embracedsome type of triple well

technology, and 75% of the 64Mb DRAM generationdevices use triple well structures," SRAM on p-typesubstrates is also moving to triple well as reported,"as are embedded memory and logic devices.'

To take full advantage of the leverage that triplewells provide, high-energy (MeV) ion implantation ispreferred over other approaches. Classic diffusedwell technologies demand prohibitively long thermalcycles at high temperatures (c- 1150°C). Retrogradewells engineered through MeV scale implants requirea fraction of the thermal budget «950°C), providegreater packing densities, are less expensive tomanufacture, outperform diffused well structuresand promote productivity improvements viachained implants.

AtA Glance ...Three strategies presentlyexist for fabricatingtriple well structures:diffused, hybrid and MeV.The decision to migrate aprocess flow to the mostadvanced of these threeoptions should be based onthe benefits associated.with the key fab drivers ofyield, cost, cycle time andthroughput. MeVtriplewells offer attractivebenefits in all these areas.

Historyof triplewellstructuresThe early work in triple wells was presented in1989by Fujii, et al., of Toshiba," The enabling char-acteristic ofthe 16Mb DRAM fabricated with thisprocess was the added degree of freedom associat-ed with independent optimization of n-well and p-well biases. This early work was carried out on ann substrate with no epi layers. The "third" well inthe processing scenario was a relatively shallow n-well implanted into a much deeper p-well. The tran-sistors fabricated in these wells were the PMOS ofthe CMOS pairs used in the peripheral circuits.

www.semiconductor.net

Continued development of this process was laterapplied to SRAMs where p substrates were used.SRAMs are particularly sensitive to soft error rate.Triple wells provided SRAMs with a lOx to 100ximprovement in SER.

Currently, triple well technology has applications -within every type of CMOS circuit with the exceptionof pure logic. For flash memory, triple wells eliminatethe need for an additional power supply and reducechip size by 30%.4 In DRAM and SRAM

High-energy implantation for triple wells isenabled through modern accelerationtechnology. Pictured here is aportion of the Genus DCTandetron accelerator.

Triple Well Applications Profit from MeV Implant Technology

Retrograde Triple Well Structure

8.00Distance (urn)

1. A retrograde (subsu-rface peak concentration) deep n-well is formed using anMeV ion implant. Since no diffusion is required to form the well, the process hasa negligible thermal budget.

0.00 4.00 12.00

circuits, the bulk of the transistors arein the memory array. However, theperipheral control circuitry requiresmultiple transistor types, which triplewells enable. Embedded CMOS cir-cuits will have varying ratios of logicand memory on the same chip andrequire multiple transistor types aswell. Straight logic is based solely onthe simple CMOS pair, and thereforethere is no overriding need to go totriple well technology here. There areadditional performance advantagesthat triple wells provide, which will bereviewed in greater detail later in thispaper.

Triple well processingThere are three methods of formingtriple wells: diffused triple well, hybridtriple well and MeV (retrograde) triplewell. The process technology employedby anyone device manufacturer is.based on that company's cost drivers,performance drivers and ultimately,their migration strategy.

Diffused triple wells have beenreported for memory applications byToshiba (DRAM, SRAM, flash andmerged memory/logic) and AMD

_(flash).' They are formed by standardlow-energy ion implantation at ener-gies of <250 ke V, followed by high tem-perature (1100-1200°C) diffusion fur-nace drive-in for 4-24 hrs. The longerdrive-in times are required in order toform a 6 urn deep n-well. The high-tem-perature anneal also serves as adenudation step. This deep junctiondepth is required to prevent depletionregion punch through from the isolatedp-well to the substrate. This break-down voltage- can be >20 V, depending

68/SEMICONDUCTOR INTERNATIONAL APRIL 1998

on the application and the maximumvoltages present in the circuit.

Hybrid triple wells have beenreported by LG and are formed by thecombination of both sub-MeV high-energy ion implantation and moderatethermal diffusion/anneals at 1000-1100°C for 1-4 hrs." This can be done inconjunction with the LOCOS isolationprocess to achieve both well drive-inand denudation steps.

True MeV retrograde triple wellshave been reported by IBM,7 Mit-subishi" and LG6 for DRAMs, ST9 forflash and Micron" for SRAM and areformed by MeV ion implantation in the2-3 MeV energy range. Typically, thisprocess forms a 2.5-3.5 urn deep buried

n-well with a retrograde (subsurfacepeak concentration) dopant profile. Inorder to pattern and block this deepimplant, thick photoresist is requiredin the 3.5-5.5 urn range. Thermal diffu-sion treatment is not required, anddopant activation and implant damagerecovery can be achieved by the subse-quent thermal processing, such as thegate oxidation step. However, sincethere is no high-temperature thermalcycle, one must engineer a high-tem-perature denuding step into theprocess or use pre-denuded wafers toensure that there are no near surfacebulk defects such as oxygen precipi-tates. If LOCOS isolation is utilized,then the LOCOS oxidation process canbe modified to accomplish the requireddenudation. If shallow-trench isolationis used, then a separate denudationstep will be required.

MeV retrograde triple well technol-ogy holds several advantages over thealternatives. There is a negligible ther-mal budget, which is important for 200mm and especially 300 mm wafer pro-cessing. Process simplification andreduced manufacturing costs can berealized. Finally, improved device per- _formance results from retrogradedopant profile of the well structures.However, substrate defect engineer-ing must be optimized to ensure waferdenuded zone formation and gettering.High-temperature denudation or lowoxygen content wafers are recom-mended for near surface defect controlto ensure a high-quality gate oxide and

Embedded Memory with Logic MigrationTo triple well structure

1------- 0.5/.lm---------111-----------0.35/.lm I

I 0.25/.lm----

2. A triple well MeV implant strategy enables the elimination of up to threemasking steps, which equates to 24 processing steps and up to $125 in savingsper 200 mm wafer.



BILL! Triple Well Structure

Eo:::l..o;-Nos::::nI'liiis 0 -fII"' __ -,

q,...

8.00Distance (urn)

3. The BILLI triple well structure provides more isolation without adding anothermasking step.

0.00 4.00 12.00

low junction leakage." the substrate and allow the optimiza-tion of bias potentials for both n- and p-wells. When used to fabricate flashmemory, power consumption isreduced (dual power supply voltagesare eliminated allowing single low volt-age power supply) and packing densityis increased by eliminating the PMOStransfer gate in the row decoder cir-cuit." DRAMs benefit through n-welland p-well bias optimization, back gatebias avoidance and minimization ofjunction capacitance," Through triplewells, logic devices can utilize embed-ded flash, SRAM and DRAM and willbecome robust against alpha particleinduced soft errors.

Minimization of thermal budget is akey element of MeV triple wells andhas a direct impact on yield issues. Lowto zero thermal budget processing iscritical to minimize bulk wafer or epi-wafer thermal-induced stresses. Ther-mal processing can lead to waferwarpage, slip and ultimately, waferbreakage. Wafer bow and warp have

Impetus for change to MeVAny change in device fab processing,represented by either a new processflow or tool set, has to be justified on acombined basis of the four fundamentalfab drivers:• Yield - raw performance per die ortotal good die per wafer. Improvedyield has a direct impact on cost-of-ownership and productivity.• Cost - the cost to manufacture adevice directly affects the margins anda company's profitability.• Cycle time - the total amount oftime required for processing a particu-lar process or process segment.Reduced cycle time equates toimproved productivity and more cyclesof learning per unit time.• Throughput - the measure of theraw number of wafers that passthrough a particular point in theprocess. High throughput minimizesthe potential for constraints andincreases productivity.

Retrograde triple well pro-cessing allows the formation ofa buried n-well beneath select-ed n- and p-wells without sur-face compensation of dopants,which can lead to improveddevice performance in theareas of latch-up, soft errorrate and alpha particle immu-

1.00 x 10·05'-- ~ _'nity (Fig. 1). Additionally, 0.00improved device packing den-sity results since no lateraldopant diffusion occurs. 4. Outgassed photoresist from high-energy implanting

Triple well structures elec- increases chamber pressure and causes dose errors.trically isolate the wells from

Maximum Chamber Pressure vs.Dose Shift for 1 MeV Implant

1.00 x 10.04

1.25 2.50 4.00Dose shift (%)

7.00

70/SEMICONDUCTOR INTERNATIONAL APRIL 1998 www.semiconductor.net

been shown to generate downstreamproblems with photolithography CMPand backgrind.!' Wafer shape willaffect flatness in certain situationsnegating tight raw wafer thicknessspecifications necessary for 0.25 urn(250 nm) processing and beyond. Thisis a problem that will become exacer-bated with the move to 300 mm sub-strates. Not only will 300 mm wafersbe more sensitive mechanically tothermal-induced stresses, but thealmost certain parallel move towardfiner linewidths to the 0.18 u.m(180 nm) node will make wafer shapecontrol paramount.

Cost and cycle timeUp to three masking steps can be elim-inated, which equates to 24 processingsteps and up to $125 in savings per200 mm wafer that can be realized (Fig.2). Elimination of 52 process hours, fivefurnace anneal steps, three maskinglevels and the associated clean andmetrology steps add up to significantcapital equipment cost savings andspace, reducing overall manufacturingcosts by up to 12%.

With continued pressure to reducemanufacturing costs and process com-plexity, one approach is through themigration to Buried Implanter Layerfor Lateral Isolation (BILL!) triplewell per Figure 1 and as reported byLG.6 In comparing hybrid, MeV andBILLI triple well, LG reported nodegradation in breakdown voltage. Infact, an improvement in short channeleffects was observed. The BILLItriple well eliminates the p-well masktherefore one mask level; however, forsome triple well applications it couldreduce two mask levels by eitherchanging substrate type or using phos-phorus rather than boron for creationof the BILLI layer. 12 A cross section ofthe modeled BILLI triple well struc-

ture is illustrated in Figure 3.

ThroughputThe implementation of MeVtechnology can provide tre-mendous leverage in the rawthroughput interpreted as thenumber of implants per hour.Through the use of chainedimplants, several implantsteps can be performed inseries without unloading thewafers from the processchamber.

The use of photoresist as animplant mask has been in use

Maximum• pressure


for years. However, the applicationof photoresist for high-energy im-plant use has several unique issuesassociated with it.

In order to mask higher energyimplants, it is necessary to usemuch thicker resist for effective-ness. For MeV implants, which mayreach as high as 3 MeV for sometriple well applications, the pro-jected range into bare silicon willbe 2-4 urn. In order to effectivelymask this implant, a resist thick-ness of 3.5-5.5 urn will be required.

When modeling resist thicknessfor implant, typically the composi-tion of the material is taken intoaccount to predetermine the densi-ty. However, it is not unusual forthe practical density to be greaterthan the modeled density becauseof pre-implant softbake. Therefore, itis required that resist density bedetermined empirically. The differencein density between modeled andempirical values for a standard resistmight be as much as 30%. Once theactual density value has been deter-mined, a range table can be derived forthe resist which will aid in determiningthe proper resist thickness.

The thickness of the resist in concertwith the nature of high-energy beamscreates a problem with outgassedmaterial that is not a concern for lowerenergy implants. There is a directlyproportional relationship to both beamcurrent and ion energy to outgassedmaterial. Since the phenomena is dueto atomic bond breaking of the resistby the ion beam, the wafer tempera-ture is an issue only to minimize car-bonization and to facilitate ashing.

Outgassed material from photore-sist into an ion implanter's processchamber will increase the partialpressures of hydrogen, nitrogen,water, hydrocarbons and other mate-rials quite dramatically. If, for exam-ple, the total pressure increaseapproaches 3X 10-5 Torr (Fig. 4) for 1MeV im-plants, then dose errors willsurface. Random charge exchangeresulting from the partial pressureincreases will cause unwanted ioniza-tion and neutralization ofthe ion beambefore it reaches the dosimetry Fara-day. This will inadvertently confusethe dosimetry system creating thedose errors. To minimize this, it isgenerally accepted that the implanttool must be designed to keep thepressure below the critical level. Thebest way to do this is via a large vol-

72/SEMICONDUCTOR INTERNATIONAL APRIL 1998

MeV Triple Well BVcbo Control24r---------------~232221

~ 20~ 19 1="'.~~Eii£ •••

in 181~=-="""'"171615L-----~~----~

2.50

.n-well dose1x1 013

• n-well dose2x1013

2.80Implant energy

3.00

5. The best p-well isolation, as measured byp-well to p-substrate breakdown, BVcbo, occurswhen the deep n-well implant is done with aminimum dose at a maximum energy.

ume process chamber and direct cry-opumping.

Energy and dose requirementsTypical modern triple well processesare all implanted. The deep n-well thatforms the added isolation of the thirdwell can require as much as 3 MeV ofenergy at a dose of 1X 1013 to 5X 1013•

Additionally, the Boron p-well, whichis implanted into the deep n-well, willrequire up to 1 MeVat a dose of 1x 1013

to 5x1013• The key parameter for con-trol is the breakdown voltage from theisolated p-well to the p substrate. Thedeep n-well energy and dose can bemanipulated to achieve the desiredrequirement. The highest breakdownvoltage is achieved with the highestenergy and the lowest dose (Fig. 5).

SummaryTriple well structures have been inuse for several years now. Their bene-fits are extensive and well document-ed. There currently exist three strate-gies for fabrication of triple wellstructures: diffused, hybrid and MeV.The decision to migrate a process flowto the most advanced of these threeoptions should be based on the bene-fits associated to the key fab driversof yield, cost, cycle time and through-put. As illustrated, MeV triple wellsoffer attractive benefits to all thesekey drivers.

When implementing MeV triplewells, the key considerations are pho-toresist outgassing and energy anddose capability. The Genus Kestrel750 has been designed to offer the bestvalue for triple well and BILLI pro-cessing through enhanced outgassing


control, higher energy range andsuperior chained implant capabili-ty. D

References1. Economic Report, Korea, vol.12, no. 7, July 1997.2. Nikkei Micro Devices, specialfeature, Nov. 1993.3. Jeff Honeycutt, Micron Semi-conductor Inc., presentation at theGenus 2nd Annual MeV ImplantSeminar, July 1994.4. Seiichi Mori, Toshiba Corp., pre-sentation at the Genus 1st AnnualMeV Implant Seminar, July 1993.5. Fujii, et aI., IEEE Journal of SolidState Circuits, vol. 24, no. 5, Oct. 1989.6. J.K. Kim, LG Semicon, presen-tation at the Genus 5th Annual

MeV Implant seminar, July 1997.7. S. Dash, et a!., IBM Corp., 1991VLSI Symposium, June 1991.8. K. Tsukamoto, Mitsubishi, ElectricCorp., presentation at the Genus 1stannual MeV implant seminar, July1993.9. Roberto Bez, ST, presentation at theGenus 3rd annual MeV implant semi-nar, July 1995.10. J. Borland, Genus Inc., SemiconSouthwest 96 technical digest on"Defect Engineering in SubmicronProcess Technologies," Oct. 1996.11. J. Kawski, et a!., "Cumulative ThinFilm Stress and its Effect on PostBackgrind Wafer Shape," Semicon Sin-gapore Technical Symposium, 199212. J. Borland, Genus Inc., presenta-tion at the Genus 2nd Annual MeVimplant seminar, July 1994.

John O. Borland isvice president ofstrategic technologyat Genus Inc. He hasbachelor's and mas-ter's degrees inmaterials sciencefrom the Massachu-setts Institute ofTechnology.

Phone: (978) 463-1500Fax: (978) 462-0210

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