03. data processing instruction (2)

7/22/2019 03. Data Processing Instruction (2)

1/35

Embedded System Design Center

ARM7TDMI Microprocessor

Data Processing I nstructions

Sai Kumar Devulapalli


2/35

2 of 35

Objectives

Detailed understanding of ARM Data processing instructions

Understanding the instruction encoding formats

Understanding the general format with which data processinginstructions can be conditionally executed and to set the statusflags

Use of immediate operand in the data processing operations

Understand the use of shifter operations for second operand

Understand the operation of multiplication instructions


3/35

3 of 35

Data processing Instructions

Largest family of ARM instructions, all sharing the sameinstruction format.

Contains:

Arithmetic operations

Comparisons (no results - just set condition codes)

Logical operations

Data movement between registers

Remember, this is a load / store architecture

These instruction only work on registers, NOT memory.

They each perform a specific operation on one or twooperands.

First operand always a register - Rn

Second operand sent to the ALU via barrel shifter.

We will examine the barrel shifter shortly.


4/354 of 35

Arithmetic AND logical Instructions: General Format

Opcode{Cond}{S} Rd,Rn,Operand 2

{Cond}- Conditional Execution of instruction

E.g. GT=GREATER THAN,LT = LESS THAN

{S}- Set the bits in status register after execution.

{Operand 2}- various form of the instruction

immediate/register/shifting

you can easily check all the combinations in the quick

references of ARM.


5/355 of 35

Instruction format

31 28 27 26 25 24 21 20 19 16 15 12 11 0

Cond 0 0 # opcode S Rn Rd operand 2

Opcode: Arithmetic / Logic Function

S : Set condition code

Rn : First operand (ARM Register)

Rd : Destination operand (ARM Register)


6/356 of 35

32 bit immediate

If # (I) = 1 then operand 2 field will be

#rot 8-bit immediate

11 8 7 0

The actual immediate value is formed by rotating right the 8-bit immediate value by the even positions (#rot * 2) in a 32bit word.

If #rot = 0 (when immediate value is less than 0xFF8 bit)

then carry out from the shifter will be indicated in C flag.

Because of this all 32 bit immediate are not legitimate. Onlythose which can be formed.


7/357 of 35

Register operand

# (I) = 0 indicates that the second operand is specified in registerwhich can also be shifted.

#shift Sh 0 Rm

11 7 6 5 4 3 0

# Shift : Immediate shift length

Rs : Register shift length

Sh : Shift type

Rm : Register used to hold second operand.

Rs 0 Sh 1 Rm

11 8 7 6 5 4 3 0

Ex:

ADD RO, R1, R2, LSL #3

Ex:

ADD RO, R1, R2, LSL R3


8/358 of 35

Shift operations

Guided by Sh field in the format

Sh = 00 Logical Shift Left : LSL Operation

Sh = 01 Logical Shift Right : LSR Operation

Sh = 10 Arithmetic Shift Right : ASR Operation

Sh = 11 Rotate Right : ROR Operation

With Sh = 11 and #shift = 00000 (similar to ROR #0) is usedfor RRX operation.


9/359 of 35

Immediate value

8 bit number

Can be rotated right throughan even number ofpositions.

Assembler will calculaterotate for you fromconstant.

Register, optionally with shiftoperation applied.

Shift value can be either be:

5 bit unsigned integer

Specified in bottom byteof another register.

Operand1

Result

ALU

Barrel

Shifter

Operand2

Using the Barrel Shifter: The Second Operand


10/3510 of 35

Data Processing instructions

0000 AND

0001 EOR

0010 SUB

0011 RSB

0100 ADD

0101 ADC

0110 SBC

0111 RSC

1000 TST

1001 TEQ

1010 CMP

1011 CMN

1100 ORR

1101 MOV

1110 BIC

1111 MVN


11/35

11 of 35

Arithmetic Operations

Operations are:

ADD operand1 + operand2

ADC operand1 + operand2 + carry

SUB operand1 - operand2

SBC operand1 - operand2 + carry -1

RSB operand2 - operand1

RSC operand2 - operand1 + carry1

Syntax:

{}{S} Rd, Rn, Operand2

Examples

ADD r0, r1, r2

SUBGT r3, r3, #1

RSBLES r4, r5, #5


12/35


13/35

13 of 35

Comparisons

The only effect of the comparisons is to

UPDATE THE CONDITION FLAGS. Thus no need to setS bit.

Operations are:

CMP operand1 - operand2, but result not written CMN operand1 + operand2, but result not written

TST operand1 AND operand2, but result not written

TEQ operand1 EOR operand2, but result not written

Syntax: {} Rn, Operand2


14/35

14 of 35

Comparisons

Examples:

CMP r0, r1

CMP R1,Operand2 e.g. CMP R1,R2

[R1] - [R2]Set the N Z C V in CPSR register.

TSTEQ r2, #5

TST R1, Operand2 e.g. TST R1,R2

[R1] AND [R2]


15/35

15 of 35

Data Movement

Operations are:

MOV Rd, operand2

MVN Rd, (NOT) operand2

Note that these make no use of operand1.

Syntax: {}{S} Rd, Operand2

Examples:

MOV r0, r1

MVN r0, r1 MOVS r2, #10

MVNEQ r1, #0


16/35

16 of 35

Quiz

Start

Stopr0 = r1?

r0 > r1?

r0 = r0 - r1 r1 = r1 - r0

Yes

NoYes

No

* Convert the GCD algorithmgiven in this flowchart into

1)Normal assembler,where only branches can beconditional.

2) ARM assembler, where allinstructions are conditional,thus improving codedensity.

* The only instructions youneed are CMP, B and SUB.


17/35

17 of 35

Quiz - Sample Solutions

NormalAssembler

gcd cmp r0, r1 ;reached the end?

beq stop

blt less ;if r0 > r1

sub r0, r0, r1 ;subtract r1 from r0

bal gcd

less sub r1, r1, r0 ;subtract r0 from r1bal gcd

stop

ARM Conditional Assembler

gcd cmp r0, r1 ;if r0 > r1

subgt r0, r0, r1 ;subtract r1 from r0

sublt r1, r1, r0 ;else subtract r0 from r1

bne gcd ;reached the end?


18/35

18 of 35

The Barrel Shifter

The ARM doesnt have actual shift instructions.

Instead it has a barrel shifter which provides a mechanism to

carry out shifts as part of other instructions.

So what operations does the barrel shifter support?


19/35

19 of 35

Shifts left by the specified amount (multiplies by powers oftwo) e.g.

LSL #5 = multiply by 32

Barrel Shifter - Left Shift

Logical Shift Left (LSL)

DestinationCF 0


20/35

20 of 35

Logical Shift Right

Shifts right by thespecified amount (divides

by powers of two) e.g.

LSR #5 = divide by 32

Arithmetic Shift Right

Shifts right (divides bypowers of two) and

preserves the sign bit, for2's complementoperations. e.g.

ASR #5 = divide by 32

Barrel Shifter - Right Shifts

Destination CF

Destination CF

Logical Shift Right

Arithmetic Shift Right

...0

Sign bit shifted in


21/35

21 of 35

Barrel Shifter - Rotations

Rotate Right (ROR)

Similar to an ASR but the bitswrap around as they leave theLSB and appear as the MSB.

e.g. ROR #5

Note the last bit rotated is alsoused as the Carry Out.

Rotate Right Extended (RRX)

This operation uses the CPSR Cflag as a 33rd bit.

Rotates right by 1 bit. Encodedas ROR #0.

DestinationCF

Rotate Right

Destination CF

Rotate Right through Carry


22/35

22 of 35

Second Operand: Shifted Register

The amount by which the register is to be shifted iscontained in either:

the immediate 5-bit field in the instruction

NO OVERHEAD

Shift is done for free - executes in single cycle.

the bottom byte of a register (not PC)

Then takes extra cycle to execute

ARM doesnt have enough read ports to read 3 registersat once.

Then same as on other processors where shift isseparate instruction.

If no shift is specified then a default shift is applied: LSL #0

i.e. barrel shifter has no effect on value in register.


23/35

23 of 35

Using a multiplication instruction to multiply by a constantmeans first loading the constant into a register and then waitinga number of internal cycles for the instruction to complete.

A more optimum solution can often be found by using somecombination of MOVs, ADDs, SUBs and RSBs with shifts.

Multiplications by a constant equal to a ((power of 2) 1)can be done in one cycle.

Example: r0 = r1 * 5Example: r0 = r1 + (r1 * 4)

ADD r0, r1, r1, LSL #2

Example: r2 = r3 * 105Example: r2 = r3 * 15 * 7Example: r2 = r3 * (16 - 1) * (8 - 1)

RSB r2, r3, r3, LSL #4 ; r2 = r3 * 15RSB r2, r2, r2, LSL #3 ; r2 = r2 * 7

Second Operand:Using a Shifted Register

Loading full 32 bit constants


24/35

24 of 35

Loading full 32 bit constants

Although theMOV/MVN mechanism will load a large range ofconstants into a register, sometimes this mechanism will notgenerate the required constant.

Therefore, the assembler also provides a method which will loadANY 32 bit constant:

LDR rd,=numeric constant

If the constant can be constructed using either aMOVorMVNthen

this will be the instruction actually generated. Otherwise, the assembler will produce anLDRinstruction with a

PC-relative address to read the constant from a literal pool.

LDR r0,=0x42 ; generates MOV r0,#0x42

LDR r0,=0x55555555 ; generateLDR r0,[pc, offset to lit pool]

As this mechanism will always generate the best instruction for agiven case, it is the recommended way of loading constants.


25/35

25 of 35

Multiplication Instructions

The Basic ARM provides two multiplication instructions.

Multiply

MUL{}{S} Rd, Rm, Rs ; Rd = Rm * Rs

Multiply Accumulate - does addition for free

MLA{}{S} Rd, Rm, Rs, Rn ; Rd = (Rm * Rs) + Rn

Restrictions on use:

Rd and Rm cannot be the same register

Can be avoid by swapping Rm and Rs around. This works becausemultiplication is commutative.

Cannot use PC.

These will be picked up by the assembler if overlooked.

Operands can be considered signed or unsigned

Up to user to interpret correctly.


26/35

26 of 35

Instructions are

MULL which gives RdHi,RdLo:=Rm*Rs

MLAL which gives RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo

However the full 64 bit of the result now matter (lowerprecision multiply instructions simply throws top 32bits

away)

Need to specify whether operands are signed or unsigned

Warning : Unpredictable on non-M ARMs.

Syntax:

UMULL/UMLAL{cond} {S} RdLo, RdHi, Rm, Rs

SMULL/SMLAL{cond} {S} RdLo, RdHi, Rm, Rs

Multiply-Long and Multiply_Accumulate Long


27/35

27 of 35

Instruction Format

000 MUL Rd := (Rm * Rs)

001 MLA Rd := (Rm * Rs) + Rn

100 UMULL RdHi : RdLo := Rm * Rs

101 UMLAL RdHi : RdLo += Rm * Rs

110 SMULL RdHi : RdLo := Rm * Rs111 SMLAL RdHi : RdLo += Rm * Rs

31 28 27 24 23 21 20 19 16 15 12 11 8 7 4 3 0

Cond 0 0 0 0 mul S Rd/RdHi Rn/RdLo Rs 1 0 0 1 Rm

E l C i


28/35

28 of 35

Example: C assignments

C:

x = (a + b) - c; Assembler:

ADR r4,a ; get address for a

LDR r0,[r4] ; get value of a

ADR r4,b ; get address for b, reusing r4LDR r1,[r4] ; get value of b

ADD r3,r0,r1 ; compute a+b

ADR r4,c ; get address for c

LDR r2[r4] ; get value of cSUB r3,r3,r2 ; complete computation of x

ADR r4,x ; get address for x

STR r3[r4] ; store value of x

Example: C assignment


29/35

29 of 35


C:

y = a*(b+c);

Assembler:

ADR r4,b ; get address for b

LDR r0,[r4] ; get value of b

ADR r4,c ; get address for c

LDR r1,[r4] ; get value of c

ADD r2,r0,r1 ; compute partial result

ADR r4,a ; get address for a

LDR r0,[r4] ; get value of a

MUL r2,r2,r0 ; compute final value for y

ADR r4,y ; get address for y

STR r2,[r4] ; store y

l i


30/35

30 of 35


C:

z = (a


31/35

31 of 35

Example: FIR filter

C:

for (i=0, f=0; i


32/35

32 of 35

FIR filter, cont.d

ADR r3,c ; load r3 with base of c

ADR r5,x ; load r5 with base of x

; loop body

loop LDR r4,[r3,r8] ; get c[i]

LDR r6,[r5,r8] ; get x[i]MUL r4,r4,r6 ; compute c[i]*x[i]

ADD r2,r2,r4 ; add into running sum

ADD r8,r8,#4 ; add 1 word offset to array index

ADD r0,r0,#1 ; add 1 to iCMP r0,r1 ; exit?

BLT loop ; if i < N, continue


33/35

33 of 35

Barrel Shifter executing Fixed Point Arithmetic


34/35

34 of 35

Summary

All data processing operations work only on internal registers,immediate operands and NOT on memory.

Data processing instructions

ArithmeticADD, ADC, SUB, SBC, RSB, RSC

ComparisonCMP, CMN, TST, TEQ

LogicalORR, AND, EOR, BIC

Data MovementMOV, MVN

Shifter OperationsLSL, LSR, ASR, ROR, RRX

Multiplication InstructionsMUL, MLA, MULL, MLAL


35/35

35 of 35

Thank You, Any Questions ?

03. data processing instruction (2)

Documents