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The UNIVERSITY ofNORTH CAROLINA atCHAPEL HILL

RAM Basics

Anselmo Lastra

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TopicsVGA timing project

Deadline Thursday

Class time change

Semester project topics

RAMs

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ClassT

imePreference for keeping TTh

Unfortunately, no open time forall

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ProjectsSome have project already

Polygon pipelineStopping points: Gouraud, texturing, etc.

Ray caster/tracer

Similar possible milestonesCan share common parts

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Simple Hdw View of RAM

Some capacity 2k

k bits of address linesOften multiplexed

Maybeh

ave read line, clock, ch

ipselect

Have a write enable line

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ReadingSetup address lines

Activate enable, read/write line

Data available after specified amt of time

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Writing

Setup address lines

Setup data lines

Activate write line

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Static vs Dynamic RAMSRAM vs DRAM

DRAM stores charge in whats essentially

capacitorDisappears over short period of time

Must be refreshed (rewritten/recharged)

SRAM easier to use

FasterMore expensive per bit

Smaller sizes

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Stru

ctu

re of SRAMControl logic

One memory cell per bitCell consists of one or more transistors

Not really a latch made of logic

Logic equivalent

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Bit SliceCells connected to form1 bit position

Word Select gates one

latch from address linesNote it selects Readsalso

B (and B not) set byR/W, Data In andBitSelectFunny thing here whenyou write.What is it?

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Bit Slice can Become Modu

le

Basically bit sliceis a X1 memory

Next

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16 X 1 RAMNowshows

decoder

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Tri-StateHave three states: H, L, and Hi-Z

High impedance

Behaves like no output connection if inHi-Z state

Allows connecting multiple outputs

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Mu

ltiplexed with

Hi-Z

Normal behavior is bluearea

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Row/Colu

mnIf RAM gets large, there is a largedecoder

Also run into chip layout issues

Larger memories usually 2D ina matrix layout

Next Slide

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16 X 1 as 4 X 4 ArrayTwodecoders

Row

Column

Address just

brokenu

pNot visiblefrom outside

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Ch

ange to 4 X 2 RAMMinor changein logic

Also pinouts

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Realistic SizesImagine 256K memory as 32K X 8

One column layout would need

15-bit decoder with 32K outputs!

Can make a square layout with 9-bit row and 6-bit column decoders

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SRAM PerformanceCurrent ones have cycle times inlow nanoseconds (say 2.5ns)

Used as cache (typically offchipsecondary cache)

Sizes up to 8Mbit or so for fast

chips

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Using SRAM on Spartan IIRecall block SRAM available onchip

11 4Kb blocks

Configured in many ways (table)

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Using from VerilogInstantiate a block (here called R1)

RAMB4_S8_S8 R1 (.DOA (data_a),

.DOB (data_b),

.ADDRA (addr_a),

.ADDRB (addr_a),

.CLKA (clk),

.CLKB (clk),

.DIA (data_in),

.DIB (data_in),

.ENA (ena),

.ENB (enb),

.RSTA (rsta),

.RSTB (rstb),

.WEA (wea),

.WEB (web));

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Can InitializeHave to do it two ways, one forsimulator, another for hardware

//synthesis attribute INIT_00 of R1 is"08192A3B4C5... total of 256 bits (64 hexcharacters)..."

//synthesis attribute INIT_01 of R1 is"08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4C5D6E7F0

8192A3B4C5D6E7F

// Up to INIT_0F

Above is for hardware (nextsoftware)

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Look atT

est CodeMy RAM loading example fromundergrad class

http://www.cs.unc.edu/~lastra/comp190/Assignments/block_ram_C.txt

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Dynamic RAMCapacitor can hold charge

Transistor acts as gate

No charge is a 0

Can add charge to store a 1

Then open switch (disconnect)

Can read by closing switchExplanation next

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Prech

arge and Sense AmpsYoull see precharge time

B is precharged to V

Charge/no-charge on C willincrease or decrease voltage

Sense amps detect this

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DRAM Ch

aracteristicsDestructive ReadWhen cell read, charge removed

Must be restored after a read

RefreshAlso, theres steady leakage

Charge must be restored periodically

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DRAM Logical Diagram

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DRAMW

riteT

iming

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DRAM Refresh

Many strategies w/ logic on chip

Here a row counter

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CAS Before RASSet column address

Apply CAS first (opposite of RW)

Then toggle RAS enough times tocycle through row addresses

On-board refresh counter applies

the row addresses

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TimingSay need to refresh every 64ms

Distributed refresh

Spread refresh out evenly over 64msSay on a 4Mx4 DRAM, refresh every64ms/4096=15.6us

Total time spent is 0.25ms, but spread

Burst refreshSame 0.25ms, but all at once

May not be good in a computer system

Refresh takes 1 % or so of total time

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Larger/W

ider Memories

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Bidirectional LinesOne set of data pins

Used as input for write

As output for read

Tri-state

Makes sense because dont needboth at once

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Synchronous DRAM (SDRAM)

Common type in PCs late-90s

Burst transfers

Multiple banks

PipelinedStart read in one bank after another

Come back and read the resulting valuesone after another

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SDRAM on Xess BoardRelatively small at 128Mbits

2M X 4 banks X 16 bits

Refresh every 64ms

Supports pipelining

Bidirectional data lines

Detailed info in a few slides

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DDR DRAMDouble Data Rate SDRAM

Transfers data on both edges of

the clock

Currently popular

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RAMBUS DRAM (RDRAM)

Another attempt to alleviatepinout limits

Many (16-32) banks per chip

Made to be read/written inpackets

Up to 400MHz bus speedsBut DDR doing very well also

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DRAM Controllers

Very common to have circuit thatcontrols memory

Handles banksHandles refresh

Multiplexes column and row

addressesRAS and CAS timing

Northbridge on PC chip set

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Next: Specifics on Our Chip

Protocol for reading/writingActivate row first

Then read/write with column

Initialization

Setting parameters

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Block Diagram

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Activate Row

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Burst Reads

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Read with Autoprecharge

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Read w/o Autoprecharge

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Random Reads

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Alternating Banks

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SingleWrite

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Initializing

See P.9 of Micron datasheet

Just NOP commands for 100 us

Precharge all banks

Two Auto Refresh commands

Then load mode register

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Mode Register

Several operating modes ofSDRAM

Burst or single

0

2 or 3 Order or

accesses

1,2,4,8 or

full page

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DRAM Links

DRAM on XSA-100 boardhttp://www.hynix.co.kr/datasheet/pdf/dram/(2)HY57V281620A(L)T-I.PDF

Low-Tech RAM descriptionhttp://www.arstechnica.com/paedia/r/ram_guide/ram_guide.part1-1.html

Datasheetshttp://www.hynix.co.kr/datasheet/pdf/dram/(2)HY57V281620A(L)T-I.PDF

http://download.micron.com/pdf/datasheets/dram/128msdram_f.pdf

http://www.infineon.com/cmc_upload/documents/018/329/hb39s128CT.pdf

Verilog modelhttp://download.micron.com/downloads/models/verilog/sdram/sdr/128meg/

mt48lc8m16a2.zip

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Assignment

Try Block RAMMaybe to scan small stamps

Or as character/sprite device

Make DRAM controller to refreshscreen

Deadline end of next week

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Next Time

Thursday 9/11 read Kurt Akeley,"Reality Engine Graphics",

SIGGRAPH 93Link is

http://doi.acm.org/10.1145/166117.166131

03 dram

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