03/10/2005 © J.-H. Jiang 1

The Initialization of Synchronous Hardware Systems

EECS 290A – Spring 2005

UC Berkeley

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Outline

Origins of the initialization problem Taxonomy of initialization approaches

Explicit vs. implicit reset An explicit reset can be either synchronous or

asynchronous A synchronous explicit reset can be seen as a

special case of an implicit one Initializability

Initialization sequences Effects of retiming & resynthesis Safe and delay replaceability

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Origins of the initialization problem

Power-up an electrical system No control over the internal logic values

Find a place to start For combinational circuits, no problem

Assume acyclic circuits For sequential circuits, wait a second (or a

minute) …

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FSM vs. HFSM

Mathematical finite state machine (FSM) is a

6-tuple (, Q, I, , , ) : input alphabet, Q : state set, I : initial

state(s), : transition function, : output function, : output alphabet

Hardware finite state machine (HFSM) is a

5-tuple (, Q, , , ) Need to find out the set I of initial states, and

how to get there

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Taxonomy of initialization approaches

Basic classification A system is of explicit reset if its registers are

initialized by some designated reset signal A system is of implicit reset if its registers are

initialized w/o using any designated reset signal

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Explicit vs. implicit reset

Some designs may not afford to have explicit reset for all registers

Power-up delays are usually acceptable

explicit implicit

area larger smaller

complexity simple complicated

reset speed fast slow

mechanisms synchronous or asynchronous

synchronous

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Explicit reset

Synchronous vs. asynchronous

In what follows, we are concerned with synchronous reset

sync. async.

area larger smaller

reset speed slower faster

skew effects robust vulnerable

meta-stability no yes

clock-triggered yes no D Q

clk

reset

Async. reset

D Q

clk

0

1

reset

0

Synch. reset

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Implicit reset

Driving a system from a power-up state to a desired initial state Apply a “meaningful” input sequence (reset

sequence) If the power-up state can be observed (partially or

fully), can have different reset sequences. Otherwise, need a universal reset sequence.

Only synchronous reset

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Synchronous explicit reset as a special case of implicit reset Synchronous explicit reset as a special case

of implicit reset Treat the reset signal as a normal primary

input signal; represent the reset circuitry explicitly in the circuit graph

Initialization sequence of length 1 It allows a uniform treatment

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Initializability Unlike those with explicit reset, systems with implicit reset may

not always be initializable Must exist a single input sequence which brings a system

from any power-up state to a known initial state

This above example is not initializable, but has a homing sequence [Koh78].

[0] [1]0

1

1

0

1

[1] [0]0 0

1

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Initialization sequences

Reset or synchronization sequences In the literature, initializing sequences and reset sequences have

different meanings. Initializing sequence: An input sequence that brings the underlying

system from an unknown state (all memory elements are of unknown value ) to an initial state. (Commonly used in fault simulation and test generation. [CA89])

Reset sequence: An input sequence that brings the underlying system from any state to an initial state.

(Any initializing sequence is a reset sequence, but not the converse.)

Here initialization sequences are meant to be the latter definition with a slight generalization:

An input sequence that brings the underlying system from any state to a set of equivalent initial states.

ci

o

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Properties of initializable FSMs

Def. A reset state is the state to which its underlying system is driven from any state by a fixed input sequence (if exists), i.e., a reset sequence.

A machine M is resetable if M has a reset state. Thm. [Pix92] Every state reachable from a reset state

is a reset state. (The set of reset states is closed under any input sequence.) How about considering output observation? (Homing

sequences)[0] [1]0

1

1

0

1

[1] [0]0 0

1

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Align equivalence

Motivation: Decide whether two gate-level designs are equivalent without reference to the intended environment, initial states, and reset sequences.

Def. Two states s1 and s2 of machines M1 and M2, respectively, are alignable if an input sequence (called an aligning sequence) s.t. (s1) ~ (s2) (s) denotes the destination state from s upon ; “~”

denotes standard state equivalence (on I/O behavior) Def. Two machines M1 and M2 are align equivalent,

denoted as M1 M2, if all state pairs (s1M1,s2 M2) are alignable Prop. Relation is symmetric and transitive, but not

reflexive

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Align equivalence

Thm. [Pix92] M1 M2 iff an input sequence (called a universal aligning sequence) that aligns all state pairs.

Thm. [Pix92] M M iff its quotient machine M/~ is resetable. (An input sequence aligns all pairs of (sM, tM) iff is a reset sequence for M/~.)

Thm. [Pix92] Relation is an equivalence relation on the set of machines whose quotients are resetable.

Thm. [Pix92] If M1 and M2 are resetable and have at least one pair of equivalent states, then M1 M2.

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Equivalence modulo power-up delay

Align equivalence is a very strong relation It aims to preserve the same reset sequence

for different designs In many cases, we only require two

initializable machines to be equivalent after they are initialized (really different from the above argument?)

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Initializing retimed circuits

Case: explicit-reset circuits of registers w/ reset values Backward retiming may not be valid Solution:

Allow only forward retiming [ESS96], Check the validity of backward moves (image

computation) [TB93], or Convert such a circuit to one of registers w/o reset

values by showing reset circuitry explicitly [SMB96] (better)

0

1

?

?

D Q

clk

0

1

reset

0

Synch. reset

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Initializing retimed circuits

Case: explicit-reset circuits of registers w/o reset values Both forward and backward moves of retiming are okay Correction of initialization sequences is same as

implicit-reset circuits (to be discussed)

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Initializing retimed circuits

Case: implicit-reset circuits Both forward and backward moves of retiming are okay Let n be the maximum number of registers moved

forward across any node in retiming. Then the reset sequence of the retimed circuit can be obtained by prefixing the original reset sequence with an arbitrary input sequence of length n (retiming lemma [LS83])

There exists a transformation-independent upper bound of length increase

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Initializing iteratively retimed & resynthesized circuits Unlike only retimed ones, circuits transformed by

retiming & resynthesis have no general transformation-independent bound on the length increase of initialization sequences The longest dangling path in state space corresponds

to the length increase of initialization sequences

(greatest fixed point computation) Iterative retiming & resynthesis can unboundedly

elongate the dangling path to strongly connected states

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Modify dangling paths by retiming & resynthesis Retiming & resynthesis can

eliminate/generate dangling paths of arbitrary lengths

ExampleLet Q = {s0,s1,s2,s3} with state transition graph GTo eliminate s0, 1. Resynthesize : {0,1} Q Q as

(x,s) = 2(1(x,s)) with 1: {0,1} Q Q\{s0} 2: Q\{s0} Q

2. Retime registers backward in-between 1 and 2

Similarly, we can further remove s1.

s2 s30

1

1

0

0,1

s1

s0

0

1

G

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Initializing retimed circuits

Preserving reset sequences after retiming [MSM04] Make every dangling state created by forward

retiming follow the next state transition of some non-dangling states

Require additional logic; not as simple as increasing reset sequences

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Safe replaceability

Def. [SP94] Machine M2 is a safe replacement for M1 (M2 M1) if given any state s2 M2 and any finite input sequence , there exists some state s1 M1 s.t. the output sequences of M1 and M2 starting from s1 and s2, respectively, are the same under

Thm. If M2 M1 and is a reset sequence for M1, then is also a reset sequence for M2, and 1(s1, ) ~ 2(s2, ) for any s1 M1 and s2 M2

HFSM

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Conclusions

We studied the initialization of synchronous hardware system including Various reset mechanisms Initializability, reset sequences Various notions of equivalence The effects of retiming & resynthesis on reset

sequences Safe replaceability

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