17.06.20 12:53CSCI 150 Introduction to Digital and Computer

System Design Lecture 3: Combinational Logic Design V

Jetic Gū2020 Summer Semester (S2)

Overview

• Focus: Arithmetic Functional Blocks

• Architecture: Combinatory Logical Circuits

• Textbook v4: Ch4 4.2; v5: Ch3 3.9

• Core Ideas:

1. Binary Adder

Systematic Design Procedures1. Specification: Write a specification for the circuit

2. Formulation: Derive relationship between inputs and outputs of the systeme.g. using truth table or Boolean expressions

3. Optimisation: Apply optimisation, minimise the number of logic gates and literals required

4. Technology Mapping: Transform design to new diagram using available implementation technology

5. Verification: Verify the correctness of the final design in meeting the specifications

Review

P0 Review

Functional Components (1)

• Value-Fixing, Transferring, Inverting, Enabler

• Decoder

• Input: �

• Output: � , �

A0A1 . . . An−1

D0D1 . . . D2n−1 Di = mi

Review

P0 Review

3-to-8 Decoder

01234567

0

1

2

Functional Components (2)• Encoder

• Input: � with only one positive value

• Output: �

• Priority Encoder: validity, priority output

• Multiplexer

• Switching between multiple input channels

m0, . . . , m2n−1

A0, . . . , An−1

Review

P0 Review

3-to-8 Decoder

01234567

0

1

2

Binary Adder

Summary

P1 Binary Adder

The good stuff begins

Binary Adder• Perform binary addition

• 1-bit Half adderinput � , � ;output � , �

• Full adderinput vectors � , � , and single-bit � ;output vector � and single-bit �

• Remember what we did before?

X YS C

X Y ZS C

Concep

t

P1 Binary Adder

1101001101

+0010110010

Augend �X

Carries

Addend �Y

Sum �S

ZC

0

1-bit Binary Adder

Review

P1 Binary Adder

1. #04-2020-1000-111_Lecture3_Combinational_Logic_Design_III, P3

ZX

+YAugend

Carries

Addend

Sum S

C

+

InputOutputX

YZ

1-Bit Binary Adder

S

C

SC

Full Adder

1-bit Binary Adder

Review

P1 Binary Adder

1. #04-2020-1000-111_Lecture3_Combinational_Logic_Design_III, P3

XYZ

1-Bit Binary Adder

S

C

SC

Full Adder

XYZ

3-to-8 Decoder

01234567

0

1

2 C

S

1-bit Half Adder

• Half adderinput � , � output � , �

X YS C

Concep

t

P1 Binary Adder

X+Y

Augend

Carries

Addend

Sum S

C

+

InputOutput

P1 Binary Adder

X+Y

Augend

Carries

Addend

Sum S

C

+

InputOutput

X Y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

1-bit Half Adder

Concep

t

P1 Binary Adder

X+Y

Augend

Carries

Addend

Sum S

C

+

InputOutput

1-bit Half Adder

Concep

t

158 CHAPTER 3 / COMBINATIONAL LOGIC DESIGN

The half adder can be implemented with one exclusive-OR gate and one AND gate, as shown in Figure 3-40.

Full Adder

A full adder is a combinational circuit that forms the arithmetic sum of three input bits. Besides the three inputs, it has two outputs. Two of the input variables, denoted by X and Y, represent the two significant bits to be added. The third input, Z, rep-resents the carry from the previous lower significant position. Two outputs are neces-sary because the arithmetic sum of three bits ranges in value from 0 to 3, and binary 2 and 3 need two digits for their representation. Again, the two outputs are designat-ed by the symbols S for “sum” and C for “carry”; the binary variable S gives the value of the bit of the sum, and the binary variable C gives the output carry. The truth table of the full adder is listed in Table 3-12. The values for the outputs are determined from the arithmetic sum of the three input bits. When all the input bits are 0, the out-puts are 0. The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to 1. The C output is a carry of 1 if two or three inputs are equal to 1. The maps for the two outputs of the full adder are shown in Figure 3-41. The simplified sum-of-product functions for the two outputs are

S = X YZ + XYZ + XY Z + XYZ

C = XY + XZ + YZ

The two-level implementation requires seven AND gates and two OR gates. However, the map for output S is recognized as an odd function, as discussed in

XY

S

C

FIGURE 3-40Logic Diagram of Half Adder

TABLE 3-12Truth Table of Full Adder

Inputs Outputs

X Y Z C S

0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

M03_MANO0637_05_SE_C03.indd 158 23/01/15 1:51 PM

1-bit Full Adder

Concep

t

P1 Binary Adder

ZX

+YAugend

Carries

Addend

Sum S

C

+

InputOutput

• Half adder1input � , � output � , �

X YS′� C′�

• Half adder2input � , � output � , �

S′� ZS C′�′�

• Full adderinput � , � , � ;output � , �

X Y ZS C

XYZ

1-Bit Binary Adder

S

C

SC

1-bit Full Adder

• Full adderinput � , � , � ;output � , �

X Y ZS C

Concep

t

P1 Binary Adder

ZX

+YAugend

Carries

Addend

Sum S

C

+

InputOutput

• Half adder1input � , � output � , �

X YS′� C′�

• Half adder2input � , � output � , �

S′� ZS C′�′�

C = C′� + C′�′�

1-bit Full Adder

• Full adderinput � , � , � ;output � , �

X Y ZS C

Concep

t

P1 Binary Adder

• Half adder1input � , � output � , �

X YS′� C′�

• Half adder2input � , � output � , �

S′� ZS C′�′�

C = C′� + C′�′�

XY

Z

1-Bit Half Adder

S

C C

1-Bit Half Adder

S

C

S

n-bit Full Adder

Concep

t

P1 Binary Adder

• Full adderinput vectors � , � , and single-bit � ;output vector � and single-bit �

X Y ZS C

1101001101

+0010110010

Augend �X

Carries

Addend �Y

Sum �S

C

0

Z

n-bit Full Adder

Concep

t

P1 Binary Adder

• Full adderinput vectors � , � , and single-bit � ;output vector � and single-bit �

X Y ZS C

1101001101

+0010110010

Augend �X

Carries

Addend �Y

Sum �S

C

0

Z

n-bit Full AdderP1 Binary Adder

A0 B0 0

1-Bi

t Bin

ary

Adde

r

S C

S0

1-Bi

t Bin

ary

Adde

r

S C

S1

1-Bi

t Bin

ary

Adde

r

S C

S2

1-Bi

t Bin

ary

Adde

r

S C

S3

A1 B1 A2 B2 A3 B3

…

Concep

t

• Ripple Carry Adder

Preview

• Binary Adder √

• Binary Subtraction (using complements)

• Adder-Subtractor Unit

• Contraction, Incrementing, Multiplication (by constant), Division (by constant)

• VHDL

Future

PX Future