978-1-4244-9485-9/11/$26.00 ©2011 IEEE

Implementation of a GMSK Communication System on FPGA

Juan Felipe Medina Lee, Student. Juan Felipe Patarroyo Montenegro, Student. Catalina Muñoz Morales, Student, Member, IEEE. Alexander López Parrado, Professor. Juan José Giraldo Gutiérrez, Researcher.

Universidad del Quindío GDSPROC

Armenia, Colombia jmedina_l@hotmail.com,

jpatarroyo_m@hotmail.com, catalina-0309@hotmail.com, parrado@uniquindio.edu.co, jjgg1987@hotmail.com,

Abstract— This paper presents the design and implementation of a complete communication system using the GMSK modulation scheme. The hardware is described in VHDL and implemented on Altera FPGA. Additionally, each block used to perform the implementation is completely described accomplishing all the requirements of this kind of modulation. Mueller & Müller algorithm is also performed to ensure timing synchronization between transmitter and receiver. This communication system was developed with educational purposes.

Keywords-GMSK; FPGA; timing synchronization; digital modulation; communication system

I. INTRODUCTION Gaussian minimum shift keying modulation (GMSK) is a digital

modulation highly used in radio communication systems due to the advantages that it presents; one of these advantages is the spectrum efficiency provided by a Gaussian filter. The implementation of this kind of modulation is very valuable, considering the increase of applications on wireless communications such as GSM and EDGE technologies. The design is based on the open source project GNU Radio [1]; it provides signal processing blocks to implement low-cost reliable RF hardware. The developed modules (transmitter and receiver) are described on VHDL using fixed point arithmetic and implemented on the Altera FPGA Cyclone II 2C70 [2]. There are only a few known implementations of this kind of systems on FPGA [3] [4] [5] [6], making this design very useful for future developments. In this case, Mueller & Müller algorithm is used to ensure timing synchronization; this algorithm is highly efficient but rarely implemented on hardware. The entire system is developed with modular blocks interconnected, using input and output enable control signals; the number representation of the system uses a bit width of 16 which provides the necessary resolution for the system to work. The fractional part (Q) is different for the modules contained on it. The audio CODEC of the board is used as the system output, therefore the highest sample rate is 48 KHz.

II. DESIGNED SYSTEM Fig. 1 shows the transmitter block diagram

Gaussian filter Mod FM

Mod IQ

NSPSD_IN

D_OUT

RESET_NCLK

CIC NSPS

Figure 1. Transmitter block diagram.

On the transmitter the binary input data are presented with a 1

KHz sample rate. The Gaussian filter represents each input symbol with 8 new samples in order to limit the band width (BW) of the signal. At the output of the Gaussian filter, the sample rate is 8 Ksps. The FM modulator uses a 0Hz carrier. The CIC filter increases the sample frequency ( sf ) up to 48 KHz. Finally, the I/Q modulator translates the signal spectrum around a 10 KHz carrier.

Fig. 2 shows the receiver block diagram

CIC Mueller & müller Mod IQ NSPSD_IN D_OUT

RESET_NCLK

Dem FM

Figure 2. Receiver block diagram.

The I/Q demodulator translates the input spectrum to base

band. The CIC filter reduces the sample rate to 8 Ksps. The Mueller & Müller module performs timing synchronization and generates one valid output for each group of 8 input symbols, reducing the sample rate to 1 Kbps.

A. Gaussian filter with Polyphase structure Fig. 3 shows a simplified block diagram of the Gaussian

interpolator with a polyphase structure. This block consists on a bank of eight finite impulse response (FIR) polyphase filters [7] that offers less computational cost and easier control. A counter circuit is connected to a multiplexer that selects the corresponding polyphase impulse response, a ready (RDY) output pin indicates a valid system output.

Pipeline register

Figure 3. Gaussian filter blocks diagram.

The sample rate at the input is 1 Kbps and the rate of the

interpolated symbols is 8Ksps. Each FIR polyphase filter of the bank is fourth ordered, so it

has five coefficients obtained from the Gaussian impulse response [7]. Fig. 4 shows the internal structure of each filter.

Figure 4. Internal structure of a FIR filter.

B. CIC Filters: Cascade integrator combs (CIC) filters are multirate and finite

response filters used to re-sampling a signal in a rate factor (R) [8] [9]. Fig. 5 shows the block diagram of the interpolator CIC filter.

Combs Zero Pad Integrators DATA_OUTDATA_IN

Figure 5. Interpolator general block diagram.

CIC filters consist on pipelined stages of N integrators and N

differentiators connected in cascade with a re-sampling module between them. The latency of the system depends on N.

Number representation of this block uses a bit width of 16 and a Q of 14 bits. Sign extension is necessary because the bit width of data_in has to be extended in order to overcome integrators stage gain.

C. Coordinate Rotation Digital Computer (CORDIC) Two modes of CORDIC algorithm were implemented:

vectoring, to compute arctangent function, and rotation for sine and cosine functions [10].

In this module Q is 13 bits, therefore, the value of π is represented with 25736. To facilitate the hardware implementation, every core using the module CORDIC has a Q=13.

This implementation of the CORDIC algorithm works in the four quadrants. To accomplish that, some sign issues had to be considered in the inputs.

D. FM Modulator: This system is used to modulate the incoming signal around a

0 Hz carrier signal. Frequency Modulation (FM) is based on a Numerically Controlled Oscillator (NCO) implemented with CORDIC algorithm. Finally, the modulator circuit generates a

complex envelope signal [11]. Fig. 6 shows the block diagram of the FM modulator.

-1Z

XIN + CORDIC

Dev RDYND

Out_ImagOut_Real

Figure 6. FM modulator block diagram.

E. I/Q Modulator

Fig. 7 shows the block diagram of I/Q modulator.

CORDIC RDY

Out_Real

Counter

In_RealIn_Imag

Figure 7. I/Q modulator block diagram.

The I/Q (in-phase/quadrature) modulator receives a complex

envelope signal and multiplies it by the real and imaginary parts of the carrier. The CORDIC circuit is very useful for this application because it performs the same operation as the I/Q modulation [10]:

)sin()cos( ZYZXX n −= (1) X is the real part of the complex envelope signal and Y the imaginary part. The carrier signal generated with CORDIC has a frequency of 10KHz.

F. I/Q Demodulator The I/Q demodulator translates input spectrum to baseband

multiplying by a complex carrier signal. Fig. 8 shows the I/Q demodulator block diagram.

Figure 8. I/Q demodulator structure.

G. FM Demodulator The FM demodulator recovers phase information using arctan

function implemented with CORDIC. The diagram of this block is shown on Fig 9.

-1Z

-1Z

-1Z

-1Z

-1

Complex

Multiplier

ARC TANCORDIC

Q

I

OUT

Figure 9. FM demodulator.

H. Timing Recovery This block is based on the classic version of the Mueller and

Müller (M&M) algorithm [12]. The purpose of this block is to receive the symbols coming from the FM demodulator, to estimate their timing lag and finally, to do the proper timing correction. For this task, the synchronizer is composed of 5 main blocks: sampler,

Iterator CORDIC ALGORITHM

Zo Rdy Xo (Imag) Xn Yo Nd (Real) Yn Data in

0

Nd

Nd

Data in

Rd

Coefficients

Data out

Rfd

Rdy

RDY pin control and multiplexer

Counter

FIR filters bank (8)

Filter FIR (1)

Filter FIR (2)

…

Filter FIR (8)

Data_

Nd

Data_out

decision device, timing error detector, loop filter and adjustable clock. These blocks are shown on Fig. 10.

M & MTiming Error

DetectorSampler Decision

Device

LoopFilter

AdjustableClock

y (t)

x (e)

ak

Figure 10. Block diagram of the Time Recovery module.

The block that makes timing correction is the sampler, it is

implemented using a interpolator FIR filter; it has 8 coefficients that change their values depending on the signal coming from the adjustable clock module. However, the most important blocks of the synchronizer are the timing error detector and loop filter. They estimate timing error according to M&M algorithm [13]. This index indicates the timing error in the received signal and it also sets which of the coefficients are going to be used in the FIR filter.

1) Sampler The 7th order FIR filter was implemented using the usual

direct form hardware structure [13]; however, it is a time variant filter with a set of 129 coefficients that depend on the d_mu input; furthermore, each set of coefficients represents a particular timing lag. The FIR filter block diagram is shown on Fig. 4. The filter uses 8 different synchronous ROM memories storing the 129 sets of coefficients that are multiplied by the registered values.

2) Timing Error Detector and Loop Filter The Timing Error Detector is based on Mueller and Müller

work. The decision device is integrated with this block in order to get the ak coefficient based on the timing delay of the input signal. The loop filter calculates the expectation of the error and turns it into an index near Nsps, that is used for reduce the sample rate of the incoming signal by a factor of Nsps. The diagram of this block is described on Fig. 11.

-1Z Sign

X

Sign

X

+ -

X

d_gain_omega

+ -

d_omega_mid d_omega_rel

+

d_omega_mid

-1Z

X

d_gain_mu

+

IN

OUT Figure 11. Timing error detector and loop filter internal structure

The most important aspect of this block is the fact that it has a

saturator that prevents data overflow (it restricts symbol timing error to values below the number of samples per symbol (Nsps), in this case Nsps=8) and makes this synchronizer a very robust and stable core.

3) Adjustable Clock Adjustable clock module has a register that stores the value of

its output plus the output value coming from the loop filter. Each time that a new sample arrives from the demodulator to

the synchronizer, the decrementer checks if the registered value is less than 1, otherwise, it decreases this value by 1 until it is less

than 1, at that point, the ready output signal flag sets during one clock cycle, a new value is acquired and the value of the coefficients on the FIR filter changes as a result.

III. EXPERIMENTAL RESULTS The modulator-demodulator GMSK system was tested using

the Altera FPGA EP2C70F896C6 [2]. In the case of the transmitter, the percentage of resources used was 10% (6,702/68,416) for logic elements, 9% (6,458/68,416) for combinational functions, 4% (2,687/68,416) for dedicated logic registers, <1% (8,248/1,152,000) for memory bits, 1% (4/300) for embedded multiplier 9 bits elements. In the case of the receiver, the percentage of resources used was 9% (6,140/68,416) for logic elements, 8% (5,295/68,416) for combinational functions, 6% (3,971/68,416) for dedicated logic registers, 1% (15,914/1,152,000) for memory bits, 10% (30/300) for embedded multiplier 9 bits elements. Signals from the tests were caught using the logic analyzer SignalTap II [14]. The maximum clock frequency supported by the system is 26.9 MHz, it was calculated using static timing analysis method. The clock to ouput time (TCO) of the system is 25.8ns.

A) Experimental results for the Gaussian filter whit polyphase

structure: Fig. 12 shows the experimental results for the Gaussian filter.

data_out

data_in

Figure 12. Polyphase structure Gaussian filter experimental results.

The top side signal is the filtered data at the output of the module, and the bottom side is the input signal with -1 and 1 random samples with Q=14. It is shown how each symbol is gaussian shapped at the filter’s output.

B) Experimental results of CIC Interpolation filter

Fig. 13 shows the experimental results CIC Interpolation filter.

data_out

data_in

Figure 13. CIC Interpolation filter experimental result.

The signal data_in is a low sampled sinusoid and the signal

data_out is the output of the CIC interpolation filter with R=8 and N=8.

C) Experimental results of CIC Decimation filter Fig. 14 shows the experimental results CIC decimator filter.

data_out

data_in

Figure 14. CIC decimation filter experimental result.

The signal data_in is a high sampled sinusoid and the signal data_out is the output of the CIC decimator filter with R=8 and N=8;

D) Experimental results of the FM modulator.

Fig. 15 shows the experimental results of the FM modulator.

d_out_real

data_in

d_out_imag

Figure 15. FM modulator experimental result.

The signal data_in takes values of 1 and 0.3. The other two

signals together are the complex envelope signal. E) Experimental results of the I/Q modulator. Fig. 16 shows the experimental results of the I/Q modulator. To simulate the I/Q modulator, the data of the signal tap were exported to MATLAB and the spectrum of that signal was calculated.

The graphic on the left shows spectrum of the data calculated with the theoretical I/Q modulator in MATLAB. The graphic on the right shows the spectrum of the data from the SignalTap II.

Figure 16. I/Q modulator experimental result.

F) Experimental Results for the Timing Recovery. This system is able to work at a maximum frequency of 78

MHz. The results of the timing recovery process were exported to MATLAB. This result is shown on Fig. 17.

The input signal is a random bit stream with a preamble used to estimate frame beginning; it takes high values until the preamble is processed, after that, the real data is fully synchronized with the system’s clock.

Figure 17. Timing recovery system experimental result.

The timing error got reduced when the preamble is processed.

IV. CONCLUSION A Mueller and Müller timing recovery system implemented

on FPGA is presented. In addition of synchronizing the incoming data, it also divides the sample rate in 8, which is the number of samples per symbol.

The cores are completely parametrizable using VHDL generics.

In [4] a similar system was implemented for an specific purpose using a ΔΣ frequency discriminator-based synthesizer , it works at a carrier frequency of 1.9 GHz, however, it doesn’t make up-conversion and the whole system is fully embedded. By the other side, the current system is completely described with modular blocks, using generics and a low cost FPGA in order to ease pedagogic purposes in despite of the low frequency used.

The system is open hardware inspired on GNU radio for digital communications applications with educational purposes.

In order to reduce the processing complexity and hardware utilization, the system operates on a base band frequency.

The model used to synchronize the blocks is very efficient and allows easy changes on the sample rate.

The CIC filters and the CORDIC allow low complexity computation due to their multiplierless structure.

REFERENCES

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