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Analysis and Des

Single-Sta

Mehdi Narimani

Department of Electrical and Computer EnUniversity of Western Ontario

London, Canadamnariman@uwo.ca

Abstract A new single-stage ac-dc co

interleaved input section is proposed in

converter can perform input power facto

reduced input current harmonic content due

input section. The proposed rectifier can a

currents that do not have deadband regio

current that is continuous for all load conditi

the operation of the new converter is explain

characteristics are determined by anal

characteristics are used to develop a procedur

the converter. The operation of the pro

converter is confirmed with experimental res

a prototypet.

I. INTRODUCTIONPower factor correction (PFC) is neede

supplies for them to comply with harmonicIEC 1000-3-2 [1]-[3]. The most common apto use two-stage power conversion schemefront-end ac-dc converter stage to performwith PFC and a back-end dcdc converter st

desired isolated dc output voltage [4];schemes, however, can be costly and comreduce the cost, size, and complexity assostage ac-dc power conversion with PFC,proposed single-stage power-factor-corconverters that integrate the functions of PFdc conversion in a single converter topologphase [5]-[12] and three-phase [13]-[25] conproposed in the literature, with three-phasepreferred over single-phase converters fapplications.

Previously proposed three-phase siconverters, shown in Fig.1, however, havefollowing drawbacks that have limited their

They are implemented with three sepastage modules [13]-[15], Fig. 1(a).

gn of an Interleaved T

ge PFC AC-DC Conver

gineering

Gerry Mosc

Department of Electrical anUniversity of We

London,

gmoschop

verter with an

this paper. The

correction with

to its interleaved

lso produce input

s and an output

ns. In this paper,

d, its steady-state

ysis, and these

e for the design of

osed interleaved

lts obtained from

d in ac-dc powerstandards such asproach to PFC iss consisting of aac-dc conversionge to produce the

such two-stageplex. In order tociated with two-researchers haveected (SSPFC)

and isolated dc-y. Several single-verters have beenconverters beingr higher power

gle-stage ac-dct least one of theidespread use:

rate ac-dc single-

The converter components arhigh voltages so that switchesvery high voltage ratings are[23].

The input currents are distorteamount of low frequencyconverter has difficulty perconversion simultaneously [16]

(a)[14]

(b)[20]Figure 1. Three-phase, single-sta

ree-Phase

ter

opoulos

Computer Engineeringstern Ontarioanada

uwo.ca

exposed to very dc busand bulk capacitors withrequired [17], [18], [22],

and contain a significantharmonics because theorming PFC and dc-dc.

ge, ac-dc converters.

978-1-4673-4355-8/13/$31.00 2013 IEEE 1005

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The converter must be controlled using verysophisticated techniques and/or non-standard techniques[5]-[11]. This is especially true of resonant typeconverter that need variable switching frequency controlmethods to operate.

The output inductor must be very low, which makes theoutput current to be discontinuous. This results in a veryhigh output ripple so that secondary diodes with high

peak current ratings and large output capacitors to filterthe ripple are needed [13]-[20].

Most of them are DCM at input and need to have a largeinput filter to filter out large high-frequency harmonics[13]-[15], [17], [18],[22]-[25].

This paper presents a new three-phase, single-stagerectifier that has an interleaved input and that does not haveany of these drawbacks. The outstanding features of thisconverter are that it has lower input section peak currentstresses and a better harmonic content than similar converterwith a non-interleaved output, the output current is continuousfor all load ranges (thus reducing output section componentcurrent stresses), and the dc bus voltage is less than 450 for all

line and load conditions. In this paper, the operation of thenew converter is explained, its steady-state characteristics aredetermined by analysis, and these characteristics are used todevelop a procedure for the design of the converter. Theoperation of the proposed interleaved converter is confirmedwith experimental results obtained from a prototype.

II. OPERATION OF THE PROPOSED CONVERTERThe proposed converter and its key waveforms are shown

in Fig. 2 and 3. The proposed converter uses auxiliarywindings that are taken from the converter transformer to act

as "magnetic switches" to cancel the dc bus capacitor voltageso that the voltage that appears across the diode bridge outputis zero. When the primary voltage of the main transformer ispositive, Auxiliary Winding 1 cancels out the dc bus voltageso that the output voltage of Diode Bridge 1 (DB1) is zero andthe currents in input inductors La1, Lb1, and Lc1 rise. When theprimary voltage of the main transformer is negative, AuxiliaryWinding 2 cancels out the dc bus voltage so that the outputvoltage of Diode Bridge 2 (DB

2) is zero and the currents in

input inductors La2, Lb2, and Lc2 rise. When there is no voltageacross the main transformer primary winding, the total voltageacross the dc bus capacitors appears at the output of the diodebridges and the input currents falls since this voltage is greaterthan the input voltage. If the input currents are discontinuous,then they will be naturally sinusoidal and in phase with theinput voltages.

The converters modes of operation are explained in thissection. Typical converter waveforms are shown in Fig. 2. Theequivalent circuit in each stage is shown in Fig. 3.Theconverter goes through the following modes of operation:

Mode 1 (t0 < t < t1)(Fig. 4(a)):During this interval, switches S1 and S2 are ON. In this

mode, energy from dc bus capacitor C1 flows to the outputload. Due to magnetic coupling, a voltage appears acrossAuxiliary Winding 1 that cancels the total dc bus capacitorvoltage; the voltage at the diode bridge output is zero and theinput currents in La1, Lb1, and Lc1 rise.

Mode 2 (t1 < t < t2)(Fig. 4(b)):In this mode, S1 is OFF and S2 remains ON. The energy

stored in L1 during the previous mode starts to transfer into thedc bus capacitor. The primary current of the main transformercirculates through D1 and S2. With respect to the converter'soutput section, the load inductor current freewheels in the

Figure 2. Proposed interleaved three-stage three-level converter. Figure 3. Typical waveforms describing the modes of operation.

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secondary of the transformer, which defines a voltage acrossthe load filter inductor equal to VL.

Mode 3 (t2 < t < t3) (Fig. 4(c)):

In this mode, S1 and S2 are OFF. The energy stored in L1still is transferring into the dc bus capacitor. The primarycurrent of the transformer charges C2 through the body diodesof S3 and S4. Switches S3 and S4 are switched ON at the end ofthis mode.

Mode 4 (t3 < t < t4) (Fig. 4(d)):

Inthis mode, S3 and S4 are ON and energy flows from the

capacitor C2 into the load. The magnetic switch cancels out thedc bus voltage and voltage across the auxiliary inductors L2becomes only the rectified supply voltage of each phase andthe current flowing through each inductor increases. Thismode ends when the energy stored in L1 completely transfersinto the dc bus capacitor. For the remainder of the switchingcycle, the converter goes through Modes 1 to 4, but with S3and S4 ON instead of S1 and S2 and DB2 instead of DB1.

It should be noted that input current is summation ofinductor currents iL1 and iL2 which are both discontinuous.However, by selecting appropriate values for L1 (= La1 = Lb1 =Lc1) and L2 (= La2 = Lb2 = Lc2) in such a way that two inductorcurrents such as iLa1 and iLa2 have to overlap each other, theinput current can be made continuous as shown in Fig. 5; thusreducing the size of input filter significantly. There is a natural180o phase difference between the currents in L1 and thecurrents in L2 as one set of currents rises when the transformer

(a) Mode 1 (t0 < t < t1) (b) Mode 2 (t1 < t < t2)

(c) Mode 3 (t2 < t < t3) (d) Mode 4 (t3 < t < t4)

Figure 4. Modes of Operation

Figure 5. Interleaving between two input inductor currents.

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primary is impressed with a positive voltage and the other setrises when the transformer primary is impressed with anegative voltage these two events occur 180o apart during aswitching cycle.

III. STEADY STATE ANALYSISThe converter operating characteristics for any given input

and output voltage are dependent on three key parameters:

transformer turns ratio N, input inductance L in and output Lo.The effect that each of these parameters has on Vbus can beseen with graphs of characteristic curves that have beengenerated with a computer program based on the proceduredescribed in [25], varying the parameter while keeping theothers fixed. Such graphs are shown in Fig. 6. Based thefollowing observations can be made based on these graphs:

A.A. Effect of output inductor value Lo on dc bus voltageVbus

It can be seen from Fig. 6(a) that varying Lo (but keeping

all the other parameters fixed, has a slight effect on Vbus forhigher output loads when the output is operating in CCM, but

does so at lower output loads when the output is in DCM.

This is because more energy can be transferred from the dcbus capacitor to the output when the output inductor current

is discontinuous rather than continuous, for the same amount

of average output current.

B.Effect of input inductor value Lin on dcbus voltage VbusIt can be seen in Fig. 6(b) that Vbus decreases as Lin is

increased and all the other parameters are kept constant.

Similar to what was stated above for the output inductor, less

energy is transferred from the input to the dc bus when the

inductor is larger and the current is more likely to approach

the boundary of CCM and DCM.

C.Effect of transformer turns ratio N on dc bus voltageIt can be seen in Fig. 6(c) that Vbus decreases as the

transformer turns ratio N is decreased. This is because as N islowered, the transformer primary current, which is related to

the current flowing out of the energy-storage capacitors,

increases for the same amount of load current and so does the

amount of energy that is pumped out of C1 and C2. If N is

very low, then C1 and C2 may pump out so much energy thatthe energy equilibrium at capacitor will result in a very low

dc bus voltage that will in turn force the converter to operate

with an output voltage that will always be lower than the

required value, especially under heavy load conditions.

Likewise, if N is very high, then C1 and C2 may pump out so

little energy that that the energy equilibrium C1 and C2 willresult in a very high dc bus voltage that will in turn force the

converter to operate with an output voltage that will always

be higher than the required value, especially under light load

conditions.

D.Effect of input voltage Vin on dc bus voltage

a. Effect of output inductor value Lo on dc bus voltage

b. Effect of input Inductor value Lin on dc Bus Voltage

c. Effect of transformer ratio value N on dc bus voltage

d. Effect of input voltage v in on dc bus voltage

Figure 6. Steady-State characteristic curves

(Vin=208Vrms, Vo=48V, fsw=100kHz).

0 200 400 600 800 1000 1200100

150

200

250

300

350

400

Po

(W)

CapacitorVoltage(V)

Lo

= 100 uH

Lo

= 30 uH

Lo

= 10 uH

0 200 400 600 800 1000 1200100

150

200

250

300

350

400

450

Po

(W)

Ca

pacitorVoltage(V

)

Lin

= 100 uH

Lin

= 140 uH

Lin

= 180 uH

0 200 400 600 800 1000 1200100

150

200

250

300

350

400

450

Po

(W)

Capa

citorVoltage(V)

N = 3.0

N = 2.5

N = 2.0

0 200 400 600 800 1000 1200100

150

200

250

300

350

400

450

Po

(W)

CapacitorVoltage(V)

Vin

LL

=265 Vrms

Vin

LL

=209 Vrms

Vin

LL

=188 Vrms

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Fig. 6(d) shows the effect of input voltage on DC busvoltage. As can be seen, increasing the input voltage

increases the dc bus voltage. This is because more energy is

pumped into the capacitors when the input voltage is at high

line.

IV. CONVERTERDESIGNA procedure for the design of the converter is presented in

this section and is demonstrated with an example. Thefollowing criteria should be considered when trying to designthe converter:

i. The energy-storage capacitor voltage Vbus should notbe excessive. The value of Vbus should be kept tobelow 800 V if possible so that the use of bulkier,more expensive capacitors can be avoided.

ii. Excessive peak output and input currents should beavoided.

iii. The input line current must satisfy the necessaryregulatory agency requirements of harmonic contentsuch as IEC1000-3-2 Class A.

A design procedure for the selection of convertercomponents based on the characteristic curves presented in theprevious sections of this paper is given along with an exampleto illustrate how the converter can be designed. The converteris to be designed with the following parameters for theexample:

Input voltage: Vin = 208 10% Vl-l, rmsOutput voltage: Vo = 48 V

Maximum output power: Po = 1100 W

Switching frequency: fsw = 1/Tsw = 100 kHz

Maximum capacitor voltage: (for each capacitor) 450 V

Input current harmonics: EN61000-3-2 for Class A

electrical equipment.

Step1: Determine Value for Turns Ratio of MainTransformer N

N is an important parameter as it affects the amount ofreflected load current that is available at the transformerprimary to discharge the bus capacitors. Fig. 6(c) is anexample of how the value of N affects the primary-side dc busvoltage. If N is very low, then there is little reflected loadcurrent available to discharge the bus capacitors, which canresult in an extremely high DC bus voltage. If N is high, thenthe primary current may be very high as there will be a highamount of current circulating in the transformer primary,which will create significant conduction losses. A trade-offbetween high values of N and low values of N, therefore, mustbe considered when selecting a value of N.

Selecting a value of N, however, cannot be done with asimple equation and must be done using some other method.One way of doing so is to use the computer program describedin [25] to examine a wide range of potentially validcombinations of Lo and Lin combinations that allow theconverter to work for the two most extreme line and loadconditions: high line, light load and low line, full load. For this

particular design example, numerous graphs of characteristiccurves for different values of N were generated by the authors(not shown here due to space) and based on these graphs, avalue of N = 2.5 is selected as an appropriate value.

As a check to see if this value makes sense,equation (1) -which shows the relation between Vbus, D, Vo and N can beused.

2 1For this check, the operation of the converter at minimum

input line when it operates with minimum primary-side dc busvoltage Vbus,min and maximum duty cycle Dmax should beconsidered. If the converter can produce the required outputvoltage and can operate with discontinuous input andcontinuous output currents in this case, then it can do so for allcases. Substituting Vbus,min and maximum duty cycle Dmax intoequation (1) gives

, 2

. 2

Substituting Vo = 48, N = 2.5, and Dmax = 0.8 (0.8 has beenselected as a conservative Dmax to provide some margin) gives

, 2480.8 . 2.5 300 3

A bus voltage of Vbus,min = 300 V or Vbus/2 = 150 V isacceptable. If a very low value of Vbus,min = 100 V or a valueof Dmax > 1 would have been found based on equation (2),then the value of N under consideration would have beenunacceptable and another value would have to be considered.It should be noted that the dc bus voltage has not beendetermined yet. All that has been determined thus far is avalue of N that can operate with an acceptable duty cycle foran acceptable minimum dc bus voltage.

Step2: Determine Value for Output Inductor Lo

For having CCM at output, the minimum value of Loshould be the value of Lo with which the converters outputcurrent will be continuous on the when the converter isoperating with maximum input voltage, minimum duty cycle(Dmin), and minimum Load (10% of Po,max). If this condition ismet, then the output current will be continuous for all other

converters operating conditions. The minimum value of Locan therefore be determined to be

,

0.1 . , . 1 2 .

2 4

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This results in a low ripple at output and low peak currentrating for secondary diodes and consequently lower outputcapacitor needs to filter the ripple. Substituting Vo = 48,, 1100 , Dmin = 0.1 and fsw=100Khz, therefore thevalue of Lo should be larger than 47 H. In this case Lo=100H is chosen to have less ripple at output and decrease theoutput capacitance filter.

Step 3: Determine Value for Input Inductor Lin

The value for L1 and L2 should be low enough to ensurethat their currents are fully discontinuous under all operatingconditions, but not so low as to result in excessively high peakcurrents. This can be done using the computer program withthe following equations, which are based on the descriptionsgiven in [25]. For the case where L1 = L2 =L are such that theiL1 and iL2 remain discontinuous for all operating conditions,then the average input power can be expressed as;

32

1 ,,

32 .

1 ,,

(5)

where fsu is the input ac frequency and and

, 2 , 14 .

. .

,1 ,

6

By substituting the value of is,k(21), Pin can be expressed as:

3 2 .1

, ,

7

3 . 8 . 2 . . .1

,

1 ,

By assuming thePin =Po, Lin can be achieved:

1 ,,

8

4 . . .1

,

1 ,

(9)

The worst-case to be considered is the case when the

converter operates with minimum input voltage and maximumload since if the input current is discontinuous under theseconditions, it will be discontinuous for all other operatingconditions and thus an excellent power factor will beachieved. In this case, Vin = 188 Vphase,rms and Vbus = 300 V ascalculated in Step 2 are used to determine Lin at the boundarycondition for the input section, and D = Dmax = 0.8; assumingthe converter to be lossless, Pin = Po = 1100 W is used. Thevalue of Lin = 180 H is found from the computer program.For this design, L = 140 H is used.

V. EXPERIMENTAL RESULTSA prototype of the proposed converter was built to confirm

its feasibility. The prototype was designed according to thefollowing specifications:

Input voltage Vin = 20810% Vrms (line-line),

Output voltage Vo = 48 V,

Output power Po = 1.1kW,

Switching frequency fsw = 100 kHz.

The main switches were IRFP27N60KPbF, and the diodeswere UF1006DICT. The components were Lin = 140 H, Lo =100 H and C1, C2 = 2200 F. The auxiliary transformer ratio

was 1:2 and the main transformer ratio was 2.5:1. Typicalwaveforms are shown in Fig. 7. The following should be notedfrom Fig. 7:

The proposed converter is a multilevel converter so thatits switch voltage waveforms (Fig. 7(a) resemble thosefound in a multilevel converter.

The proposed converter is also full-bridge converter andthus has a typical transformer primary waveform (Fig.7(b)).

The proposed converter can operate with an excellentinput power factor and with an input current ripple that ismuch less than what is typically found in other single-

stage converters (Fig. 7(c)).

The proposed converter can operate with continuouscurrent at the output from 10% of full load to full load,which makes the output current have less ripple (Fig.7(d)).

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VI. CONCLUSIONAn interleaved three-phase, three-level, single-stage

power-factor-corrected ac/dc converter was presented in thispaper. The proposed converter uses auxiliary windings takenfrom its power transformer as magnetic switches to cancel thecapacitor voltage in a way the input inductors act likeinductors in a three-phase single-switch boost converter tohave a single stage power factor correction. The proposedconverter can operate with lower peak voltage stresses acrossits switches and the dc bus capacitors as it is a three-levelconverter. This allows for greater flexibility in the design ofthe converter and ultimately improved performance. Theproposed converter can operate with an input current harmoniccontent that meets the EN61000-3-2 Class A standard withminimal input filtering due to the interleaved structure. The

output inductor of the proposed converter can be designed towork in CCM mode over a wide load range. This results in alower output inductor current ripple than that found inpreviously proposed converters. The operation of the proposedinterleaved converter was confirmed with experimental resultsobtained from a prototype.

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(a) Top switch voltages Vds1 and Vds2

(V: 100V/div., t:4 s/div.)

(b) Primary voltage of the main transformer

(V:100V/div.,t: 4 s/div.)

(c) Input current and voltage(V: 100 V/div, I: 4 A/div)

(d) Output inductor current

(I:10A/div., t: 4 s/div.)

Figure 7. Experimental results.

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