06ec-71 computer communication networks - … computer communication networks electronics &...

ELECTRONICS & COMMUNICATION ENGG VII SEMESTER C OURSE DIARY

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06EC-71

Computer Communication Networks


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Computer Communication Networks

Subject Code: 06EC71 IA marks: 25 Hours/ week: 04 Exam Hours: 03 Total Hrs: 52 Exam Marks: 100 PART - A UNIT - 1 Layered tasks, OSI Model, Layers in OSI model, TCP?IP Suite, Addressing, Telephone and cable networks for data transmission, Telephone networks, Dial up modem, DSL, Cable TV for data transmission. 6 Hours UNIT - 2 DATA LINK CONTROL: Framing, Flow and error control, Protocols, Noiseless channels and noisy channels, HDLC. 7 Hours UNIT - 3 MULTIPLE ACCESSES: Random access, Controlled access, Channelisation. 6 Hours UNIT - 4 Wired LAN, Ethernet, IEEE standards, Standard Ethernet. Changes in the standards, Fast Ethernet, Gigabit Ethernet, Wireless LAN IEEE 802.11 7 Hours PART - B UNIT - 5 Connecting LANs, Backbone and Virtual LANs, Connecting devices, Back bone Networks, Virtual LANs 6 Hours UNIT - 6 Network Layer, Logical addressing, Ipv4 addresses, Ipv6 addresses, Ipv4 and Ipv6 Transition from Ipv4 to Ipv6. 7 Hours UNIT - 7 Delivery, Forwarding, Unicast Routing Protocols, Multicast Routing Protocols 6 Hours UNIT - 8 Transport layer Process to process Delivery, UDP, TCP, Domain name system, Resolution 6 Hours TEXT BOOK:

1. Data Communication and Networking, B Forouzan, 4th Ed, TMH 2006

REFERENCE BOOKS: 1. Computer Networks, James F. Kurose, Keith W. Ross: Pearson education, 2nd Edition, 2003 2. Introduction to Data communication and Networking, Wayne Tomasi: Pearson education 2007


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LESSON PLAN

Subject Code: 06EC71 IA marks: 25 Hours/ week: 04 Exam Hours: 03 Total Hrs: 62 Exam Marks: 100

S. No. Topics Unit I

1 Introduction 2 Layered tasks 3 OSI Model, Layers in OSI model 4 TCP?IP Suite, Addressing 5 Telephone and cable networks for data transmission 6 Telephone networks 7 Dial up modem, 8 DSL 9 Cable TV for data transmission

Unit II 10 DATA LINK CONTROL: Framing, 11 Flow and error control 12 Protocols 13 Protocols 14 Noiseless channels 15 Noiseless channels 16 Noisy channels 17 Noisy channels 18 HDLC Unit III

19 MULTIPLE ACCESSES: Introduction 20 Random access, 21 Random access, 22 Controlled access 23 Controlled access 24 Channelisation 25 Channelisation

Unit IV 26 Wired LAN, Ethernet, 27 IEEE standards, 28 Standard Ethernet. 29 Changes in the standards, 30 Fast Ethernet, 31 Gigabit Ethernet, 32 Wireless LAN IEEE 802.11

Unit V 33 Introduction 34 Connecting LANs, 35 Backbone LANs 36 Virtual LANs, 37 Connecting devices,


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S. No. Topics 38 Back bone Networks, 39 Virtual LANs Unit VI

40 Network Layer, 41 Logical addressing, 42 Ipv4 addresses, 43 Ipv6 addresses, 44 Ipv4 and Ipv6 45 Transition from Ipv4 to Ipv6. 46 Transition from Ipv4 to Ipv6.

Unit VII 47 Introduction 48 Delivery, 49 Forwarding, 50 Unicast Routing Protocols, 51 Unicast Routing Protocols, 52 Multicast Routing protocols 53 Multicast Routing protocols

Unit VIII 54 Introduction 55 Transport layer Process to process Delivery, 56 Transport layer Process to process Delivery, 57 UDP, 58 TCP, 59 Domain name system, 60 Domain name system, 61 Resolution 62 Resolution

Text Books:

1. Data communication and Networking: B Forouzan, 4 th Ed, TMH,2006 Reference Books:

1. Computer Networks, James F Kurose, Keith W Ross, Pearson education, 2 nd Edition, 2003.

2. Introduction to data communication and networking, Wayne Tomasi, Pearson education 2007.


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MODEL QUESTION PAPER

1. Explain the 5 key assumption for dynamic channel allocation in LANS and MANS.

2. Compare virtual circuit subnet with data gram subnet. 3. Mention the types of routing algorithm. Explain the line state routing. 4. List the techniques , the system designers use to achieve god quality of service.

Explain the leaky bucket algorithm. 5. Explain the IPV4 header format. 6. Explain CIDR. 7. Explain the UDP and TCP header. 8. List the principle header fields related to message transport, Explain. 9. A bit stream 10011101 is transmitted using standard CRC method. The

generator polynomial is x3+1. Show the actual bit string transmitted. Assume that the 3rd bit from left is inverted during transmission. Show that this error is detected at receivers end.

10. Explain the connection establishment and connection release in TCP. 11. Explain how IP addresses are assigned. Find the class of each address.

(i) 75.45.301.14 (ii) 221.34.7.82 (ii)14.23.120.8(iv)252.5.15.111 12. Explain 1 bit sliding window protocol with normal case and abnormal case. 13. What are pico net and scatter net in Bluetooth. 14. Discuss various types of ethernet cabling. 15. Discuss the principle of optimality. Explain link state routing. 16. What is multiplexing? Explain different types of multiplexing in transport layer. 17. Write short notes on:

(i) E-mail (ii) WAN (iii) Packet switching (iv) TDM


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06EC72

Optical Fiber Communication


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Optical Fiber Communication Subject Code: 06EC72 IA marks: 25 Hours per week: 04 Exam Hours: 03 Total Hrs: 52 Exam Marks: 100

PART A UNIT - 1 OVERVIEW OF OPTICAL FIBER COMMUNICATION: Introduction, Historical development, general system, advantages, disadvantages, and applications of optical fiber communication, optical fiber waveguides, Ray theory, cylindrical fiber (no derivations in article 2.4.4), single mode fiber, cutoff wave length, mode filed diameter. Optical Fibers: fiber materials, photonic crystal, fiber optic cables specialty fibers.

8 Hours UNIT - 2 TRANSMISSION CHARACTERISTICS OF OPTICAL FIBERS: Introduction, Attenuation, absorption, scattering losses, bending loss, dispersion, Intra model dispersion, Inter model dispersion. 5 Hours UNIT - 3 OPTICAL SOURCES AND DETECTORS: Introduction, LED’s, LASER diodes, Photo detectors, Photo detector noise, Response time, double hetero junction structure, Photo diodes, comparison of photo detectors. 7 Hours UNIT - 4 FIBER COUPLERS AND CONNECTORS: Introduction, fiber alignment and joint loss, single mode fiber joints, fiber splices, fiber connectors and fiber couplers. 6 Hours

PART - B UNIT - 5 OPTICAL RECEIVER: Introduction, Optical Receiver Operation, receiver sensitivity, quantum limit, eye diagrams, coherent detection, burst mode receiver, operation, Analog receivers 6 Hours UNIT - 6 ANALOG AND DIGITAL LINKS: Analog links – Introduction, overview of analog links, CNR, multichannel transmission techniques, RF over fiber, key link parameters, Radio over fiber links, microwave photonics. Digital links – Introduction, point–to–point links, System considerations, link power budget, resistive budget, short wave length band, transmission distance for single mode fibers, Power penalties, nodal noise and chirping.

8 Hours UNIT - 7 WDM CONCEPTS AND COMPONENTS: WDM concepts, overview of WDM operation principles, WDM standards, Mach-Zehender interferometer, multiplexer, Isolators and circulators, direct thin film filters, active optical components, MEMS technology, variable optical attenuators, tunable optical fibers, dynamic gain equalizers, optical drop multiplexers, polarization controllers, chromatic dispersion compensators, tunable light sources. 6 Hours UNIT - 8 Optical Amplifiers and Networks – optical amplifiers, basic applications and types, semiconductor optical amplifiers, EDFA. OPTICAL NETWORKS: Introduction, SONET / SDH, Optical Interfaces, SONET/SDH rings, High – speed light – waveguides. 6 Hours


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TEXT BOOKS: 1. "Optical Fiber Communication”, Gerd Keiser, 4th Ed., MGH, 2008. 2. "Optical Fiber Communications", John M. Senior, Pearson Education. 3rd Impression, 2007. REFERENCE BOOK: 1. Fiber Optic Communication - Joseph C Palais: 4th Edition.


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LESSON PLAN

Class: VII Semester Subject code: EC72 Subject: Optical Fiber Communication Hours/week: 04 Total Hrs: 62 Exam Marks: 100

Sl. No.

Topics

UNIT – 1 OVERVIEW OF OPTICAL FIBER COMMUNICATION

1 Introduction 2 Historical development 3 general system 4 general system, advantages 5 general system disadvantages 6 applications of optical fiber communication 7 optical fiber waveguides 8 Ray theory ,cylindrical fiber 9 single mode fiber ,cutoff wave length

10 mode filed diameter 11 Optical Fibers: fiber materials 12 photonic crystal, fiber optic cables

UNIT – 2 TRANSMISSION CHARACTERISTICS OF OPTICAL FIBERS

13 Introduction 14 Attenuation ,absorption 15 scattering losses, bending loss 16 dispersion, 17 Intra model dispersion, Inter model dispersion

UNIT – 3 OPTICAL SOURCES AND DETECTORS

18 Introduction

19 LED’s, LASER diodes 20 Photo detectors, Photo detector noise 21 Response time 22 double hetero junction structure 23 Photo diodes, comparison of photo detectors

UNIT – 4 FIBER COUPLERS AND CONNECTORS

24 Introduction, , , and 25 fiber alignment 26 joint loss 27 single mode fiber joints 28 fiber splices 29 fiber connectors 30 fiber couplers

UNIT – 5 OPTICAL RECEIVER


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31 Introduction

32 Optical Receiver Operation 33 receiver sensitivity 34 quantum limit, 35 eye diagrams 36 coherent detection 37 burst mode receiver, operation, 38 Analog receiver

UNIT – 6 ANALOG AND DIGITAL LINKS:

39 Analog links

40 Introduction, overview of analog links 41 CNR, multichannel transmission techniques 42 RF over fiber, key link parameters 43 Radio over fiber links 44 microwave photonics 45 Digital links – Introduction, point–to–point links 46 System considerations, link power budget 47 resistive budget, short wave length band 48 transmission distance for single mode fibers 49 Power penalties, nodal noise and chirping

UNIT - 7WDM CONCEPTS AND COMPONENTS

50 WDM concepts 51 overview of WDM operation principles, 52 WDM standards, Mach-Zehender interferometer, multiplexer,

Isolators and circulators 53 direct thin film filters, active optical components, MEMS technology 54 variable optical attenuators, tunable optical fibers, dynamic gain

equalizers, optical drop multiplexers, 55 polarization controllers, chromatic dispersion compensators, tunable

light sources UNIT – 8 OPTICAL NETWORKS

56 Optical Amplifiers and Networks 57 optical amplifiers, basic applications and types 58 semiconductor optical amplifiers, EDFA 59 Introduction, SONET / SDH 60 Optical Interfaces 61 SONET/SDH rings 62 High – speed light – waveguides

Text books: 1. Gerd Keiser, "Optical Fiber Communication”, 4th edition, MGH, 2008. 2. John M. Senior, "Optical fiber Communications", Peasrson Edun. 2nd Ed, 2004. References: 1. Govind P.Agarwal, Fiber Optic Communication Systems, 3rd Edn, John Wiley 1. Programming and Customizing the 8051 Microcontroller – Predko, TMH


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Model Question Paper

1. Define Numerical Aperture. Deduce the expression for Numerical Aperture of step index optical fiber.

2. Write a note on the number of modes available in step index fiber. 3. List out the advantages and limitations of optical fiber communication. 4. Write a note on photonic crystals. 5. Differentiate between intrinsic and extrinsic absorption. 6. Derive an expression for the pulse spread due to material dispersion using group

delay concept. 7. The input power to an optical fiber is 2 mw while the power measured at the

output end is 2 µw. If the fiber attenuation is 0.5 dB/Km, calculate the length of the fiber.

8. Write a note on inter modal and intra modal dispersion. 9. Explain in detail about Laser diodes with neat diagram. 10. With neat block diagram explain the structure of photo detectors. 11. Explain different types of fiber splicing techniques. 12. Derive the expression for power generated internally to the LED. 13. Discuss the different types of noise occurring in laser diodes. 14. A double hetero junction InGaAsP LED emitting at a peak wavelength of 1310

nm has radiative and nonradiative recombination times of 30 ns and 100 ns respectively. The drive current is 40 mA. What is the internal quantum efficiency.Also what is the power generated internally to the LED.

15. Discuss about the SONET/SDH rings, SONET/SDH networks. 16. Explain the scheme of multichannel amplitude modulation. 17. With a schematic diagram explain the working of optical receiver. 18. Discuss the various types of line codes used in optical fiber communication

systems. 19. Explain the significance of relative intensity noise.


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06EC-73

Power Electronics


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Power Electronics

Subject Code: 06 EC73 IA marks: 25 Hours per week: 04 Exam Hours: 03 Total Hrs: 52 Exam Marks: 100 PART-A Unit 1 Introduction, Power semiconductor devices, Applications of power electronics, Control characteristics, Types of power electronics circuits. 5 Hrs Unit 2 Power Transistor: Power BJT’s, Switching characteristics, Switching limits, Base derive control, Power MOSFET’s, Switching characteristics, Gate drive, IGBT’s, Isolation of gate and base drives. 7 Hrs Unit 3 Introduction to Thyristor: Thyristor and its control circuits, Modes of operation, Characteristics, Two transistor model, Dynomic characteristics, Thyrisrot gate characteristics, di / dt and dv / dt protection, Thyristor firing circuits. 7 Hrs Unit 4 CONTROL RECTIFIERS: Introduction, Principles of phase controlled converter operation, 1φ half controlled converters, 1φ fully controlled converters, Duel converters. 7 Hrs PART-B Unit 5 Commutation Technique: Introduction, Natural commutation, Forced communication, Self communication, Impulse communication, Resonant pulse communication and Complementary communication. 6 Hrs Unit 6 Ac Voltage Controllers: Introduction, Principles of on and off control, Principles of phase control, Single phase controllers with restive loads and Inductive loads. 6 Hrs Unit 7 Dc Choppers: Introduction, Principles of step down and step up choppers, Step down chopper with RL loads, Chopper classification, Analysis of impulse commutated, Thyristor chopper (only qualitative analysis). 6 Hrs Unit 8 Invertors: Introduction, Principles of operation, Performance parameters, 1φ bridge invertor, voltage control of 1φ invertors, current source invertors, Variable DC link inverter. 8 Hrs Text Books: 1) M.H. Rashid “Power electronics” 3rd edition, PHI / Pearson publisher 2004. 2) M.D. Singh and Kanchandani K.B. “Power electronics” TMH publisher, 2nd Edn. 2007. Reference Books: 1) G. K. Dubey S.R. Doradla, A. Joshi and Rmk Sinha “Thyristorized power controllers” New age international (P) ltd reprint 1999. 2. Jayanth Baliga, Modern Power Devices, John Wiely (?)


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LESSON PLAN Class: VII Semester Subject code: 06EC73 Subject: Power Electronics Hours/week: 05 Total No. of hours: 62

Hour No Topics To Be Covered

01 UNIT 1:Introduction

02 Applications of power electronics

03 Power semiconductor devices

04 Control characteristics

05 Types of power electronics circuits

06 Peripheral effects

UNIT-2 POWER TRANSISTOR

07 Power BJT’s,

08 Switching characteristics

09 Switching limits

10 Base drive control

11 Power MOSFET’s

12 Switching characteristics

13 Gate drive

14 IGBT’s

15 Isolation of gate and base drives

UNIT-3 INTRODUCTION TO THYRISTORS

16 Principle of operation states anode-cathode characteristics

17 Two transistor model.

18 Turn-on Methods

19 Dynamic Turn-on and turn-off characteristics

20 Gate characteristics,

21 Gate trigger circuits

22 di / dt and dv / dt protection

23 Thyristor firing circuits

24 Numerical problems

UNIT-4 CONTROLLED RECTIFIERS


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25 Introduction, Principles of phase controlled converter operation

26 1φ fully controlled converters

27 Duel converters

28 1 φ semi converters with R load

29 1 φ semi converters with R & RL load

30 Problems

UNIT-5

31 Thyristor turn off methods, natural and forced commutation

32 self commutation

33 class A and class B types

34 Complementary commutation

35 auxiliary commutation

36 external pulse commutation

37 AC line commutation


UNIT-6 AC VOLTAGE CONTROLLERS

39 Introduction

40 Principles of on and off control

41 Principles of phase control

42 Single phase controllers with restive loads


44 Single phase controllers with Inductive loads


UNIT-7 DC CHOPPERS

46 Introduction

47 Principles of step down

48 step up choppers

49 Step down chopper with RL loads

50 Chopper classification


52 Analysis of impulse commutated Thyristor chopper


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UNIT-8 INVERTORS

55 Introduction

56 Principles of operation of inverter

57 Performance parameters

58 1φ bridge inverter

59 Voltage control of 1φ invertors

60 Current source invertors

61 Variable DC link inverter



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Model Question paper

1) Briefly explain the different types of thyristor power converters &mention two applications of each. 2) Explain briefly types of power electronics circuits 3) Explain the important characteristic feature of power transistors. 4) With the aid of o/p& transfer characteristics discuss the different operating regions of power BJT. 5) Explain two transistor model with necessary equations. 6) Discuss the concept of Gate triggering& list the different gate triggering circuits. 7) Explain in 1φ fully controlled converters with necessary equations&waveforms. 8) Explain in detail with circuit diagram thyristor turn off methods, natural and forced commutation 9) What is commutation? Discuss various types of commutations. 10) Explain Principles of on and off control, Principles of phase control with neat circuit&wave forms. 11) Single phase controllers with Inductive loads 12) What is a DC chopper? 13) Define the term duty cycle in DC-DC converters 14) Analysis of impulse commutated Thyristor chopper 15) Define the term Inverter gain 16)Numerical problems


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06EC74

DSP Algorithms and Architecture


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DSP Algorithms and Architecture

Subject Code:06EC74 IA marks: 25 Hours per week: 04 Exam Hours: 03 Total Hrs: 52 Exam Marks: 100

PART-A Unit 1 Introduction to Digital Signal Processing: Introduction, A Digital Signal-Processing System, The Sampling Process, Discrete Time Sequences, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), Linear Time-Invariant Systems, Digital Filters, Decimation and Interpolation. 05 Hrs Unit 2 Architectures For Programmable Digital Signal-Processors: Introduction, Basic Architectural Features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation Unit, Programmability and Program Execution, Features for External Interfacing. 08 Hrs Unit 3 Programmable Digital Signal Processors: Introduction, Commercial Digital Signal processingDevices, Data Addressing Modes of TMS32OC54xx., Memory Space of TMS32OC54xx Processors, Program Control. 06 Hrs Unit 4 Detail Study of TMS320C54X: TMS32OC54xx Instructions and Programming, On- Chip peripherals, Interrupts of TMS32OC54XX Processors, Pipeline Operation of TMS32OC54xx Processor. 06 Hrs PART-B Unit 5 Implementation of Basic DSP Algorithms: Introduction, The Q-notation, FIR Filters, IIR Filters, Interpolation and Decimation Filters( one example in each case ). 06 Hrs Unit 6 Implementation oF FFT Algorithms: Introduction, An FFT Algorithm for DFT Computation, Overflow and Scaling, Bit-Reversed Index Generation & Implementation on the TMS32OC54xx. 06 Hrs Unit 7 Interfacing Memory and Parallel I/O Peripherals to DSP Devices: Introduction, Memory Space Organization, External Bus Interfacing Signals. Memory Interface, Parallel I/O Interface, Programmed I/O, Interrupts and I / O Direct Memory Access (DMA). 08 Hrs Unit 8 Interfacing And Applications of DSP Processor: Introduction, Synchronous Serial Interface, A CODEC Interface Circuit. DSP Based Bio-telemetry Receiver, A Speech Processing System, An Image Processing System. 06 Hrs Text Book: 1. Avatar Singh and S. Srinivasan, “Digital Signal Processing”, Thomson Learning, 2004 REFERENCE BOOKS: 2. Ifeachor E. C., Jervis B. W “Digital Signal Processing: A practical approach, Pearson-Education, 2002 1. B Venkataramani and M Bhaskar “Digital Signal Processors”, TMH, 2002


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LESSON PLAN

Class: VII Semester Subject code:06 EC74 Subject: DSP Algorithms and Architecture Hours/week: 04 Total No. of hours: 62

HOUR TOPIC 01 Unit 1 Introduction to Digital Signal Processing: Introduction

02 A Digital Signal-Processing System 03 The Sampling Process, Discrete Time Sequences 04 Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) 05 Linear Time-Invariant Systems, Digital Filters 06 Decimation and Interpolation

07 Unit 2Architectures For Programmable Digital Signal-Processors: Introduction

08 Basic Architectural Features 09 Basic Architectural Features-contn. 10 DSP Computational Building Blocks 11 Bus Architecture and Memory 13 Data Addressing Capabilities 13 Address Generation Unit 14 Programmability and Program Execution 15 Features for External Interfacing 16 Unit 3 Programmable Digital Signal Processors: Introduction 17 Commercial Digital Signal processing Devices 18 Commercial Digital Signal processing Devices-contn. 19 Data Addressing Modes of TMS32OC54xx. 20 Data Addressing Modes of TMS32OC54xx.-contn. 21 Memory Space of TMS32OC54xx Processors 22 Program Control 23 Unit 4 Detail Study of TMS320C54X- Introduction 24 TMS32OC54xx Instructions 25 TMS32OC54xx Instructions –contn. 26 Programming 27 Programming -contn 28 On-Chip peripherals 29 Interrupts of TMS32OC54XX Processors 30 Pipeline Operation of TMS32OC54xx Processor. 31 Unit 5Implementation of Basic DSP Algorithms: Introduction 32 The Q-notation 33 FIR Filters 34 FIR Filters-contn. 35 IIR Filters 36 IIR Filters –contn. 37 Interpolation and Decimation Filters( one example in each case ) 38 Unit 6Implementation oF FFT Algorithms: Introduction 39 An FFT Algorithm for DFT Computation 40 An FFT Algorithm for DFT Computation -contn


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HOUR TOPIC 41 Overflow and Scaling

42 Bit-Reversed Index Generation &Implementation on the TMS32OC54xx

43 Bit-Reversed Index Generation &Implementation on the TMS32OC54xx –contn.

44 Unit 7Interfacing Memory and Parallel I/O Peripherals to DSP Devices: Introduction

45 Memory Space Organization 46 External Bus Interfacing Signals

47 .Memory Interface 48 Parallel I/O Interface 49 Programmed I/O 50 Interrupts 51 I / O Direct Memory Access (DMA) 52 Unit 8Interfacing And Applications of DSP Processor: Introduction 53 Synchronous Serial Interface 54 Synchronous Serial Interface –contn. 55 A CODEC Interface Circuit 56 A CODEC Interface Circuit –contn. 57 DSP Based Bio-telemetry Receiver 58 DSP Based Bio-telemetry Receiver-contn. 59 A Speech Processing System 60 A Speech Processing System –contn. 61 An Image Processing System 62 An Image Processing System –contn.


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Model Question Paper

1. What are the DFT and IDFT equations? 2. What is the relationship between DFT and Frequency response of a sequence?

3. What is advantage of FFT in terms of computational savings?

4. Convolution, Z-Transform and System Function, o/p vs. i/p relationship of LTI

systems

5. Block Diagram of a digital filters, FIR and IIR comparisons

6. What is the function of Decimation filter?

7. What is the function of Interpolation filter?

8. What are the requirements of a programmable DSP device?

9. Unsigned (Braun) and signed multiplier (Baugh-Wooley) architecture

10. Barrel shifter architecture discussion

11. A MAC unit architecture, example. ALU unit details with block diagram

12. Von-Neumann Vs Harvard architecture under Bus Architecture

13. What is purpose of on-chip memory? How it is organized?

14. What are different data addressing capabilities of a programmable DSP and what are they meant for?

15. Name some of the commercially available Digital Signal-Processing Devices

16. What are the data addressing modes of TMS320C54xx Processors?

17. Explain with programs the addressing modes of the TMS320C54xx

18. What LD, RPT, PORTR, READA, WRITA, dmad, pmad instruction stands for?

(These are commonly used instructions in TMS320C54xx). Explain with program.

19. Explain with diagram Direct addressing mode of TMS320C54xx

20. Explain with diagram Indirect addressing mode of TMS320C54xx

21. Explain with diagram Circular addressing mode of TMS320C54xx

22. Discuss memory space of TMS320C54xx


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EC751

OPERATING SYSTEMS


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OPERATING SYSTEMS Subject Code: 06EC751 IA marks: 25 Hours per week: 04 Exam Hours: 03 Total Hrs: 52 Exam Marks: 100 PART A Unit 1 Introduction And Overview Of Operating Systems : Operating system, Goals of an O.S, Operation of an O.S, Resource allocation and related functions, User interface related functions, Classes of operating systems, O.S and the computer system, Batch processing system, Multi programming systems, Time sharing systems, Real time operating systems, distributed operating systems. (Chap 1: 1.1 – 1.5, Chap 2: 2.1 – 2.7) 06 Hrs Unit 2 Structure Of The Operating Systems: Operation of an O.S, Structure of the supervisor, Configuring and installing of the supervisor, Operating system with monolithic structure, layered design, Virtual machine operating systems, Kernel based operating systems, and Microkernel based operating systems. (Chap 3: 3.1 – 3.8) 06 Hrs Unit 3 Process Management: Process concept, Programmer view of processes, OS view of processes, Interacting processes, Threads, Processes in UNIX, Threads in Solaris. (Chap 4: 4.1 – 4. 7) 06Hrs Unit 4 Memory Management: Memory allocation to programs, Memory allocation preliminaries, Contiguous and noncontiguous allocation to programs, Memory allocation for program controlled data, kernel memory allocation. (Chap 5: 5.1 – 5.6) 06 Hrs PART B Unit 5 Virtual Memory: Virtual memory basics, Virtual memory using paging, Demand paging, Page replacement, Page replacement policies, Memory allocation to programs, Page sharing, UNIX virtual memory. (Chap 6: 6.1 – 6.7) 06 Hrs Unit 6 File Systems: File system and IOCS, Files and directories, Overview of I/O organization, Fundamental file organizations, Interface between file system and IOCS, Allocation of disk space, Implementing file access, UNIX file system. Text (Chap 7: 7.1 – 7.8) 06 Hrs Unit 7 Scheduling: Fundamentals of scheduling, Long-term scheduling, Medium and short term scheduling, Real time scheduling, Process scheduling in UNIX. (Chap 8: 8.1 – 8.5) 07 Hrs Unit 8 Message Passing: Implementing message passing, Mailboxes, Interprocess communication in UNIX) (Chap 9: 9.1 – 9. 3) 05 Hrs Text book: 1. D.M.Dhamdhare, “Operating Systems A Concept based Approach” ,TMH, 2nd Ed, 2006. Reference books 1. Silberschatz and Galvin, Operating Systems Concepts, John Wiley, 5th Edition 2002


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LESSON PLAN

Class: VII Semester Subject code: EC751 Subject: Operating Systems Hours/week: 04 Total No. of hours: 62

Hours Topics to be Covered UNIT 1: INTRODUCTION AND OVERVIEW OF OPERATINGSYSTEMS:

1 Operating system, Goals of an O.S 2 Operation of an O.S, 3 Resource allocation and related functions 4 User interface related functions, 5 Classes of operating systems 6 O.S and the computer system 7 Batch processing system, 8 Multi programming systems 9 Time sharing systems 10 Real time operating systems, distributed operating systems

UNIT 2: STRUCTURE OF THE OPERATING SYSTEMS 11 Operation of an O.S 12 Structure of the supervisor 13 Configuring and installing of the supervisor 14 Operating system with monolithic structure, 15 layered design 16 Virtual machine operating systems 17 ,Kernel based operating systems 18 Microkernel based operating systems

UNIT 3: PROCESS MANAGEMENT 19 Process concept 20 Programmer view of processes 21 OS view of processes 22 Interacting processes 23 Threads, Processes in UNIX 24 Threads in Solaris

UNIT 4: MEMORY MANAGEMENT 25 Memory allocation to programs, , , , 26 Memoryallocation preliminaries

27 Contiguous and noncontiguous allocation to programs

28 Memory allocation for program controlled data 29 kernel memory allocation.

30 Problems PART - B

UNIT 5: VIRTUAL MEMORY 31 Virtual memory basics 32 Virtual memory using paging 33 Demand paging 34 Page replacement


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Hours Topics to be Covered 35 Page replacement policies 36 Memory allocation to programs 37 Page sharing 38 UNIX virtual memory

UNIT 6: FILE SYSTEMS 39 File system and IOCS 40 Files and directories 41 Overview of I/O organization 42 Fundamental file organizations 43 Interface between file system and IOCS 44 Allocation of disk space 45 Implementing file access 46 Implementing file access 47 UNIX file system.

UNIT – 7 SCHEDULING 48 Introduction to scheduling 49 Fundamentals of scheduling 50 Long-term scheduling 51 Long-term scheduling 52 Medium scheduling 53 short term scheduling 54 Real time scheduling 55 Process scheduling in UNIX

UNIT – 8 MESSAGE PASSING 56 Introduction to Message Passing 57 Implementing message passing 58 Mailboxes 59 Mailboxes 60 Mails 61 Inter process 62 Communication in UNIX

Text book: 1. D.M.Dhamdhare, “Operating Systems A Concept based Approach” ,TMH, 2nd Ed, 2006. Reference books 1. Silberschatz and Galvin, Operating Systems Concepts, John Wiley, 5th Edition 2002


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1. a) what is OS ? List the task commonly performed by OS b) explain the typical computational structure and mention the OS responsibilities in each case 2.a) What do you mean by resource allocation differentiate partition based and pool based allocation approaches. b) What is virtual device &how spooling is used to improve utilization of I/O device? 3.a) How a multiprogramming system improves resource utilization. what architectures support is required for a multiprogramming system? How through put of the system can be improved by scheduling? (6) b) A program consists of a single loop which executes 50 times and contain a computation which consumes 50msec of CPU time, followed by an I/O operation which last for 200msec. A BP system uses a spooling. In this system each I/O operation of the program consume only 5msec. compute reduction in the CPU idle time due to spooling. ( 4) 4. Comment on validity of the following statement:A CPU bound program never has a high progress co-efficient in a multiprogramming system “. (10) 5. Explain how to configure and install the supervisor. (10)

6. What is process state? Explain various states of a process, giving state transition diagram. Explain data structure of a process control block (PCB).

How it is used in scheduling & context switching? (10)

7. a) Why is the separation of policy and mechanism a desirable principle? (5) b) Explain .bat file in MS.DOS and shells in UNIX.

8. Explain the following OS structure& also its advantages and disadvantages. (10) a) Monolithical structure b) Layered structure

9. Explain the following with example (10) Virtual machine OS Time-sharing system.

10.a) What is OS? Explain goals and resource allocation method w.r.t OS. (5) b) What is virtual device &how spooling is used to improve utilization of I/O device? (5) c) Explain the operation of os with example. (5) d) Explain system call in operating system. (5)

11.a) How a multiprogramming system improves resource utilization. what architectures support is required for a multiprogramming system? How through put of the system can be improved by scheduling? (8) b) A time-sharing system is to be designed to support a large number of user list all consideration, which influence the choice of the slice. Justify each consideration. (8)


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c) A program consists of a single loop which executes 50 times and contain a computation which consumes 50msec of CPU time, followed by an I/O operation which last for 200msec. A BP system uses a spooling. In this system each I/O operation of the program consume only 5msec. compute reduction in the CPU idle time due to spooling. (4)

12. a) Comment on validity of the following statement: “ A CPU bound program never has a high progress co-efficient in a multiprogramming system “. (10) b) Explain how to configure and install the supervisor. (10)

13. a) Explain the advantages and disadvantages of the following OS structure. (10) 1.Monolithical structure 2.Layered structure 3.Kernal-based structure 4.micro kernal-based structure

b) What is process state? Explain various states of a process, giving state transition diagram. Explain data structure of a process control block (PCB).

How it is used in scheduling & context switching? (10)

14. a) Why is the separation of policy and mechanism a desirable principle? (5) b) Describe the action taken by OS while creating a process. (5)


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06EC755

Image Processing


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Image Processing Subject Code: 06EC755 IA marks: 25 Hours per week: 04 Exam Hours: 03 Total Hrs: 52 Exam Marks: 100

PART A Unit 1 DIGITAL IMAGE FUNDAMENTALS: What is Digital Image Processing? fundamental Steps in Digital Image Processing, Components of an Image processing system, elements of Visual Perception. 06 Hrs Unit 2 Image Sensing and Acquisition, Image Sampling and Quantization, Some Basic Relationships between Pixels, Linear and Nonlinear Operations. 05 Hrs Unit 3 Image Transforms: Two-dimensional orthogonal & unitary transforms, properties of unitary transforms, two dimensional discrete Fourier transform. 06 Hrs Unit 4 Discrete cosine transform, sine transform, Hadamard transform, Haar transform, Slant transform, KL transform. 07 Hrs PART B Unit 5 Image Enhancement: Image Enhancement in Spatial domain, Some Basic Gray Level Transformations, Histogram Processing,, Enhancement Using Arithmetic/Logic Operations, Basics of Spatial Filtering. 06 Hrs Unit 6 Smoothing Spatial Filters, Sharpening Spatial Filters, Image enhancement in the Frequency Domain, Sharpening Frequency Domain Filters. IMAGE ESTORATION: A Model of the Image Degradation/Restoration Process, Noise Models, Restoration in the Presence of Noise, Only-Spatial Filtering. 06 Hrs Unit 7 Periodic Noise Reduction by Frequency Domain Filtering, Linear Position-Invariant Degradations, Estimating the Degradation Function. 07 Hrs Unit 8 Inverse Filtering, Minimum Mean Square Error (Wiener) filtering.Geometric Mean Filtering. COLOR IMAGE PROCESSING: Color Fundamentals. Color Models, Pseudo color Image Processing. 07 Hrs Text Book: 1. Rafael C.Gonzalez and Richard E.Woods, “Digital Image Processing”, Pearson Education, 2001, 2nd edition. Reference Books: 2. Anil K. Jain, “ Fundamentals of Digital Image Processing”, Pearson Education, 2001 3. B. Chanda and D. Dutta Majumdar, “Digital Image Processing and Analysis”, PHI,


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LESSON PLAN

Subject Code: 06EC755 IA marks: 25 Hours per week: 04 Exam Hours: 03 Total Hrs: 62 Exam Marks: 100

Sl. No. Topics

1 UNIT 1:DIGITAL IMAGE FUNDAMENTALS 2 Introduction 3 What is Digital Image Processing 4 Block diagram of DIP 5 Fundamental Steps in Digital Image Processing 6 Components of an Image processing system 7 Elements of Visual Perception 8 UNIT 2:Image Sensing 9 Acquisition 10 Quantization 11 Problems on no of bits required for storing digital data 12 Some Basic Relationships between Pixels 13 Linear Operations 14 Nonlinear Operations 15 UNIT 3:Two-dimensional orthogonal transforms 16 Unitary transforms 17 Properties of unitary transform 18 Properties of unitary transform 19 Two dimensional discrete Fourier transform 20 Two dimensional discrete Fourier transform 21 Examples ofUnitry& discrete Fourier transform 22 UNIT 4:Discrete cosine transform 23 Sine transform 24 Hadamard transform 25 Haar transform 26 Examples on Haar transform 27 Slant transform 28 KL transform 29 Revision 30 UNIT 5:IMAGE ENHANCEMENT: Introduction 31 Image Enhancement in Spatial domain 32 Some Basic Gray Level Trans -formations 33 Histogram Processing 34 Enhancement Using Arithmetic Operations 35 Enhancement Using Logic Operations 36 Revision 37 UNIT 6:Basics of Spatial Filtering 38 Image enhancement in the Frequency Domain filters 39 Smoothing Frequency Domain filters 40 Sharpening Frequency Domain filters 41 Examples on frequency domain filters 42 Homomorphic filtering 43 Homomorphic filtering


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Sl. No. Topics 44 UNIT 7:Model of image degradation 45 Degradation process 46 Restoration process 47 Introduction to noise& its effect 48 Noise models 49 Restoration in the Presence of Noise 50 Only-Spatial Filtering 51 Periodic Noise Reduction 52 Periodic Noise Reduction by Frequency Domain Filtering 53 Linear Position-Invariant Degradations 54 Inverse filtering 55 Minimum mean square error (Weiner) Filtering 56 UNIT 8:Introduction 57 Color Fundamentals 58 Color Models:RGB 59 HIS color model 60 Pseudo color Image Processing 61 Processing basics of full color image processing 62 Revision

Text Book: 1. Rafael C. Gonzalez and Richard E.Woods, “Digital Image Processing”, Pearson Education, 2001, 2nd edition. Reference Books: 2. Anil K. Jain, “Fundamentals of Digital Image Processing”, Pearson Education, 2001

3. B. Chanda and D. Dutta Majumdar, “Digital Image Processing and Analysis”, PHI,


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1) With a block diagram describe various components used in digital image processing. 2) Explain the role of sampling& quantization 3) Calculate the no of bits required to store digital image of size 1024*1024 pixels number of grey levels are128. 4) Explain any 2 methods for image zooming& shrinking 5) Histogram Processing 6) Explain briefly about image sampling. 7) State the properties of 2-D DFT 8) Explain Sharpening Frequency Domain filters 9) Explain what is meant by pseudo inverse filtering. 10) What is Pixel coding? Explain. 11) Explain the limitations of practical sampling and reconstruction systems. (8 marks) 12) What are image transforms &list them. 13) Explain briefly any 5 properties of two dimensional DFT.

14) (a) Explain how discrete cosine transform of an image can be computed using DFT. (b) Discuss the various point operations performed for image enhancement. 15) Explain the image restoration scheme using inverse filtering. What are its limitations? 16) Explain in detail the transform coding technique with neat block diagram. 17) Explain some Basic Gray Level Trans –formations? 18) Explain the basics of full color image processing? 19) Describe the elements of Visual Perception? 20) Develop a scheme for converting RGB to HSI & Vice versa with necessary equations. 21) Explain pseudo color image processing 22) Write a short note on intensity color slicing


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23) Describe the Basic Relationships between Pixels, Linear and Nonlinear Operations? 24) Explain the properties of unitary transform? 25) Basics of Spatial Filtering Image enhancement in the Frequency Domain filters? 26) Explain only-Spatial Filtering Periodic Noise Reduction by Frequency Domain Filtering 27) With relevant probability density function plots explain 1) Gaussian noise 2) Impulse Noise 28 a) Explain wiener filtering? b) Explain inverse filtering with necessary equations


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06EC762

REAL-TIME SYSTEMS


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REAL-TIME SYSTEMS

Subject Code : 06EC762 IA Marks : 25 No. of Lecture Hrs/Week : 04 Exam Hours : 03 Total no. of Lecture Hrs. : 52 Exam Marks : 100

PART - A UNIT - 1 INTRODUCTION TO REAL-TIME SYSTEMS: Historical background, RTS Definition, Classification of Real-time Systems, Time constraints, Classification of Programs. 6 Hours UNIT - 2 CONCEPTS OF COMPUTER CONTROL: Introduction, Sequence Control, Loop control, Supervisory control, Centralised computer control,Distributed system, Human-computer interface, Benefits of computer control systems. 6 Hours UNIT - 3 COMPUTER HARDWARE REQUIREMENTS FOR RTS: Introduction, General purpose computer, Single chip microcontroller, Specialized processors, Process-related Interfaces, Data transfer techniques, Communications, Standard Interface. 6 Hours UNIT - 4 LANGUAGES FOR REAL-TIME APPLICATIONS: Introduction, Syntax layout and readability, Declaration and Initialization of Variables and Constants, Modularity and Variables, Compilation, Data types, Control Structure, Exception Handling, Low-level facilities, Co routines, Interrupts and Device handling, Concurrency, Real-time support, Overview of real-time languages. 8 Hours

PART - B UNIT - 5 & 6 OPERATING SYSTEMS: Introduction, Real-time multi-tasking OS, Scheduling strategies, Priority Structures, Task management, Scheduler and real-time clock interrupt handles, Memory Management, Code sharing, Resource control, Task co-operation and communication, Mutual exclusion, Data transfer, Liveness, Minimum OS kernel, Examples. 12 Hours UNIT - 7 DESIGN OF RTSS – GENERAL INTRODUCTION: Introduction, Specification documentation, Preliminary design, Single-program approach, Foreground/background, Multi-tasking approach, Mutual exclusion, Monitors. 8 Hours UNIT - 8


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RTS DEVELOPMENT METHODOLOGIES: Introduction, Yourdon Methodology, equirement definition for Drying Oven, Ward and Mellor Method, Hately and Pirbhai Method. 6 Hours TEXT BOOKS: 1. Real - Time Computer Control- An Introduction, Stuart Bennet, 2nd Edn. Pearson Education. 2005. REFERENCE BOOKS: 1. Real-Time Systems Design and Analysis, Phillip. A. Laplante, second edition, PHI, 2005. 2. Real-Time Systems Development, Rob Williams, Elsevier. 2006. 3. Embedded Systems, Raj Kamal, Tata Mc Graw Hill, India, 2005.


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Lesson Plan

Subject Code : 06EC762 IA Marks : 25 No. of Lecture Hrs/Week : 04 Exam Hours : 03 Total no. of Lecture Hrs. : 62 Exam Marks : 100

Hours Topics to be Covered Unit 1

1 introduction to real-time systems 2 Historical background, RTS Definition 3 Classification of Real-time Systems 4 Time constraints 5 Classification of Programs

UNIT –2: 6 CONCEPTS OF COMPUTER CONTROL: Introduction ,Sequence Control 7 Loop control 8 Supervisory control 9 Centralized computer control

10 Distributed system 11 Human-computer interface 12 Benefits of computer control systems

UNIT –3:

13 COMPUTER HARDWARE REQUIREMENTS FOR RTS: Introduction, General purpose computer

14 Single chip microcontroller 15 Specialized processors 16 Process-related Interfaces 17 Data transfer techniques 18 Communications, Standard Interface

UNIT –4: 19 LANGUAGES FOR REAL-TIME APPLICATIONS: Introduction 20 Syntax layout and readability 21 Declaration and Initialization of Variables and Constants 22 Modularity and Variables 23 Compilation ,Data types 24 Control Structure 25 Exception Handling, 26 Low-level facilities, Co routines 27 Interrupts and Device handling, Concurrency 28 Real-time support 29 Overview of real-time languages

PART B UNIT –5 & 6 30 OPERATING SYSTEMS: Introduction 31 Real-time multi-tasking OS 32 Real-time multi-tasking OS 33 Scheduling strategies 34 Priority Structures 35 Task management 36 Scheduler and real-time clock interrupt handles 37 Memory Management


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Hours Topics to be Covered 38 Memory Management 39 Code sharing, Resource control 40 Task co-operation and communication 41 Mutual exclusion, Data transfer 42 Liveness 43 Minimum OS kernel 44 Examples

UNIT 7 45 DESIGN OF RTSS – GENERAL INTRODUCTION: Introduction 46 Specification documentation 47 Preliminary design 48 Single-program approach 49 Foreground/background 50 Foreground/background 51 Multi-tasking approach 52 Mutual exclusion 53 Mutual exclusion 54 Monitors

UNIT 8 55 RTS DEVELOPMENT METHODOLOGIES: Introduction 56 Yourdon Methodology 57 Yourdon Methodology 58 requirement definition for Drying Oven 59 requirement definition for Drying Oven 60 Ward and Mellor Method 61 Ward and Mellor Method 62 Hately and Pirbhai Method


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06ECL77

VLSI Lab


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Subject Code : 06ECL77 IA Marks : 25 No. of Practical Hrs/Week : 03 Exam Hours : 03 Total no. of Practical Hrs. : 42 Exam Marks : 50

PART – A

DIGITAL DESIGN

ASIC-DIGITAL DESIGN FLOW 1. Write Verilog Code for the following circuits and their Test Bench for verification, observe the waveform and synthesise the code with technological library with given Constraints*. Do the initial timing verification with gate level simulation. i. An inverter ii. A Buffer iii. Transmission Gate iv. Basic/universal gates v. Flip flop -RS, D, JK, MS, T vi. Serial & Parallel adder vii. 4-bit counter [Synchronous and Asynchronous counter] viii. Successive approximation register [SAR] * An appropriate constraint should be given PART - B ANALOG DESIGN Analog Design Flow 1. Design an Inverter with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design e. Verify & Optimize for Time, Power and Area to the given constraint*** 2. Design the following circuits with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design. i) A Single Stage differential amplifier ii) Common source and Common Drain amplifier 3. Design an op-amp with given specification* using given differential amplifier Common source and Common Drain amplifier in library** and completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis


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ii). AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design. 4. Design a 4 bit R-2R based DAC for the given specification and completing the design flow mentioned using given op-amp in the library**. a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design. 5. For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and verify the functionality by completing ASIC Design FLOW.

[Specifications to GDS-II]

•••• Appropriate specification should be given.

** Applicable Library should be added & information should be given to the Designer. *** An appropriate constraint should be given


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06ECL 78

Power Electronics Lab


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Subject Code: 06ECL78 IA marks: 25 Hours per week: 03 Exam Hours: 03 Total Hrs: 42 Exam Marks: 50

1) Static characteristics of SCR and DIAC. 2) Static characteristics of MOSFET and IGBT. 3) Controlled HWR and FWR using RC triggering circuit 4) SCR turn off using i) LC circuit ii) Auxiliary Commutation 5) Synchronized UJT firing circuit for HWR and FWR circuits. 6) Generation of firing signals for thyristors/ trials using digital circuits / microprocessor. 7) AC voltage controller using triac – diac combination. 8) Single phase Fully Controlled Bridge Converter with R and R-L loads. 9) Voltage (Impulse) commutated chopper both constant frequency and variable frequency operations. 10) Speed control of a separately exited DC motor. 11) Speed control of universal motor. 12) Speed control of stepper motor. 13) Parallel / series inverter.


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06ec-71 computer communication networks - … computer communication networks electronics &...

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