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CMOS IMPLEMENTATION OF

LOW POWER LOW VOLTAGEFULL ADDERS

PRESENTED BY

T. NOOR SUBANI

08MU1A0455

UNDER THE GUIDENCE OF

Mr.T.PRASAD,M.EAssociate professor 

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CONTENTS

Objective

Introduction

Tools used

Full adder 

28T CMOS adder 

Serf adder 

 Adder 13A

Results

Conclusion

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OBJECTIVE

We proposed a technique to build a 10T full adders i.e

SERF adder and novel XOR, XNOR gates with the

consistently consume an average power and have higher 

speed compared with conventional 28T CMOS adder.

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Cont…

The adder is one of the most critical components of a

processor, as it is used in the Automatic logic unit (ALU),

in the floating-point unit, and for address generation in

case of catch or memory access .

The full adder performance would affect the system as a

whole.

The conventional adder uses 28 transistors implemented

in CMOS technique.

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Cont…

A new full adder called static energy-recovery full-adder 

(SERF) uses only 10 transistors, which has the least

number of transistors and has reported to be the best in

power consumption.

Compared to the complementary static CMOSadders,

such low-power adders have the problem of threshold

loss.

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TOOLS USED

The tool used to implement this full adders is

tanner(TSPICE).

SPICE is program that simulates electronic circuits on

our PC. We can view any voltage or current waveform in

our circuit.

SPICE calculates these voltages and currents versustime (Transient Analysis) or versus frequency (AC

  Analysis). Most SPICE programs also perform other 

analysis like DC, Sensitivity, Noise and Distortion.

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FULL ADDER 

A full adder performs the addition of two bits A and B with

the Carry(Cin) bit generated in the previous stage. The

integer of this relations shown by

Sum=A XOR B XOR Cin

 COUT=AB + BCin + Cin A

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Cont…

A B CIN SUM COUT

0 0 0 0 0

0 0 1 1 00 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

TABLE: TRUTH

TABLE

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DESIGN AND IMPLEMENTATION

28 transistor full adder:

 A B

B

 A

C i 

C i  A

 X 

V DD

V DD

 A B

C i  B A

B V DD

 A

B

C i 

C i 

 A

B

 A C i B

C o

V DD

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FOUR BIT 28 T FULL ADDER 

Power results:

 Average power consumed -> 1.128593e-003

watts

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SIMULATION RESULTS

Inputs: a0=11,a1=01, a2=11,a3=00

b0=01,b1=00 ,b2=10, b3=01,Cin=00

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SERF ADDER 

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FOUR BIT SERF ADDER 

Power results:

 Average power consumed -> 6.141519e-004 watts

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SIMULATION RESULTS

Inputs: a0=10,a1=01,a2=11,a3=01

b0=11,b1=11,b2=01,b3=01,cin=00

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NOVEL XOR AND XNOR 

GATES

Block diagram of a novel xor and xnor:

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SIMULATION RESULTS

Inputs :a0=11,a1=01,a2=10,a3=10

b0=10,b1=00,b2=01,b3=00,cin=00

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ADVANTAGES

Complexity is low.

10% Low power consumption and

90% higher speed compared to the previous adder.

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RESULTS

ADDERNAME

POWER DELAY AREA

Mirror 5.16watts 1.05sec 112

CMOS 4.21watts 1.28sec 112

Serf 1.91watts 0.43sec 40

13A 1.23watts 0.30sec 40

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CONCLUSION

In this work we have complemented different adders and

compared their power consumptions with SERF adder.

  And we have presented a systematic approach to

construct full adders only 10 transistors.

We conclude that 3 new adders consume on average

10% less power and have 90% high speed compared to

the previous 10 transistors adder.

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REFERENCES

• J. Wang, S. Fang, and W. Feng, “New efficient

designs for XOR and XNOR functions on the

transistor level,” IEEE J. Solid-State Circuits,

• R. Shalem, E. John, and L. K. John, “A novel low

power energy recovery full adder cell,” in Proc. IEEE

Great Lakes VLSI Symp.,

• www.ECIRCUIT CENTER.com

• WWW.SCRIBD.COM

• WWW.VLSIBANK.COM

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THANK YOU