08/31/2001copyright cecs & the spark project center for embedded computer systems university of...
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08/31/2001Copyright CECS & The Spark Project
Center for Embedded Computer SystemsUniversity of California, Irvine
http://www.cecs.uci.edu/~spark
Conditional Speculation and its Effects on Performance and Area for High-Level Synthesis
Sumit Gupta Nikil DuttNick Savoiu Rajesh Gupta
Alex Nicolau
SPARK High Level Synthesis System
Supported by Semiconductor Research Corporation
2Copyright CECS & The Spark Project
High Level Synthesis
From C to CDFG to Architecture
3Copyright CECS & The Spark Project
Scheduling with Given Resource Allocation
Resource Constraints + <
4Copyright CECS & The Spark Project
Conditional Speculation
+ +
-
<
Resource Constraints + <
ConditionallySpeculate
Unused/idle resource slots
5Copyright CECS & The Spark Project
Conditional Speculation
+ +-
<
Resource Constraints + <
-
Higher resource utilization inside conditionals
Shorter schedule lengths
6Copyright CECS & The Spark Project
Creation of idle slots by Speculation
- +
-
<
BB 1 BB 2
BB 3
BB 0
x y
a a
z
Speculate
7Copyright CECS & The Spark Project
After Speculation
- +
-
<
BB 1 BB 2
BB 3
BB 0x y
a a
z
a = b a = c
b c
ConditionallySpeculate
8Copyright CECS & The Spark Project
After Conditional Speculation
- +<
BB 1 BB 2
BB 3
BB 0x y
a = b a = c
b c
- -
b c
z1 z2
9Copyright CECS & The Spark Project
Generalized Code Motions
+
+
+
If Node
T F
Conditional Speculation
Reverse SpeculationSpeculation
Across HierarchicalBlocks
10Copyright CECS & The Spark Project
Recent Related WorkCode motions in the presence of conditionals
Condition Vector List Scheduling [Wakabayashi 89] Symbolic Scheduling [Radivojevic 96] WaveSched Scheduler [Lakshminarayana 98] Basic Block Control Graph Scheduling [Santos 99]
Limitations Arbitrary nesting of conditionals and loops not
handled or handled poorly Ad hoc optimizations
Not part of a complete synthesis system Limited analysis of logic and control costs
11Copyright CECS & The Spark Project
The Spark High-Level Synthesis Methodology
Developed a set of speculative code motions along with supporting transformations
Implemented in a comprehensive synthesis framework Input: Behavioral description in ANSI-C Output: Synthesizable register-transfer level VHDL
Quality of results measured in terms of Scheduling results: cycles in longest path Controller size: number of states in FSM Logic synthesis results: critical path length,unit area
12Copyright CECS & The Spark Project
The Spark High-Level Synthesis Framework
Experiments performed using two benchmarks: ADPCM Encode and MPEG-1 Prediction Block
13Copyright CECS & The Spark Project
Improvements of up to 50 % in Number of States in FSM and Cycles on Longest Path due to Code Motions
0
0.5
1
1.5
2
Num
ber o
f Sta
tes
(Nor
mal
ized
)
ADPCMEncode
MPEGcalc_forw
MPEG pred2
Effects of Speculative Code Motions on Size of Controller (Number of FSM States)
0
0.5
1
1.5
2
Cycl
es o
n Lo
nges
t Pat
h(N
orm
aliz
ed)
ADPCMEncode
MPEGcalc_forw
MPEG pred2
Effects of Speculative Code Motions on Longest Path Cycles (Performance)
Within Basic BlocksWithin BBs, Across Hierarchical BlocksWithin BBs, Across Hier Blocks, SpeculationWithin BBs, Across Hier Blocks, Spec, Early Condition ExecutionWithin BBs, Across Hier Blocks, Spec, Early Cond Exec, Conditional Speculation
Allowed Code MotionsConditional Speculation: Leads to between 10 to 30 % Improvements
14Copyright CECS & The Spark Project
Synthesis Results usingSynopsys Design Compiler
0
0.2
0.4
0.6
0.8
1
1.2
Nor
mal
ized
CriticalPath (c ns)
LongestPath
(l cycles)
Delay(c*l ns)
Unit Area
Synthesis Results for the MPEG Pred2 function using LSI-10K Synthesis Library
Within Basic BlocksWithin BBs, Across Hierarchical Blocks, SpeculationWithin BBs, Across Hier Blocks, Spec, Early Condition ExecutionWithin BBs, Across Hier Blocks, Spec, Early Cond Exec, Conditional Speculation
Allowed Code Motions
0
0.2
0.4
0.6
0.8
1
1.2
Nor
mal
ized
CriticalPath (c ns)
LongestPath
(l cycles)
Delay(c*l ns)
Unit Area
Synthesis Results for the ADPCM Encoder function using LSI-10K Synthesis Library
Conditional Speculation leads to Reduced circuit delays: between 7 to 35 % Increased Area: between 4 to 8 %
Area figures are high in absolute terms
15Copyright CECS & The Spark Project
Increasing sizes of steering logic and associated control logic
Code motions lead to Higher Resource Sharing and Utilization Larger Multiplexors Larger Control Circuits
ControlLogic
ALU+ +
16Copyright CECS & The Spark Project
Increasing sizes of steering logic and associated control logic
ControlLogic
ALU+ ++
Code motions lead to Higher Resource Sharing and Utilization Larger Multiplexors Larger Control Circuits
17Copyright CECS & The Spark Project
Increasing sizes of steering logic and associated control logic
ControlLogic
ALU+ ++ +
Code motions lead to Higher Resource Sharing and Utilization Larger Multiplexors Larger Control Circuits
18Copyright CECS & The Spark Project
Interconnect minimization by resource binding
Minimize the complexity of steering logic Multiplexors and demultiplexors
Bind operations with same inputs or outputs to same functional units
Bind variables, which are inputs/outputs to same functional units, to the same registers
Both of these binding problems have been formulated as network flow problems
19Copyright CECS & The Spark Project
Reduction in Area by Interconnect Minimizing Resource Binding
0
0.5
1
Norma
lized
MPEG Pred2 function synthesized using LS I -10K Library
Critical Path
TotalDelay
Unit Area
0
0.5
1
Norma
lized
ADPCM Encoder function synthesized using LS I -10K Library
Critical Path
TotalDelay
Unit Area
Naïve Resource Binding
Interconnect Minimizing Resource Binding
Reductions in area of between 15-32 % Fairly constant critical path lengths and
circuit delay
20Copyright CECS & The Spark Project
ConclusionsSynthesis results after code motions
Considerable gain in execution cycles and controller size Large Area costs due to interconnect (multiplexors)
Interconnect minimizing resource binding leads to significant area reductions
Benchmarks used are large real-life applications
Future Work:Develop better cost models for code motions
Consider effects on interconnect while scheduling Create a notion of global cost of the design
21Copyright CECS & The Spark Project
Thank you !
Please do drop by during the Poster session
08/31/2001Copyright CECS & The Spark Project
Center for Embedded Computer SystemsUniversity of California, Irvine
http://www.cecs.uci.edu/~spark
Conditional Speculation and its Effects on Performance and Area for High-Level Synthesis
Sumit Gupta Nikil DuttNick Savoiu Rajesh Gupta
Alex Nicolau
SPARK High Level Synthesis System
Supported by Semiconductor Research Corporation
23Copyright CECS & The Spark Project
Additional Slides
24Copyright CECS & The Spark Project
Reducing Interconnections by Improved Operation Binding
1:a=b+c
ALU 1
2:d=e+f
ALU 2
4:h=a+c3:g=e+d
b,d,h f,a,gc e
3:g=e+d; 4:h=a+c
1:a=b+c; 2:d=e+f
25Copyright CECS & The Spark Project
Reduced Interconnections after Operation Binding
1:a=b+c
ALU 1
2:d=e+f
ALU 2
4:h=a+c 3:g=e+d
b,d,g f,a,hc e
26Copyright CECS & The Spark Project
Reducing Interconnections by Improved Variable Binding
1:a=b+c
ALU 1
2:d=e+f
ALU 2
4:h=a+c 3:g=e+d
b,d,g f,a,hc e
27Copyright CECS & The Spark Project
Reduced Interconnections due to Improved Resource Binding
1:a=b+c
ALU 1
2:d=e+f
ALU 2
4:h=a+c 3:g=e+d
b,a,h f,d,gc e
28Copyright CECS & The Spark Project
Improvements of up to 50 % in Number of States in FSM and Cycles on Longest Path due to Code Motions
0
0.5
1
1.5
2
Num
ber o
f Sta
tes
(Nor
mal
ized
)
ADPCMEncode
MPEGcalc_forw
MPEG pred2
Effects of Speculative Code Motions on Size of Controller (Number of FSM States)
0
0.5
1
1.5
2
Cycl
es o
n Lo
nges
t Pat
h(N
orm
aliz
ed)
ADPCMEncode
MPEGcalc_forw
MPEG pred2
Effects of Speculative Code Motions on Longest Path Cycles (Performance)
Within Basic BlocksWithin BBs, Across Hierarchical BlocksWithin BBs, Across Hier Blocks, SpeculationWithin BBs, Across Hier Blocks, Spec, Early Condition ExecutionWithin BBs, Across Hier Blocks, Spec, Early Cond Exec, Conditional Speculation
Allowed Code Motions
29Copyright CECS & The Spark Project
Synthesis Results usingSynopsys Design Compiler
0
0.2
0.4
0.6
0.8
1
1.2
Nor
mal
ized
CriticalPath (c ns)
LongestPath
(l cycles)
Delay(c*l ns)
Unit Area
Synthesis Results for the MPEG Pred2 function using LSI-10K Synthesis Library
Within Basic BlocksWithin BBs, Across Hierarchical Blocks, SpeculationWithin BBs, Across Hier Blocks, Spec, Early Condition ExecutionWithin BBs, Across Hier Blocks, Spec, Early Cond Exec, Conditional Speculation
Allowed Code Motions
0
0.2
0.4
0.6
0.8
1
1.2
Nor
mal
ized
CriticalPath (c ns)
LongestPath
(l cycles)
Delay(c*l ns)
Unit Area
Synthesis Results for the ADPCM Encoder function using LSI-10K Synthesis Library