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21

Analog Applications Journal

Texas Instruments Incorporated Power Management

4Q 2003 www.ti.com/sc/analogapps Analog and Mixed-Signal Products

UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 2

IntroductionPower factor corrected (PFC) preregulators are generallyused in offline ac/dc power converters with a power levelhigher than 75 W or to meet line harmonic requirementssuch as EN61000-3-2. PFC is typically done with a boostconverter ac/dc topology due to the continuous input current that can be manipulated through average current-mode control to achieve a near-unity power factor (PF).However, due to the high output voltage of a boost con-verter, a second dc/dc converter is generally needed tostep down the output to a usable voltage. In the past thishas been accomplished with two pulse-width modulators(PWMs). One PWM controlled and regulated the PFC

power stage, while the second was used to control thestep-down converter. The UCC28517 controller reducesthe need for two PWMs and combines both of these func-tions into one control-integrated circuit. The UCC28517operates the second converter at twice the switching frequency of the PFC stage, which reduces the size of the boost magnetics and the ripple current in the boost capacitor. For more information on this device, please seeReference 7. This article reviews the design of the second12-V, 8-W power stage to be used as an auxiliary bias supply. A review of the PFC preregulator power stage can be found in the 3Q03 issue of the TI AnalogApplications Journal.

By Michael OLoughlin (Email: [email protected])Member, Applications Engineering Staff

t Soft-start interval1 Output A efficiency2 Output B efficiencyCDIODE Boost diode capacitanceCOSS FET drain-to-source capacitanceDmax Duty cycle maximumESR Output capacitance equivalent resistancefc Voltage-loop crossover frequencyfopto_pole Frequency where optoisolator gain is 3 dB from its dc

operating pointfS Minimum switching frequencyfSA Output A switching frequencyfSB Output B switching frequencyGc(s) Control transfer functionGco(s) Control to output transfer functionGopto(s) Optoisolator gain transfer functionH(s) Voltage divider gainIm Transformer magnetizing currentIop_min Minimum optocoupler current (1 mA)IPK Peak inductor current, peak diode current, peak

switch currentIRMS RMS device currentISS UCC28517 soft-start current of 10 ALm Transformer primary magnetizing inductanceN Transformer turns ratioNp Primary turnsNs Secondary turnsPCOND Device conduction lossesPCOSS Power dissipated by the FETs drain-to-source

capacitancePDIODE Total loss in the boost diode

PDIODE_CAP Loss due to boost diode capacitancePFET_TR FET transition lossesPGATE Power dissipated by the FET gatePOUTA Output A maximum powerPOUTB Output B maximum powerQGATE FET gate chargeRDS(on) On resistance of the FETRload Typical load impedanceRSENSE Current sense resistors Angular frequency (j2f)tblank Amount of leading-edge blanking timetf FET fall timetr FET rise timeTSB 1/fSB = 5 sTs(f) Voltage loop frequency responseVboost Same as VOUTAVc Control voltageVct Oscillator peak (5 V)Vd Forward diode drop (0.6 V)Vdynamic Current sense voltage rangeVf Forward voltage of a diodeVGATE Gate-drive voltageVIN RMS input voltageVOUTA Boost output voltage (Vboost)VOUTB Auxiliary output voltageVpp Output peak-to-peak ripple voltageVREF UCC28517 internal referenceVripple Output B ripple voltageVslope Voltage ramp peak added for slope compensationVVERR Feedback error voltageVVREF_TL431 TL431 (D13) internal reference

Variable definitions

Texas Instruments IncorporatedPower Management

22

Analog Applications JournalAnalog and Mixed-Signal Products www.ti.com/sc/analogapps 4Q 2003

The following design example was generated using typi-cal parameters rather than worst-case values. Please referto Table 1 and Figures 13 for design specifications andcomponent placement. All variables are defined in thesidebar on page 21.

12-V, 8-W auxiliary converter (OUTB)Due to the high input voltage from the boost converter, thisdesign required a dc/dc converter with a step-down trans-former to achieve the desired output voltage of 12 V. Thelow power requirements permitted use of a discontinuous-mode flyback topology, which uses fewer components thana standard forward converter.

Transformer turns ratioThe following equation can be used to calculate the trans-former turns ratio (N) needed for this power stage.

The UCC28517 PWM/PFC controller has a user-selectableduty-cycle clamp. For this design the duty-cycle clamp wasset to a Dmax of 0.55. The UCC28517 has a forward enablecomparator that will not allow the forward converter tooperate with a boost voltage less than 50% of the nominalvalue. This allows the cascaded step-down converter to

ND V T

D V V TOUTA SB

OUTB d SB=

+ max

max( . ) ( )0 9

+

OUTA

OUTA+P1

P2

C3100 F

C20.47 F

R20

22.1 k

R33

562 k

R15

3.92 k

1

R18

392 kR24

392 k

Q1IRFP450

HFA08TB60

D3

TP11

D1

G1756

L11.7 mH

R41

47

R14

1.5 k

R29

10.0 k TP2

TP1

F1

VIN

AC_L

AC_N

D11PB66

C2647 nF

1

2

3

4

+

R5

0.33

R22

562 k

R44

47 TP12

PKLMT

IAC

VR

EF 1 2 54

Figure 1. PFC power stage schematic

MAXIMUM TYPICAL MINIMUMVIN 265 Vrms 85 VrmsOutput A (VOUTA) 410 V 390 V 370 VOutput B (VOUTB) 12.6 V 12 V 11.4 VOutput A efficiency (1) 85%Output B efficiency (2) 50%POUTA 100 W 10 WPOUTB 8 W 4 WOutput ripple A (Vpp) 12 VOutput ripple B (Vripple) 750 mVOutput A THD (% THD) 10%PF 1Output A switching frequency (fSA) 100 kHzOutput B switching frequency (fSB) 200 kHz

Table 1. Design specifications


23

Analog Applications Journal 4Q 2003 www.ti.com/sc/analogapps Analog and Mixed-Signal Products

TP7

TP9TP8 TP6

C11 F

C30100 F

R31

47

R26

100 kR36

200 k

D14R16

680 k

R351 k

C153.3 nF

C14150 nF

R32

38.3 k

R27

10 k

R410 k

R9

82 k

R39

10 k

R144.2 k

R43

10 k

D15

GND

3

1 24

R3

82 k

T1PB2039

C1247 F

C9100 F

OUTB

OUTA

OUTB+

OUTA+

C292.2 F

P4

P1

R2 10 k

P2

+

D8

P32

1

2

1

6

5Q2

D5

Q3

4

1

2

3

7

9

10

C38100 pF

R13

2 k

VREF

VERR

6

Note: Star groundingtechnique must be used

7

VCC

U25

6

4 2

1

GND2

D1314

2

3

Figure 2. dc/dc power stage schematic

Q4

VERR

VREF

1 2 4 5

76

C271 F

C231.5 F

C282.2 F

C25150 nF

C10330 pF

PWRGND

GT1

SS2

PKLMT

CAOUT

ISENSE1

MOUT

IAC

VFF

VREF

GT2

VCC

ISENSE2

VERR

GND

CT

VSCLAMP

VSENSE

RT

VAOUT

1TP4

1

TP5

1

1

R34

1.18 kR28

48.7 k

R21

1 k

R30

30.1 k

U1

R19

3.92 k

R6

10

D10 D9

R17

7.5 k

R7

10

R11

1 k

R8

9.09 k

R42

100

R40

1 k

R10

10

R25133 k

UCC28517DW

C22390 pF

C192.2 nF

TP3

11

12

13

14

15

16

17

18

19

20

10

9

8

7

6

5

4

3

2

1

D_CLAMP

D_CLAMP

GT2

GT2

VCC

C24100 pF

1IAC

C24100 pF

1IAC

C1610 nF

C647 F

C180.1 F

C17100 pF

C1356 pF

1

1

TP10

1

D12

1

PKLMTD16

1

Figure 3. Controller schematic


24


operate during loss of line voltage. An auxiliary winding of22 turns was added to power the UCC28517 control IC aswell. For this design Pulse Engineering designed a 22-turntransformer (part number PB2039).

Power switch (Q2) and output diode (D8) selectionTo select D8 and Q2 properly, a power budget is generallyset for these devices to maintain the desired efficiencygoal. The following equations were used to estimate powerloss in the switching devices. To meet the power budgetfor this design, an IRFBF20S FET and a 20CJQ045 dualdiode from International Rectifier were chosen.

Output capacitorThe output capacitor selection for the step-down converterwas based on requirements for energy storage, output ripplevoltage, RMS current, and peak current.

P P PDIODE COND D DIODE CAP D= +_ _ _8 8

I ID

RMS D PK D_ _max

8 8

1

3=

P V ICOND D f RMS D_ _8 8=

PC

V fDIODE CAP DDIODE

OUTB SB_ _ 82

2=

ID

VPK D OUTB_

max( )8

2 1=

POUTB

P P P P PQ GATE Q COSS Q COND FET FET TR Q2 2 2 2= + + +_ _ _ _ _

P V I t t fFET TR Q OUTB RMS Q r f SB_ _ _ ( )2 21

2= +

P C V fCOSS Q OSS Q OUTB S_ _2 221

2=

P Q V fGATE Q GATE GATE S_ 2 =

P R ICOND FET Q DS on RMS FET_ _ ( ) _22

=

IRMS FET Q_ _ 2 =

P

2 N

D

3OUTB max

I

PV

NPK Q

OUTB

OUTB_ 2

2

2=

RSENSE2The dc/dc power converter is designed for peak-current-mode control. R4 is the current sense resistor, which canbe sized through the following two equations.

Soft startThe UCC28517 has soft-start circuitry to allow for a con-trolled ramp of the second stages duty cycle during startup.The following equation was used to calculate the approxi-mate capacitance needed to achieve a soft start of roughly5 ms (t).

Slope compensationDesigning a power converter that uses peak-current-modecontrol generally requires slope compensation to removeinstabilities in the control loop and to make the design lesssusceptible to noise. Resistors R11 and R8 (Figure 3) sumin a portion of the oscillator signal to the current sensesignal for slope compensation. Generally the added slope(Vslope) required is equal to half the down slope of thechange in output current. By selecting R11 first, you cancalculate the required value of R8 to generate the requiredslope compensation.

RR V V

Vct slope

slope

811

( )

VI

NRslope

PK C= +

Im

_ 30

24

C16I t

5 VSS

=

RV

I

N

dynamic

PK C4

30=

+Im_

Immax

=

V D

L fOUTA

m SB

I I DD

RMS C PK C_ _ maxmax( )

( )30 30 1

4 3 1

12=

CI D

f VPK

SB OUTB

300 5 1

. ( )max

ESRV

ICripple

PK C30

30_ max

_

I

P

V

DPK C

OUTB

OUTB_

max30 2 1=


25


Leading-edge blanking circuitThe typical current sense signal for aconverter using peak-current-modecontrol is shown in Figure 4. As shown,during time T1 there is a leading cur-rent spike. This is partly caused by theparasitic gate-to-source capacitance ofthe power stage switch Q4 and thevoltage divider formed off the gatedrive by R4 and R7. This leading-edgespike can cause the peak-current-mode signal to terminate the gatedrive prematurely. To remove thisinstability, a leading-edge blanking circuit was constructed.

Electronic components Q4, R40,R42, and C10 form a leading-edgeblanking circuit. This circuit is used to clamp leading-edge current spikes.The timing of the leading-edge blank-ing can be adjusted by modifying thesize of timing capacitor C10:

Control loop for the dc/dc converterFigure 5 shows the control block dia-gram for the control loop of the dc/dcconverter. Gc(s) is the compensationnetworks transfer function (TF), Gopto(s) is the optoisolatorgain TF, Gco(s) is the control-to-output gain TF, and H(s) isthe divider gain TF. To estimate the frequency response ofeach gain block, the following equations can be used.fopto_pole is the frequency where the optoisolator gain is 3 dB from its dc operating point; and VVREF_TL431 is theinternal reference voltage of the TL431 shunt regulator.Rload represents the typical load impedance for the design.

GV

V

R

R4

N

N

1 s C30 ESR

1 s C30 Rco(s)OUTB

c

load p

s load

= = +

+

Gs R C

s C R s R C

R

R sf

c s

opt

( ) ( )=

+

+

+

35 14 1

14 31 1 35 15

13

36

1

12 oo pole_

GR

R sf

opto s

opto pole

( )

_

= +

13

36

1

12

HR27

R27 R32

V

V(s)VREF_TL431

OUTB

=

+=

Ct

R Rblank10

2 40 42=

+( )

Figure 6 shows the circuitry that was used for the voltagefeedback loop. D13 is a TL431 shunt regulator that canfunction as an operational amplifier to provide feedbackcontrol when set up in this configuration.

T1

Figure 4. Typical current sense signal

Gc(s) Gco(s)VVREF_TL431

H(s)

V(V )

OUTA

boost

VOUTB+

Vc

Figure 5. dc/dc converter control loop

H11AV1

VREF

R13

U3

PGND2

D14R36

R16

C14

R35

R27

D13TL431

R32

VOUTBV = Vc VERRGco(s)

V(V )

OUTA

boost

C153

2

1

4

5

6

Figure 6. Voltage feedback loop


26


Initially the resistor values for the divider gain, H(s), mustbe selected. The following equation can be used to sizethese resistors, where VOUTB is the desired output voltageand VVREF_TL431 is the internal reference of the TL431.

It is important to bias the TL431 and the optoisolatorcorrectly for proper operation. Resistors R16 and R13 provide the minimum bias currents for the TL431 and theoptoisolator, respectively, and can be selected with the following equations. The optoisolator was configured tohave a dc gain of roughly 20 dB, and the optoisolator hada crossover frequency of roughly 80 kHz. Figure 7 showsthe small signal frequency response of the optoisolator.

Before attempting to compensate the control loop, Ts(f),we must define some design goals for the closed-loop frequency response. Typically the loop is designed to cross over at a frequency below one-sixth of the switchingfrequency (see Reference 3). For this design example tohave good transient response, the design goal was to havethe loop gain crossover frequency (fc) at roughly 1 kHz,which is less than one-sixth of the switching frequency(fSB). The following equation describes the frequencyresponse of the system loop gain, Ts(f), in decibels.

The compensation network that is used (Gc(s)) hasthree poles and one zero. One pole occurs at the origin,and a second pole is caused by the limitations of theoptoisolator. The third pole is set at one-half the switchingfrequency to attenuate the high frequency gain. The zero

T G G Hs(f) c(s) co(s) (s)dB dB dB= + +

RV V

IREF VERR

op

13 = (max)

_ min

R16V

If

TL431_min

=

R32R27(V V )

VOUTB VREF_TL431

VREF_TL431

=

is set at the desired crossover frequency. The followingequations can be used to select R35, C14, and C15 of Gc(s)to obtain the desired design goals.

Figure 8 shows the measured loop gain frequencyresponse, Ts(f). The frequency response characteristics inFigure 8 show that fc was roughly equal to 800 Hz with aphase margin of roughly 50. It is important to note that theequations used to compensate the control loop by select-ing C14, C15, and R35 are estimates and the values mayhave to be adjusted to get the appropriate compensation.

C151

2 R35f

2S

=

CR fc

141

2 35=

R35 R32 10

G G H

20

co(s)dB opto(s)dB (s)dB

=

+ +( )

H Hs sdB( ) ( )log( )= 20

60

40

20

0

20

40

60

100 1 k 10 k 100 k

Ph

as

e(d

eg

ree

s)

Ga

in(d

B)

Frequency (Hz)

180

120

60

0

60

120

180

Opto Gain

Opto Phase

Figure 7. Optoisolator frequency response

10

20

30

40

50

0

20

10

30

40

50

100 1 k 10 k 100 k

Ph

as

e(d

eg

ree

s)

Ga

in,

T(d

B)

s(f

)

Frequency (Hz)

180

36

72

108

144

0

180

144

108

72

36

Gain

Phase

Figure 8. Frequency loop response, Ts(f)


27


0

5

10

15

20

25

30

35

10 20 30 40 50 60 70 80 90 100

Output Power (W)

Cu

rren

tT

HD

(%) V = 85 VIN

V = 175 VIN

V = 265 VIN

Figure 9. Output A THD vs. output power

V = 85 VIN

V = 175 VIN

V = 265 VIN

50

60

70

80

90

100

10 20 30 40 50 60 70 80 90 100

Output Power (W)

Eff

icie

nc

y(%

)

Figure 10. Output A efficiency vs. output power

0.85

0.9

0.95

1

10 20 30 40 60 70 80 90 100

Output Power (W)

PF

V = 85 VINV = 175 VIN

V = 265 VIN

50

Figure 11. Output A PF vs. output power

0

20

40

60

80

1 4 6 8

Output Power (W)

Eff

icie

ncy

(%)

Figure 12. Output B efficiency vs. output power

SummaryIn this design example we reviewed the design of a 100-WPFC ac/dc preregulator with an auxiliary 12-V, 8-W biassupply. The UCC2851x family of combination PWM con-trollers is perfect for offline applications that require PFCand auxiliary power supplies to meet different systemrequirements. The design performance of this two-stagepower converter is shown in Figures 912.

ReferencesFor more information related to this article, you can down-load an Acrobat Reader file at www-s.ti.com/sc/techlit/litnumber and replace litnumber with the TI Lit. # forthe materials listed below.

Document Title TI Lit. #1. Laszlo Balogh, Design Review: 140W,

Multiple Output High Density DC/DC Converter, p. 6-9 . . . . . . . . . . . . . . . . . . . . . . . . .slup117

2. Laszlo Balogh, Unitrode UC3854A/B and UC3855A/B Provide Power Limiting With Sinusoidal Input Current for PFC Front Ends,Unitrode Design Note . . . . . . . . . . . . . . . . . . . . .slua196

3. Lloyd Dixon, Control Loop Cookbook, p. 5-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .slup113

4. Lloyd Dixon, Optimizing the Design of a High Power Factor Switching Preregulator, pp. 7-117-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . .slup093

5. James P. Noon, A 250kHz, 500W Power Factor Correction Circuit Employing Zero Voltage Transitions, pp. 1-111-14 . . . . . . . . . .slup106

6. Practical Considerations in Current Mode Power Supplies, Unitrode Application Note . . .slua110

7. Advanced PFC/PWM Combination Controllers, Data Sheet . . . . . . . . . . . . . . . . . . .slus517

8. UCC28517 EVM Users Guide . . . . . . . . . . . . sluu117

Related Web sitesanalog.ti.comwww.ti.com/sc/device/TL431www.ti.com/sc/device/UCC28517

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