1 1 1 audio-susceptibility analysis. 2 2 2 3 3 3
TRANSCRIPT
1
11
Audio-susceptibility AnalysisA
udi
o-s
usc
ep
tibili
ty A
naly
sis
vsG
pZ
vdG
isG
qZ
idG
mF
iR
vF
d
Iv
conv
Li
ov
sv
oi
2
22
Audio-susceptibility Analysis
( )
with
For Buck Converters
( )1
u
i id i m v vd v m
vs is
vd id S
vsu
i v
A s
T G R F T G F F
G G D
G G V
GA s
T T
Au
dio
-su
sce
ptib
ility
Ana
lysi
s
3
33
Audio-susceptibility Analysis
zco
-1
-2
esr
-1
cr
1|T |
0dB
u| A |
vs|G |
20log D
-1
-11
ci
Au
dio
-su
sce
ptib
ility
Ana
lysi
s
4
44
Audio-susceptibility Analysis
0dB
zc o
-1-2
Case 3
Case 2
Case 1
-1
cr
-2
20log D
zc esr
-1
1| |T
-1
1
1
ci
| |vsG
|A |u
id| |iT
| |vT
Au
dio
-su
sce
ptib
ility
Ana
lysi
s
5
55
Audio-susceptibility Analysis
1| |T
| |iT
| |vsG
| |uA
0.1 1 10 100
-60
-40
-20
0
20
40
60
Mag
nitu
de [
dB]
Frequency [kHz]
4
4
4
Case 1: 1.97 10 r/s
Case 2: 3.91 10 r/s
Case 3: 7.82 10 r/s
v
v
v
K
K
K
Au
dio
-su
sce
ptib
ility
Ana
lysi
s
6
66
Boost or Buck/boost Converter CasesA
udi
o-s
usc
ep
tibili
ty A
naly
sis
1 2
( )1
1 1 111
Two prevailng conditions:
Thus, ( )
11Boost converter:
2(1 ) 1 ( ) / 2
Buck/boost converter:
is vdvs i vs
idu
i v
is vd is vdvs vs
vs id vs id
vi v
i
u
cui
c
G GG T G
GA s
T T
G G G GG G
G G G GTT T T T
T
A s
sCRA
D sC R R
A
2 1
(1 )(1 ) 1 ( ) / (1 )c
uic
sCRD
D D sC R R D
7
77
Output Impedance AnalysisO
utp
ut I
mp
eda
nce
An
aly
sis
vsG
pZ
vdG
isG
qZ
idG
mF
iR
vF
d
Iv
conv
Li
ov
sv
oi
8
88
Output Impedance Analysis
1 2
(1 )
( ) ( )1
1 1 111
Two prevailing conditions:
Thus, ( )
1 1Buck converter: Boost converter:
1 ( ) 2 1 (
ip i q vd
ido o
i v
q vd q vdp p
p pid id
vi v
i
o
c coi oi
c c
TZ T Z G
GZ s Z s
T T
Z G Z GZ Z
Z ZG GTT T T T
T
Z s
sCR sCRRZ R Z
sC R R sC R R
) / 2
1Buck/boost converters:
1 1 ( ) / (1 )c
oic
sCRRZ
D sC R R D
Ou
tpu
t Im
ped
anc
e A
na
lysi
s
9
99
Output Impedance Analysis
esr
cicr
2|T |
pip| Z |
o| Z |
zc
Ou
tpu
t Im
ped
anc
e A
na
lysi
s
10
1010
Output Impedance Analysis
zc
esr
Case 3
Case 2
Case 1
+1
pi
cr
-1
+1
2|T |
oi| Z |
o| Z |
0dB
zc
Ou
tpu
t Im
ped
anc
e A
na
lysi
s
11
1111
Output Impedance AnalysisO
utp
ut I
mp
eda
nce
An
aly
sis
4
4
4
Case 1: 1.97 10 r/s
Case 2: 3.91 10 r/s
Case 3: 7.82 10 r/s
v
v
v
K
K
K
2| |T
| |oiZ
| |oZ
0.1 1 10 100
-40
-20
0
20
Mag
nitu
de [
dB]
Frequency [kHz]
12
1212
Step Load Response: S
tep
Lo
ad
Res
pon
se A
nal
ysis
m0dBmax| |
2010OZ
stepI
1
zc
zc
max
( )
| ( ) | | ( ) |
o
o o
Z s
Z j Z j
1 step
max
( ) ( )
( )
o o
o
Iv t L Z s
s
v t
13
1313
Step Load Response:
max
( )
| ( )| | ( ) |
o
o o
Z s
Z j Z j
zc esr
cr
m0 dB
Ste
p L
oa
d R
esp
onse
An
alys
is
14
1414
Step Load Response:
max
( )
with
( ) (0)
o
zc cro o step
m esr
v t
v t v I
Case 3: cr esr S
tep
Lo
ad
Res
pon
se A
nal
ysis
15
1515
Step Load Response:
max
1
( )
1 1
| ( )|
| ( )|
esro
m
zc cr
o
o
s
sZ s
s s
Z s
Z j
zc cr
esr
m0dB
Ste
p L
oa
d R
esp
onse
An
alys
is
16
1616
Step Load Response:
( ) ( ) ( )( )
(0)
zc crt tstep zc cro esr zc cr esr
cr zc m esr
zc cro step
m esr
Iv t e e
v I
Case 1: cr esr S
tep
Lo
ad
Res
pon
se A
nal
ysis
17
1717
Step Load Response:
max( )
(0) ( )( )
zc cr esr zco o step
m esr cr zcv v t I
Case 1: cr esr
1
zc
1
cr
Ste
p L
oa
d R
esp
onse
An
alys
is
18
1818
Step Load Response
3.5
4.0
4.5
3.5
4.0
4.5
3.5
4.0
4.5
Time [ms]
0.0 0.5 1.0 1.5 2.0 2.5
Case 1: 0.5cr esr
Case 2 : cr esr
Case 3: 2.0cr esr
max| ( )|
20max step
3
Cases 2 and 3:
( ) 10o
szc
Z j
o
t
v t I
max| ( )| | ( )|
20 20maxCase 1: 10 ( ) 10o oZ j Z j
step o stepI v t I
Ste
p L
oa
d R
esp
onse
An
alys
is
19
1919
Small Phase Margin and Output Impedance
Design A DB C
Design A
D
BC
0.1 1 10 100-200
-160
-120
-80
Phas
e [d
eg]
Frequency [kHz]
-20
0
20
40
Mag
nitu
de [
dB]
Design AB C D
0.1 1 10 100-60
-40
-20
0
Frequency [kHz]
Ste
p L
oa
d R
esp
onse
An
alys
is
Design A : Design B :
Design C : Design D :
Loop gain Output impedance
20
2020
Step Load Response
3.5
4.0
4.5 3.5
4.0
4.5 3.5
4.0
4.5 3.5
4.0
4.5
Time [ms]
0.0 0.5 1.0 1.5 2.0 2.5
Design A
Design B
Design C
Design D
Ste
p L
oa
d R
esp
onse
An
alys
is
Design A :
Design B :
Design C :
Design D :
m
m
m
m
21
2121
Switched Capacitor Converter Example
103 104-40
-30
-20
-10
Frequency [Hz]
Mag
nitu
de [
dB]
| o maxZ |
| ( )oZ j |
zc cr
esr
-2
-1
0
1
2
0.2ms0.2msTime [ms]
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Ste
p L
oa
d R
esp
onse
An
alys
is
1
( )
1 1
esro
m
zc cr
s
sZ s
s s
Experimantal output impedance
22
2222
Switched Capacitor Converter Example
103 104-40
-30
-20
-10
Frequency [Hz]
Mag
nitu
de [
dB]
| o maxZ |
| ( )oZ j |
zc cr
esr
-2
-1
0
1
2
0.2ms0.2msTime [ms]
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Ste
p L
oa
d R
esp
onse
An
alys
is
max| ( )| | ( )|
20 20max10 ( ) 10o o
zc
Z j Z j
step o stepI v t I
Experimantal output impedance Predicted step load response
23
2323
Step Load Response S
tep
Lo
ad
Res
pon
se A
nal
ysis
max
33
max
| ( )| | ( )|
20 20max
33/20 23/20max max
3 32 3 10 0.16 ms
2 3 10
| ( ) | 33 dB and | ( ) | 23 dB
10 ( ) 10
4 10 ( ) 4 10 0.10 V ( ) 0.28V
o o
zc szc
Z j Z j
step o step
o o
t
Z j Z j
I v t I
v t v t
24
2424
Current Mode Control for Boost ConverterB
oos
t Con
vert
er
Ca
se
RC
CR
L
convrampv
CSN
PWM
refV
E/A
2Z
1Z
25
2525
Power Stage Transfer Functions
RC
CR
L
oVd
D LˆI d
1:D
iR ( )vF s
mF
d
ˆˆ ( ) ( )( ) ( )
ˆ ˆ( ) ( )o L
vd idv s i s
G s G sd s d s
Bo
ost C
onve
rte
r C
ase
26
2626
Voltage Loop Gain
zco
esrrhp
-270
v|T |
vT
-2
-1-1
-2
-1
vd|G |
2
2
ˆ ( )( )
ˆ( )
1 1
1
ovd
rhp esrvd
oo
v sG s
d s
s s
Ks s
Q
Bo
ost C
onve
rte
r C
ase
27
2727
Instability with
1|T |
-2
-1
-1
-1
0dB
i|T |
i|T |
atv i rhp|T | |T | -1
zco
-9090-
-180
-270
-360
v|T |
vT
-2
-1
-1
Bo
ost C
onve
rte
r C
ase
28
2828
0.1 1 10 100
-450
-300
-150
0
150
Phas
e [d
eg]
Frequency [kHz]
-40
0
40
80
Mag
nitu
de [
dB] | | | | ati v rhpT T
Instability with | | | |i v rhpT T at B
oos
t Con
vert
er
Ca
se
29
2929
Loop Gain Crossover FrequencyB
oos
t Con
vert
er
Ca
se
-902T
-1
o
id
-2
-1
0dB -2
zc
-1
-2
-1
| |vT
| |iT
2| |T
ci
30
3030
Boost Converter ExampleB
oos
t Con
vert
er
Exa
mp
le
CSN
PWM
rampv
4refV V
E/A
1 10kΩR 3C
2R 2C
40 kΩXR
12 V
160 H 0.05Ω
0.05Ω
470 F5Ω
V1.5
2
2
3
1(1 )
1 2
(1 )
2 1
(1 ) 2(1 )
O So rhp
O
Sesr vd id
c
S O Sid L peak s
V V D RD D
V LLC
VK
CR RCD
V V VK i DT
R D LD R
31
3131
Current Loop Design
1) crossover frequency:
2) Dc gain of :
3) CSN gain:
4) Modulator gain:
5) Compensation ramp:
i
i
T
T
Bo
ost C
onve
rte
r E
xam
ple
32
3232
Voltage Loop Design
6) Compensation pole:
7) Compensation zero:
8) crossover frequency:
9) Integrator gain:
10) Voltage feedback circuit:
2T
Bo
ost C
onve
rte
r E
xam
ple
33
3333
Loop GainsL
oop
Ga
ins
1| |T
| |iT | |vT
| |vT
| |iT 2| |T
0.01 0.1 1 10 100
-40
-20
0
20
40
60M
agni
tude
[dB
]
Frequency [kHz]
0.01 0.1 1 10 100
-40
0
40
Mag
nitu
de [
dB]
Frequency [kHz]
1
2
1
2
Design targets:
crossover frequency:
crossover frequency:
Design results:
crossover frequency:
crossover frequency:
T
T
T
T
34
3434
Loop Gains
1| |T
2| |T
2T
1T
0.01 0.1 1 10 100
-240
-200
-160
-120
-80
-40
Pha
se [
deg]
Frequency [kHz]
-40
-20
0
20
40
60
Mag
nitu
de [
dB]
Overall loop gain:
Outer loop gain:
Loo
p G
ain
s
35
3535
Closed-Loop PerformanceF
requ
enc
y-do
ma
in P
erf
orm
anc
e
2| |T
| |uiA
| |uA
0.01 0.1 1 10 100-60
-40
-20
0
20
40
Frequency [kHz]
2| |T
| |oZ
| |oiZ
0.01 0.1 1 10 100-40
-20
0
20
40
Frequency [kHz]
Audio-susceptibility Output impedance
36
3636
Closed-Loop Performance
8 10 12 14 16 185
10
15
20
25
Time [ms]8 10 12 14 16 18
5
10
15
20
25
Time [ms]
( ) [V]Ov t
( ) [A]Li t
( ) [V]Ov t
( ) [A]Li t
Tim
e=
-do
ma
in P
erf
orm
ance
Step Input Response Step Load Response
37
3737
Loop Gain AnalysisL
oop
Ga
in A
naly
sis
2890vK
5780vK
2890vK 5780vK
0.01 0.1 1 10 100-300
-200
-100
0
Pha
se [
deg]
Frequency [kHz]
0
30
60
Mag
nitu
de [
dB]
38
3838
Loop Gain Analysis
2890vK
14560vK
5780vK 9900vK
14560vK
9900vK
2890vK
5780vK
0.01 0.1 1 10 100
-240
-200
-160
-120
-80
Pha
se [
deg]
Frequency [kHz]
-20
0
20
40
Mag
nitu
de [
dB]
Loo
p G
ain
Ana
lysi
s
39
3939
Loop Gain Analysis
1T
2| |T
2T
0.01 0.1 1 10 100-240
-200
-160
-120
-80
-40
Pha
se [
deg]
Frequency [kHz]
-30
0
30
60
Mag
nitu
de [
dB]
Loo
p G
ain
Ana
lysi
s
40
4040
Loop Gain Analysis
-4 -3 -2 -1 0-2
-1
0
1
2
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2-5
-4
-3
-2
-1
0
1
2
3
4
5
14560vK
2890vK
5780vK
9900vK
2890vK
14560vK
5780vK 9900vK
Loo
p G
ain
Ana
lysi
s
Overall Loop Gain
Outer Loop Gain
41
4141
Root Locus AnalysisR
oo
t Lo
cus
An
alys
is
-5.00k -3.75k -2.50k -1.25k 0.00 1.25k 2.50k
-10.0k
-5.0k
0.0
5.0k
10.0k 9900vK
5780
2890
14560