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CS 161Computer Architecture

Chapter 5Lecture 12

Instructor: L.N. Bhuyanwww.cs.ucr.edu/~bhuyan

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Datapath + Control Points

ALU

Regs

ReadReg1

Readdata1

Readdata2

ReadReg2

WriteReg

WriteData

Sgn Ext- end

PC

<<2

A

B

ALU-Out

Address

ReadData

Mem

WriteData

MDR

Mux

25:21

20:16

15:0 0 1M2 u3 x

Mux

Mux

Mux

IR4

z

15:11

IorDMemRead

MemWriteIRWrite

RegDstRegWrite

ALUSrcA

ALUSrcB

MemtoReg

ALUControl

ALUOp

22

3

(funct) 5:0

Mux

PCSrcPCWrite

PCWrite-Cond

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Multicycle Instruction Execution°All instructions execute in 3-5 cycles

• 3 cycles: beq

• 4 cycles: R-type, sw

• 5 cycles: lw

°1: fetch instruction, PC=PC+4

°2: decode, fetch registers, brnch target

°3: execute/compute address/branch

°4: access memory/complete R-type

°5: (lw) store memory

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Summary:

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Implementing a Finite State Machine

• internal storage (current state register)

• two combinational circuits: - next state function; output function

Clock

Nextstate

Outputs

Inputs

OutputFunction

Next-stateFunction

current state reg

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MemReadALUSrcA = 0

IorD = 0IRWrite

ALUSrcB = 1ALUOp = 0

PCWritePCSrc = 0

state 0

ALUSrcA = 0ALUSrcB = 3ALUOp = 0

ALUSrcA = 1ALUSrcB = 2ALUOp = 0

ALUSrcA = 1ALUSrcB = 0

ALUOp =2

ALUSrcA = 1ALUSrcB = 0

ALUOp =1PCWriteCond

PCSrc = 1

1

26

8

Memory Access

R-format execution

Branch Completion

FSM diagram for Multicycle Machine

start new instruction

cycle1

cycle2

cycle3

lw/sw

R-form

at beq

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MemReadIorD = 1

MemWriteIorD = 1

RegDst = 1RegWrite

MemtoReg = 0

RegDst = 0RegWrite

MemtoReg = 1

write-back (step 5)

memoryaccess(step 4)

memoryaccess(step 4)

R-formatcompletion

(step 4)

3 5 7

4

from state 2

to state 0

FSM controller: execution cycles 3-5

lw sw

from state 6

cycle4

cycle5

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°Note:• don’t care if not

mentioned

• asserted if name only

• otherwise exact value

• How many state bits will we need?

Add JumpMemRead

ALUSrcA = 0IorD = 0IRWrite

ALUSrcB = 01ALUOp = 00

PCWritePCSource = 00

ALUSrcA = 0ALUSrcB = 11ALUOp = 00

ALUSrcA = 1ALUSrcB = 00ALUOp = 10

ALUSrcA = 1ALUSrcB = 10ALUOp = 00

MemReadIorD = 1

MemWriteIorD = 1

RegDst = 1RegWrite

MemtoReg = 0

RegDst = 1RegWrite

MemtoReg = 0

PCWritePCSource = 10

ALUSrcA = 1ALUSrcB = 00ALUOp = 01

PCWriteCondPCSource = 01

Instruction decode/register fetch

Instruction fetch

0 1

Start

Jumpcompletion

9862

3

4

5 7

Memory readcompleton step

R-type completionMemoryaccess

Memoryaccess

ExecutionBranch

completionMemory address

computation

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° How many cycles will it take to execute this code? lw $t2, 0($t3)

lw $t3, 4($t3)beq $t2, $t3, Label #assume notadd $t5, $t2, $t3sw $t5, 8($t3)

Label: ...

What is going on during the 8th cycle of execution?

In what cycle does the actual addition of $t2 and $t3 takes place?

Simple Questions

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Implementing the FSM controller PCWrite

PCWriteCond

IorD

MemtoReg

PCSrc

ALUOp

ALUSrcB

ALUSrcA

RegWrite

RegDst

NS3NS2NS1NS0

Op

5

Op

4

Op

3

Op

2

Op

1

Op

0

S3

S2

S1

S0

IRWrite

MemRead

MemWrite

Outputs

Inputs

PLA or ROMimplementation of both next-state and output functions

Next-state}

DatapathControl Points

Instruction register opcode field

state register

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PLA Implementation

Op5

Op4

Op3

Op2

Op1

Op0

S3

S2

S1

S0

IorD

IRWrite

MemReadMemWrite

PCWritePCWriteCond

MemtoRegPCSource1

ALUOp1

ALUSrcB0ALUSrcARegWriteRegDstNS3NS2NS1NS0

ALUSrcB1ALUOp0

PCSource0

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° ROM = "Read Only Memory"• values of memory locations are fixed ahead of time

° A ROM can be used to implement a truth table• if the address is m-bits, we can address 2m entries in the

ROM.

• our outputs are the bits of data that the address points to.m is the "height", and n is the "width“ equal to number of outputs.

ROM Implementation

m n

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° How many inputs are there?6 bits for opcode, 4 bits for state = 10

address lines(i.e., 210 = 1024 different addresses)

° How many outputs are there?16 datapath-control outputs, 4 state

bits = 20 outputs

° ROM is 210 x 20 = 20K bits (and a rather unusual size, so go for next size chip)

° Rather wasteful due to lots of don’t care situations => the outputs onlydepend on states, not opcodes.

ROM Implementation

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° Break up the table into two parts

— 4 state bits tell you the 16 outputs, 24 x 16 bits of ROM

— 10 bits tell you the 4 next state bits, 210 x 4 bits of ROM

— Total: 4.3K bits of ROM => Lots of savings.

° PLA is much smaller

— can share product terms

— only need entries that produce an active output

— can take into account don't cares

° Size is (#inputs #product-terms) + (#outputs #product-

terms)

For this example = (10x17)+(20x17) = 510 PLA cells

PLA cells usually about the size of a ROM cell (slightly

bigger)

ROM vs PLA

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Alternative to FSM for Multi-cycle? °MIPS-lite has (about) 7 instructions, 10 FSM states

°Real machines have 100 or more instructions; real controllers have hundreds, or even thousands of states!

°Problem: FSM Bubble-diagram too large

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Observation about real machines°Machine Language: next instruction

to be executed is usually implied• PC register determines instruction

• next instruction always at PC+4 (unless branch or jump)

°FSM Controller: often only one exit arc from current state to next state

°Suppose borrow idea from Machine Language, represent each control step as some kind of “instruction”?

°Leads to Microprogrammed Control

n

n+1

n+2

n+3

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Micro-programmed Control° In microprogrammed control, FSM states become microinstructions of a microprogram (“microcode”)

• one FSM state=one microinstruction

• usually represent each micro-instruction textually, like an assembly instruction

°FSM current state register becomes the microprogram counter (micro-PC)

• normal sequencing: add 1 to micro-PC to get next micro-instruction

• microprogram branch: separate logic determines next microinstruction

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Microprogramming Vs Hardwired Control° Microprogramming offers flexibility for

design and architectural changes. The control memory (ROM) can be reprogrammed or replaced. Hardwired control is difficult to design for complex set architecture. Once it is designed, no further change is possible

° Microprogramming is slow because the control memory is accessed in every cycle. Memory access is slow. Hardwired control is fast because the cycle time depends on the combinational logic delay of the control unit, which is much less than memory access time.

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Microprogramming

°What are the “microinstructions” ?

PCWritePCWriteCondIorD

MemtoRegPCSourceALUOpALUSrcBALUSrcARegWrite

AddrCtl

Outputs

Microcode memory

IRWrite

MemReadMemWrite

RegDst

Control unit

Input

Microprogram counter

Address select logic

Adder

1

Instruction registeropcode field

BWrite

Datapath

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° A specification methodology

• appropriate if hundreds of opcodes, modes, cycles, etc.

• signals specified symbolically using microinstructions

Will two implementations of the same architecture have the same microcode? What would a microassembler do?

Microprogramming

LabelALU

control SRC1 SRC2Register control Memory

PCWrite control Sequencing

Fetch Add PC 4 Read PC ALU SeqAdd PC Extshft Read Dispatch 1

Mem1 Add A Extend Dispatch 2LW2 Read ALU Seq

Write MDR FetchSW2 Write ALU FetchRformat1 Func code A B Seq

Write ALU FetchBEQ1 Subt A B ALUOut-cond FetchJUMP1 Jump address Fetch

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Microinstruction formatField name Value Signals active Comment

Add ALUOp = 00 Cause the ALU to add.ALU control Subt ALUOp = 01 Cause the ALU to subtract; this implements the compare for

branches.Func code ALUOp = 10 Use the instruction's function code to determine ALU control.

SRC1 PC ALUSrcA = 0 Use the PC as the first ALU input.A ALUSrcA = 1 Register A is the first ALU input.B ALUSrcB = 00 Register B is the second ALU input.

SRC2 4 ALUSrcB = 01 Use 4 as the second ALU input.Extend ALUSrcB = 10 Use output of the sign extension unit as the second ALU input.Extshft ALUSrcB = 11 Use the output of the shift-by-two unit as the second ALU input.Read Read two registers using the rs and rt fields of the IR as the register

numbers and putting the data into registers A and B.Write ALU RegWrite, Write a register using the rd field of the IR as the register number and

Register RegDst = 1, the contents of the ALUOut as the data.control MemtoReg = 0

Write MDR RegWrite, Write a register using the rt field of the IR as the register number andRegDst = 0, the contents of the MDR as the data.MemtoReg = 1

Read PC MemRead, Read memory using the PC as address; write result into IR (and lorD = 0 the MDR).

Memory Read ALU MemRead, Read memory using the ALUOut as address; write result into MDR.lorD = 1

Write ALU MemWrite, Write memory using the ALUOut as address, contents of B as thelorD = 1 data.

ALU PCSource = 00 Write the output of the ALU into the PC.PCWrite

PC write control ALUOut-cond PCSource = 01, If the Zero output of the ALU is active, write the PC with the contentsPCWriteCond of the register ALUOut.

jump address PCSource = 10, Write the PC with the jump address from the instruction.PCWrite

Seq AddrCtl = 11 Choose the next microinstruction sequentially.Sequencing Fetch AddrCtl = 00 Go to the first microinstruction to begin a new instruction.

Dispatch 1 AddrCtl = 01 Dispatch using the ROM 1.Dispatch 2 AddrCtl = 10 Dispatch using the ROM 2.

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° No encoding:

• 1 bit for each datapath operation

• faster, requires more memory (logic)

• used for Vax 780 — an astonishing 400K of memory!

° Lots of encoding:

• send the microinstructions through logic to get control signals

• uses less memory, slower

° Historical context of CISC:

• Too much logic to put on a single chip with everything else

• Use a ROM (or even RAM) to hold the microcode

• It’s easy to add new instructions

Maximally vs. Minimally Encoded

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Microcode: Trade-offs

° Distinction between specification and implementation is sometimes blurred

° Specification Advantages:

• Easy to design and write

• Design architecture and microcode in parallel

° Implementation (off-chip ROM) Advantages

• Easy to change since values are in memory

• Can emulate other architectures

• Can make use of internal registers

° Implementation Disadvantages, SLOWER now that:

• Control is implemented on same chip as processor

• ROM is no longer faster than RAM

• No need to go back and make changes

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Historical Perspective

° In the ‘60s and ‘70s microprogramming was very important for implementing machines

° This led to more sophisticated ISAs and the VAX

° In the ‘80s RISC processors based on pipelining became popular

° Pipelining the microinstructions is also possible!

° Implementations of IA-32 architecture processors since 486 use:

• “hardwired control” for simpler instructions (few cycles, FSM control implemented using

PLA or random logic)

• “microcoded control” for more complex instructions(large numbers of cycles, central control

store)

° The IA-64 architecture uses a RISC-style ISA and can be implemented without a large central control store

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Pentium 4

° Somewhere in all that “control we must handle complex instructions

° Processor executes simple microinstructions, 70 bits wide (hardwired)

° 120 control lines for integer datapath (400 for floating point)

° If an instruction requires more than 4 microinstructions to implement, control from microcode ROM (8000 microinstructions)

° Its complicated!

Control

Control

Control

Enhancedfloating pointand multimedia

Control

I/Ointerface

Instruction cache

Integerdatapath

Datacache

Secondarycacheandmemoryinterface

Advanced pipelininghyperthreading support

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Chapter 5 Summary

° If we understand the instructions…

We can build a simple processor!

° If instructions take different amounts of time, multi-cycle

is better

° Datapath implemented using:

• Combinational logic for arithmetic

• State holding elements to remember bits

° Control implemented using:

• Combinational logic for single-cycle implementation

• Finite state machine for multi-cycle implementation

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Pipelining (Chap 6)

°Techniques illustrated in chapter 5 are at the heart of every computer

°All recent computers, however, go beyond techniques of chapter 5, and use pipelining to improve performance

°By overlapping execution of multiple instructions, pipelining can achieve:

• throughput close to 1 instruction per clock cycle (like single-cycle machine)

• with a clock cycle time determined by the delay of individual datapath components (like multi-cycle machine)