1

2010 Litho ITRS Update

Lithography iTWG

July 2010

2

Outline

• Major Challenges

• Lithography Potential Solutions

• Some table updates

• Summary

3

ITRS Working GroupChris Bencher AMATReiner Garreis Carl ZeissNaoya Hayashi DNPHarry Levinson GLOBALFOUNDRIESMichael Lercel IBMBob Gleason LuminescentDoug Resnick Molecular ImprintsTetsuo Yamaguchi NuFlare Mauro Vasconi NumonyxTakayuki Uchiyama Renesas ElectronicsDavid Chan SEMATECHLloyd Litt SEMATECHTony Yen tsmcGrant Willson UT Austin

4

Difficult Challenges > / = 16nmEquipment infrastructure (writers, inspection, metrology, cleaning, repair) for fabricating masks with sub-resolution assist features

Registration, CD, and defect control for masks

Eliminating formation of progressive defects and haze during exposure

Understanding and achieving the specific signature and specifications for a Double Patterned mask

Establishing a stable process so that signatures can be corrected.

Overlay of multiple exposures including mask image placement, mask-to-mask matching, and CD control for edges defined by two separate exposuresAvailability of software to split the pattern, apply OPC, and verify the quality of the split while preserving critical features and maintaining no more than two exposures for arbitrary designsAvailability of high productivity scanner, track, and process to maintain low cost-of-ownership

Photoresists with independent exposure of multiple passes

Fab logistics and process control to enable low cycle time impact that efficient scheduling of multiple exposure passes.

Achieving constant/improved ratio of exposure related tool cost to throughput over time

ROI for small volume products

Resources for developing multiple technologies at the same time

Cost-effective resolution enhanced optical masks and post-optical masks, and reducing data volume

450 mm diameter wafer infrastructure if at 16nm

Optical masks with features for resolution enhancement and post-optical mask fabrication

Cost control and return on investment

Doluble and Multiple Patterning

5

Difficult Challenges > / = 16nm

New and improved alignment and overlay control methods independent of technology option to

<5.7 nm 3s overlay error

Controlling LER, CD changes induced by metrology, and defects < 10 nm in size

Greater accuracy of resist simulation models

Accuracy of OPC and OPC verification, especially in presence of polarization effects

Lithography friendly design and design for manufacturing (DFM)

Source power > 180 W at intermediate focus, acceptable utility requirements through increased conversion efficiency and sufficient lifetime of collector optics and source componentsCost control and return on investmentResist with < 1.5 nm 3s LWR, < 10 mJ/cm2 sensitivity and < 20 nm ½ pitch resolutionFabrication of Zero Printing Defect Mask Blanks

Establishing the EUVL mask Blank infrastructure (Substrate defect inspection, actinic blank inspection)

Establishing the EUVL patterned mask infrastructure (Actinic mask inspection, EUV AIMs)Controlling optics contamination to achieve > five-year lifetimeProtection of EUV masks from defects without pelliclesFabrication of optics with < 0.10 nm rms figure error and < 7% intrinsic flare

EUV lithography

Process control

6

Difficult Challenges <16nmNAhigher Source power

Resist

incident angle

Limits of chemically amplified resist sensitivity for < 16 nm half pitch due to acid diffusion lengthMaterials with improved dimensional and LWR control add (limits)Resist and antireflection coating materials composed of alternatives to PFAS compoundsLow defects in resist materials (size < 10nm)Line width roughness < 1.4nm 3 sigma

Timeliness and capability of equipment infrastructure (writers, inspection, metrology, cleaning, repair)

Increasingly long mask write and cycle time Mask process control methods and yield enhancementCost control and return on investment

Required degree of complexity with computational Lithography

Different LTEM and absorber material to deal with high source power and heating

double patterning at EUV, flare

Resist materials

EUV lithography - Extendibility

Mask fabrication

7

Achieving constant/improved ratio of exposure-related tool cost to throughputDevelopment of cost-effective post-optical masksCost effective 450mm lithography systemsAchieving ROI for small volume products

Cost control and return on investmentWafer processing to tighter overlay and CD controlsMask fabrication to tighter specifications

Required degree of complexity with computational Lithography Increasing numbers of masks required.Defect inspection on patterned wafers for defects < 20 nmResolution and precision for critical dimension measurement down to 6 nm, including line width roughness metrology for 0.8 nm 3sMetrology for achieving < 2.8 nm 3s wafer overlay errorTemplate inspection for 1X Imprint Patterned MasksPhase shifting masks for EUV

Limits of chemically amplified resist sensitivity for < 16 nm half pitch due to acid diffusion length

193 nm Immersion Multilple Patterning

Metrology and defect inspection

Cost control and return on investment

Difficult Challenges <16nm

8

Development of litho and post litho processes to control gate CD < 1.5 nm 3s with < 1.4 nm 3s line width roughness. Printed, post print process reduction, and final roughnessDevelopment of new and improved alignment and overlay control methods independent of technology option to achieve total < 2.8 nm 3s overlay error on products. especially for imprint lithography

Wafer ThroughputCost control and return on investmentDie-to-database inspection of wafer patterns written with maskless lithographyPattern placement - including stichingControlling variability between beams in multibeam systems

Defect-free Imprint templates at 1X dimensionsInfrastructure for 1X technology Templates (Write, inspection, and repair)Template fabrication to tighter specificationsProtection of Imprint templates from defects without pellicles

Mask Life timeThroughputCost control and return on investmentOverlayProcess control methods to compensate for systematic CD and overlay errors

Maskless Lithography

Imprint Lithography

Gate CD control improvements and process control

Difficult Challenges <16nm

9

First Year of IC Production 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024

Flash ½ Pitch (nm) (un-contacted Poly)(f) 38 32 28 25 23 20 18 16 14 13 11 10 8.9 8.0 7.1 6.3

32

22

16193nm immersion Multiple PatternEUVML2Imprint193nm immersion + DSAInterference Lithography

11 EUV193nm immersion Multiple PatternImprintEUV + DSAML2Innovative patterning solution

193 nm Immersion Double Pattern

193 nm Immersion Double Pattern

Narrow Options

Narrow Options

NAND Flash Time Line

2010 28 & 25 nm HP

10

First Year of IC Production 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024

DRAM ½ pitch (nm) (contacted) 52 45 40 36 32 28 25 23 20 18 16 14 13 11 10 9

MPU/ASIC Metal 1 (M1) ½ pitch (nm) 54 45 38 32 27 24 21 19 17 15 13 12 11 9.5 8.4 7.5

45 193 nm Immersion with water

32 193 nm Immersion Double PatternEUV - Korea input pending + footnote

22 EUV193 nm Immersion Double / Multiple PatternML2 (MPU only)Imprint (DRAM only)

16 EUV193nm immersion Multiple PatternML2Imprint193nm immersion + DSAInterference Lithography

11 EUVML2ImprintLitho + DSAInnovative patterning solution

Narrow Options

Narrow Options

Narrow Options

Narrow Options

MPU / DRAM time line

11

Proposed Optical / EUV Mask Updates

Year of Production 2009 2010 2011 2012DRAM/ MPU/ ASIC (M1) ½ pitch (nm) (contacted) 52 45 40 36

DRAM CD control (3 sigma) (nm) 5.4 4.7 4.2 3.7

Flash ½ pitch (nm) (un-contacted poly) 38 32 28 25MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) 54 45 38 32

Optical CD mean to target (nm) [M] 4.1 3.6 3.2 2.9

EUV (Is) CD mean to target (nm) [H] 4.1 3.6 3.2 2.9EUV (New)CD mean to target (nm) [M] 4.1 3.6 3.2 2.9

Optical Defect size (nm) [N] * 41 36 32 29

EUV (Is) Defect size (nm) [I] 41 36 32 29EUV (New)Defect size (nm) [I] 41 36 32 29

12

Double Patterning Update

Mean CD Difference in DP Lines 0.6 0.5 0.5 0.4 0.4 0.3 0.3

Pooled Dual Line CD control (3 sigma) (nm) 2.7 2.4 2.2 2.0 1.8 1.7 1.5

Max. mean overlay for MPU LFLE or LELE 0.6 0.5 0.4 0.4 0.3 0.3 0.3

Overlay 3s for MPU LFLE or LELE 3.8 3.1 2.6 2.3 2.0 1.8 1.5

Printed Dependent Space CD control for MPU LFLE-LELE (nm,3s)

4.5 3.8 3.2 2.9 2.5 2.3 2.0

Generic Pitch Splitting - Double Patterning Requirements Driven by MPU metal 1/2 Pitch

No DP at this pitches (45nm and

above)

Image placement (nm, multipoint) for double patterning of dependent layers [V] 3.4 3.0 2.7

Difference in CD Mean-to-target for two masks used as a double patterning set (nm) [W]

Spec under review. Recommended to be removed at present.

Pitch Spliting - Double Patterning Specific Mask No DP at

this pitches (45nm and

above)

13

• Preliminary feedback:

•No differentiation among different products

•No mask cost increase by node

•Write time increase

•No breakdown on “critical” and “non-critical”

• Need to check published data by TSMC and Intel

14

Summary• Lithography solutions for 2010

– 45 nm half-pitch - 193 Immersion Single Exposure for DRAM/MPU

– Flash using Double Patterning (Spacer) for 32 nm half-pitch

• Lithography solutions for 2013– 32 nm half-pitch Double patterning or EUV for DRAM/MPU– EUV needed – 16 nm half-pitch for Flash and 22nm

DRAM/MPU

• Double exposure / patterning requires a complex set of parameters when different exposures are used to define single features

• Mask Complexity for Double patterning• Mask Infrastructure for EUV