1 4-bit decimation filter rashmi joshi siu kuen(steve) leung cuong trinh advisor: dr. david parent...
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![Page 1: 1 4-bit Decimation Filter Rashmi Joshi Siu Kuen(Steve) Leung Cuong Trinh Advisor: Dr. David Parent December 5, 2005](https://reader030.vdocument.in/reader030/viewer/2022032704/56649d3b5503460f94a15f86/html5/thumbnails/1.jpg)
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4-bit Decimation Filter
Rashmi JoshiSiu Kuen(Steve) Leung
Cuong Trinh
Advisor: Dr. David ParentDecember 5, 2005
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Agenda
• Abstract• Introduction• Summary of Results• Project Details• Results• Cost Analysis• Conclusions
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Abstract
• We designed a 4-bit Decimation Filter. The system operates at 142.8 MHz, uses less than 192.5 mW per clock of power, and occupies an area of 550x890 m2.
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Introduction
• Decimation filter is used to average the output of an A/D converter. The function of a decimation filter is to remove all of the out-of-band signals and noise, and to reduce the sampling rate by k.
• Decimation filter samples input data until k samples have been accumulated. The output is then the sum of k (=4) accumulated samples. The frequency of the output is thus 4 times less than that of the input.
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Project Summary
The design consists of a nand-based 7-bit ripple carry adder, a divide-by-4 counter, and 3 stacks of D flip-flops. The first stack is at the input side. The second stack serves as an accumulator. A divide-by-4 counter clocks the out put flip-flops and resets the accumulator.
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Block Diagram
FF6 FF0FF1FF2FF3FF4FF5
FF6 FF0FF1FF2FF3FF4FF5
FF6 FF0FF1FF2FF3FF4FF5
FA6 FA5 FA0
Counter
X3 X2 X1 X0
Y0Y1Y2Y3Y4Y5Y6
ck ckckckck
v
ckck ck
ckck
ck ck ck ck
A0A5A6
B0B5B6
Cin
ckck ck ck ck ck ck
K=4
clk
D0D5D6
Preset
CLK/kD0D5D6
RR R R R RR
OUTPUT
INPUT
S6 S5 S0
clk
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Longest Path Calculations
Tphl = 6.666ns/20 = .333ns
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Schematic (4-BIT-DECIMATION FILTER)
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Layout (4-BIT-DECIMATION FILTER)
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LVS
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Schematic Simulation
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Analog Extracted Simulation
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Impulse and step input responses
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Cost Analysis
• Estimated time spent on each phase of the project:– verifying logic (1 week)– verifying timing (1 week)– layout (3 weeks)– post extracted timing (2 weeks)
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Lessons Learned
• LVS failure due to same metal layer wire crossing. This can be spotted in single layer view and LVS high-lighted errors in analog-extracted view.
• Spend more time on researching on alternative design options.
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Summary
• This project is a good start for students to learn IC design flow with CAD tool.
• The design can run at 142.8 MHz, has an area of 550x890 m2, and uses less than 192.5 mW per clock of power.
• The design can run faster than 150 MHz if a CLA adder is used instead of RC adder.
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Acknowledgements
• Thanks to our family for support
• Thanks to Cadence Design Systems for the VLSI lab
• Thanks to Professor David Parent for guidance