1 adc performance metrics, measurement and calibration techniques tibi galambos jan 2009
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1
ADC Performance Metrics, Measurement and Calibration Techniques
Tibi Galambos
Jan 2009
2
Outline
Performance metrics of ADC- Definitions (INL, DNL, ENOB, SNDR)
- Measurement techniques - histogram method
- A glimpse at ADC state of the art Calibration techniques for ADC (overview)
- stating the problem
- classification of techniques
- examples
3
ADC Performance metrics – A High Level ADC Model
S
Xddt
Vin
jRMS
njitter
SS
nQ
nps
nthermal
nD
Nout
ADC Model jRMS = clock jitter (RMS cycle to cycle)
nD = distortion (RMS value)
nQ = quantization noise (RMS value, uniform)
nSupply = power supply noise (RMS value, spikes) PSRR can be modeled as LPF
nthermal = thermal noise (RMS value, gaussian)
nSupply
PSRR
ABWABW = analog (full power)
bandwidth
The signal to noise and distortion ratio (SNDR) (assuming a full scale single tone input) is:
Based on the SNDR, the effective number of bits ENOB are defined as:
22222
8
2
log10psjitterthermalDQ
VFS
nnnnnSNDR
02.6
76.1 SNDR
ENOB
4
ADC Performance metrics – Static Characteristic of an Ideal ADC
Vin
Nout
-VFS/2 VFS/2
VLSB
VLSB
1/2
-1/2
NoutMax
-NoutMax
-NoutMax
NoutMax
NLEV oddNLEV even
Vi Vi+1Vci
VLSB=VFS/NLEVNoutMax=(NLEV-1)/2
Vci=i*VLSBVi=(i-½)*VLSB
1
-1
NLEV
VFSVLSB ideal
MaxMax
i
NoutiNout
iVLSBV
1for
)( 21idealideal
Decision levels:
12
22 VLSB
nQ
Quantization error (noise):
Assumes uniform signal PDF over the code bin.ADC Resolution:
For a full-scale single tone signal quantized by an ideal ADC:
76.102.6)log(20log10)log(10log102
23
2
23
2
8ideal2
NbitNLEV
nSNDR
NbitNLEV
VLSBVFS
Q
VFS
)(log2 NLEVNbit
ENOB definition
5
ADC Performance metrics – Offset and Gain Error
Offset and gain errors can be defined by end-to-end or by best fit.
End-to end definitions (using the outer decision levels):
Vin
Nout
-VFS/2 VFS/2
1/2
-1/2
NoutMax
-NoutMax
Ideal ADC
Viideal
V-Noutmax+1 VNoutmax
Non-Ideal ADC
NoutMax-1/2
-NoutMax+1/2
(NLEV-2)*VLSB
Vi
Voff
i
Gain Error
2
1 MaxMax NoutNout VVVoff
2
1
NLEV
VVVLSB MaxMax NoutNout
[%]1001ideal
VLSB
VLSBGE
6
ADC Performance metrics – INL and DNL
INL (integral non-linearity) and DNL (differential non-linearity) are defined AFTER correcting for linear (offset and gain) errors.
Vin
Nout
-VFS/2 VFS/2
V-Noutmax+1 VNoutmax
Non-Ideal ADC
NoutMax-1/2
-NoutMax+1/2
(NLEV-2)*VLSB
Vi
INLi*VLSB
Voff
Vi*ideal
Offset and Gain Fitted Ideal ADC
i
2
1
iVLSB
VoffVINL i
i
iiii
i INLINLVLSB
VVDNL
11 1
INL can be interpreted as the distance between the actual decision level and the decision level of an ideal ADC that has been gain and offset corrected expressed in VLSB units.
The DNL expresses the difference between the actual and the ideal code bin widths in VLSB units.
The first and last code bin widths are defined by extension by VLSB, so that by definition:
001 MaxMaxMaxMax NoutNoutNoutNout DNLDNLINLINL
1i
Noutkki
Max
DNLINL
Max
Max
Nout
NoutkkDNL 0
7
ADC Performance metrics – From INL to ENOB There is no simple conversion from the two metrics, however:
Max
Max
i
i
Nout
Nouti
V
V
i
ii
DQ dvVcvVVNLEV
n1
2ideal*
1
2 )(11
22
211
222
2
312
D
Max
Max
Q n
Nout
Noutiiiii
n
DQ INLINLINLINLNLEV
VLSBVLSBn
iINL
INL
2222
27
2
123
2
12
2222222
DQDQ n
Max
nn
INL
n
DQ
INLVLSBVLSBVLSBVLSBn
22
211
222
2
312
D
Max
Max
Q n
Nout
Noutiiiiii
n
DQ INLINLINLINLPVLSBVLSB
n
iP
The mean square error (quantization and distortion) can be calculated (assuming the input signal has an uniform probability density function):
(uniform PDF input) We observe that equation above contains the quantization and the distortion components. Making the further assumption that
are uncorrelated, with a normal distribution of standard deviation then we get:
(uniform PDF input)For signals that do not have an uniform probability density function, assuming the probability density is uniform within each code bin we get:
where is the probability that the input signal is within code bin i.
8
ADC Performance – A Glimpse at ADC State of the Art(1)
R.H. Walden, “Analog-to-digital converter survey and analysis,” IEEE Journal on Selected Areas in Communications,
vol. 17, no. 4, pp. 539-550, April 1999.
ADC performance is limited by fundamental laws of nature
9
ADC Performance – A Glimpse at ADC State of the Art(2)
Additional performance metrics are customary:
NbitteSamplingRa
Power
2isionEnergy/Dec
ENOBteSamplingRa
ageSupplyVoltPower
2FOMMerit of Figure
R.H. Walden, “Analog-to-digital converter survey and analysis,” IEEE Journal on Selected Areas in Communications,
vol. 17, no. 4, pp. 539-550, April 1999.
Progress in ADC performance in terms of ENOB is slow
10
ADC Performance – A Glimpse at ADC State of the Art(3)
Yun Chiu; Gray, P.R.; Nikolic, B.,"A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR", IEEE Journal of
Solid-State Circuits, , Volume: 39 , Issue: 12 , Dec. 2004
Progress in ADC power consumption (Figure of Merit) is fast
11
ADC Performance – A Glimpse at ADC State of the Art(4)
Where do we stand today?
0
2
4
6
8
10
12
14
16
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10
Sampling Rate [Samples/s]
EN
OB
[b
it]
ISSCC2009 ISSCC2007 ADI
0.000
0.500
1.000
1.500
2.000
2.500
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10
Sampling Rate [Samples/s]
En
erg
y p
er d
ecis
ion
[p
J]
ISSCC2009 ISSCC2007 ADI
Research papers quote net power, industrial data is for a packaged ADC
12
ADC Performance – A Glimpse at ADC State of the Art(4)
Recent trends in ADC design- Very high sampling rate modest resolution low power converters
for serial communications- High complexity DSP-intensive solutions
- ADC power has decreased x10 in the last decade,
- In the same period, digital circuit power has decreased x100.
- SNR > 50 digital is very cheap
- SNR >70 it is for free.
- New design paradigm: analog, DSP and system level have to go hand in hand.
13
ADC Measurement Techniques – The Histogram MethodSetup for ADC Characterization
For measurement purposes we need a very accurate signal source - single and dual tone sources are used
In order to get a clean measurement, a very large number of samples is required
A convenient way to reduce the storage requirements for the samples is to collect a histogram: count the occurrences h(i) of each code bin I
The normalized cumulative normalized histogram is defined:
Generator
Clock Source
Data CollectionADC Under Test
Post-Processing
BPF
ff
f
The spectral purity of the signal applied to the ADC is very important
The jitter on the clock source has to be well controlled
The clock and signal frequencies have to be close to independent to make sure all possible clock-signal phase relationships are swept
)()(
)()( 1
0
0
iL
k
i
k VvPkh
khich
14
ADC Measurement Techniques – The Histogram MethodSine Wave Quantization
If we know the signal amplitude and offset we can calculate the decision levels from the normalized cumulative histogram of the code bins
The signal at the input of the ADC is usually not directly accessible for measurement:
- The parameters A and d have to be estimated
- Note: V is measured here in LSB units
A
d
p p ffi p fi
Vi
d+Asin(fi)
p
p
pfpf
2
arcsin2
2
2))((
AdV
VvP
i
ii
1
))((cosich
ii VvPAdV fp
15
ADC Measurement Techniques – The Histogram MethodSimple Sine Fitting
The simplest way to estimate the parameters A and d is to assume the outmost excited decision levels are correct
If l and h are respectively the lowest and highest non-empty code bins, we assume Vl+1 and Vh-1 to be correct. (Reminder- V is in LSB units)
)1(cos)(cos
)(cos)1()1(cos)1(cos)(cos
1
hchlch
lchhhchld
hchlch
lhA
pppp
pp
Next All the decision levels can be estimated and then the INL and DNL
The ENOB and SNDR parameters can also be estimate from the histogram data
For accurate results a more sophisticated sine fitting method has to be used that uses the whole of the information in the histogram.
hhchAdV
llchAdV
h
l
)1(cos
1)(cos1
pp
16
ADC Calibration Techniques – Definition of the Problem
ADC calibration techniques aim to improve the overall performance of a given ADC by means of added circuitry
Raw Output
ADC
Calibration System
N Bit
Corrected Output
M >= N Bitvin
Reference Control
17
Limitations of ADC Calibration Techniques
Calibration techniques can not cancel:
- Random effects (thermal noise, jitter)
- Quantization noise (an 8 bit ADC can not become 9 bit after
calibration)
- Fast events (spikes, metastability)
18
Classification of ADC Calibration Techniques (1)
By the domain of the correction:
- Analog calibration techniques
- Adjust reference voltages
- Adjust components (capacitors, resistors)
- Dynamic matching techniques
- Digital calibration techniques
- No adjustment is performed on the analog circuitry
- Some analog calibration source is always needed
(By the nature of the problem any calibration technique is a mixed-
mode circuit)
19
By the time the correction is performed:- Background calibration techniques
- Calibration circuits run in parallel and not interfering with the normal functioning of the ADC
- Off-line calibration techniques- Require a specially allocated training mode- Offline calibration can be performed
- At fabrication (expensive, done at testing time)
- At power-up
- Periodically (but it incurs inactive times)
Classification of ADC Calibration Techniques (2)
20
By the nature of the underlying ADC model :
- Static calibration
- The ADC is described by a static (memory-less) non-linear function
- Dynamic (slope dependent) impairments can not be corrected
- Dynamic calibration
- The ADC is described by a non-linear dynamic system
- Increased complexity of the calibration technique
Classification of ADC Calibration Techniques (3)
21
Analog Calibration by Capacitor Trimming (in pipe-line ADC)
The Capacitor Trimming Technique by Capacitor Divider Network
Comparator Based Trimming Technique Delta-Sigma Trimming Technique Limitations and Benefits of Trimming
22
Capacitor Divider (1)
In practice several taps are built and the trimming is done with a resolution of up to 3-4 bits C
C1 C2
Ct
b 0
1
Ceq
Vt
221
21
21
21
2121
21
21
21
CC
CCb
CC
CCC
CCCCC
CCb
CC
CCCCeq t
t
t
23
Capacitor Divider (2)
Parasitic capacitances on the floating nodes increase the effect of parasitic capacitances to the substrate
Depending on technology, non-discharged floating nodes can be a problem
The additional switches used for trimming will increase the leakage problems
C
C1 C2
Ct
b 0
1
Ceq
Vt
Cp
C2+bCt
Ceq C
C1*Cp
C1+C2+bCt+CpC1*(C2+bCt)
C1+C2+bCt+Cp
C2*Cp
C1+C2+bCt+Cp
24
Comparator Based Trimming Technique
The comparator can use the stage amplifier
Offset Cancellation is needed This is an off-line technique
-
+
F2
F1Cf
CiVa
F1 CompF2
F1
Vref
Vref
Search Engine(Logic)
CiCf
CiCfVrefVa
At the end of phase F2:
Y.-M. Lin, B. Kim, and P. R. Gray, “A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-um
CMOS,” IEEE J. Solid-State Circuits, vol. 26, pp. 628–636, Apr. 1991
25
Delta-Sigma Based Trimming Technique
Calibration only when
The error term in this case has a constant sign
This is an fully background technique
1Ctrl if)1()2(11
20Ctrl if)1()2(
VrefbVinVoutVrefb
VinVout
VrefbVinVout
Seung-Tak Ryu, Sourja Ray, Bang-Sup Song, Gyu-Hyeong Cho, and Kanti Bacrania ,"A 14-b Linear Capacitor Self-Trimming Pipelined ADC", IEEE Journal of Solid-State Circuits, VOL. 39, NO. 11, November 2004
-
+
F2
F1
F1
F2
Vinbi*Vref
From DAC
C
C*(1+)Va
VoutF1
Ctrl=(bi=1)*(PRN=1)
Ctrl
Ctrl
Ctrl
Ctrl
bi = -1, 0, +1PRN = -1, +1
bi
PRNGenerator
Delta-SigmaPolarity Detector
And Control
bi
0ib
26
Benefits & Limitations of Trimming
If we implement a 3 bit trimming we can gain ~ 2 bits over the matching given by the capacitors
The price of trimming is paid in- Complexity- Power- Increased sensitivity to parasitic capacitance / leakage
Trimming should be used only for the first stages of the pipe-line ADC to get closer to the thermal limited capacitor size
27
Digital Calibration by the Precision Bootstrapping Algorithm (in pipe-line ADC) (1)
- This is an off-line digital static calibration technique
- The analog calibration source is a DC voltage - advantage
- The control machine for the training sequence is complicated
E. G. Soenen and R. L. Geiger, “An architecture and an algorithm for fully digital correction of monolithic pipelined ADC’s,” IEEE Trans. Circuits
Syst. II, vol. 42, pp. 143–153, Mar. 1995.
Vin
Stage L
Vres1
Vresi+1
Nout
Enc
oder
Vref1
Vrefk
Vref2
+
-gi
ni (-ki/2, ki/2)
Vdac (ki+1 levels)
Flash ki comparators
T&H Amplifier
nL
VresL
Stage 1Stage L-1
nL-1
VresL-1
Stage i
ni n1
Vresi
Vresi
Stage i
DAC
Digital Correction
Calibrate
ncal
Vfix
wL
LUT LUTLUTLUT
w1wiwL-1
28
Effect and Limitations of Fully Digital Calibration
The output of the ADC is a higher resolution representation but the decision points are the same as for an un-calibrated ADC.
Calibrated
Uncalibrated
Nout
Vin0
1
2
3
4
5
6
7
Decision Points
v0 v7v6v5v4v3v2v1
INL is improved but DNL not and even non-monotone errors can occur.
Digital Calibration by the Precision Bootstrapping Algorithm (in pipe-line ADC) (2)
29
Digital Calibration with State Space Error Table
ADC Z-1Vin
LookupTable (LUT)
Address2N bits N
out(
i)
Nou
t(i-1
)
Nout_corrected
N bits
> N bits
Correction Phase- This is an off-line digital
dynamic calibration technique
- The analog calibration source is a known-statistics signal source
- Theoretically higher order dynamic calibrations are possible
J . Tsimbinos K,.V. Lever “Improved error-table compensation of A/D converters” IEE Proc.-Circuits Devices Syst., Vol. 144, No 6, December 1997
ADC Z-1
LookupTable (LUT)
Address2N bitsN
out(i
)
Nou
t(i-1
)
N_estimate
N bits
> N bits
Calibration Source
Analysis Engine
Calibration Phase
30
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