1 aerospace data storage and processing systems seakr engineering proprietary information seakr...

1

Aerospace Data Storage and Processing Systems

SEAKR Engineering, Inc.

SEAKR Engineering Proprietary Information

SEAKR Engineering Inc. SEAKR Engineering Inc.

On-Board ProcessingOn-Board Processing

SEAKR Engineering Inc. SEAKR Engineering Inc.

On-Board ProcessingOn-Board Processing

2




ReConfigurable Computing, SEAKR’s Core Business

RCC technology is a core technology for SEAKR engineering

• We are dedicated to developing state of the art RCC and other processing systems.

• Leverage large diverse customer base– Radiation testing of components– Prevent obsolescence– Fastest development times– Lowest cost systems– High level of integration

– Reduced SWaP• Creates a sustainable system

– Eliminate Stove pipes

Developing industry partners for using our RCC technology across subsystems.

• Flexible platforms that enable reuse among subsystems.

• Routers, COMSEC, Telecom, SDR, OBP

Payload Data

Processor

COMSEC

Routers

Telecom

Accelerators

Software

Defined Radio

Mass Data

Storage

3




SEAKR Processing Concept

Objectives• Provide sustainable processing

platforms for users.– SEAKR algorithms

– Users algorithms

– SEAKR platforms

– Users platforms

• Provide SEE mitigation technologies for users of SEAKR platforms.

– IP cores

– System design techniques

– Radiation characterization of components

• Provide technical customer support that specializes in the specific needs of the space community

Hardware Architecture

Radiation

Testing

SEE

MitigationCores

Platform

(SEAKR, Customer)

Algorithms

System

Application

Reliability

Testing

Board level

Or Integrated

System

SEAKR,

Customer, or

Combination

Thermal

Management

Structural

Design

Software

API

SEAKR

Core

Technology

POL

Converters

Integrated and cost effective solutions

Provide a competitive advantage to users

4




4 Generations of RCC Platforms

Four Generations of RCC Platforms

V1, V2, V2P/-X, V4

V1-RCC

V2-RCC

NT-RCC-R

NT-RCC

COP A

Xilinx V4

DDRII

FlashFlashFlash

Power

Switch

PCI-PCI

Bridge /

Config

COP

SelectMap

COP B

Xilinx V4

(NIC)DDR II

SDRAM

512 Mbyte

Serial RIO 4X3.125 Gbps

NIC SelectMap

DDR II

SDRAM

512 Mbyte

High Speed MezzHigh Speed Mezz

V4-RCC

5




SEAKR RCC Development

Virtex-I RCC product• Four Xilinx XQVR1000 FPGA CO-Processors• 256 Mbytes of EDAC R-S Protected SDRAM for each COP• Configuration RAM SEU detection and correction• Non-Volatile memory for 32 different configurations

– Symmetrical FPGA designs

• Internal PCI bus with PMC slot• Cop Interconnect Bus• Read and write COP configurations via cPCI• cPCI 32/64 33 Mhz, 6U form factor• LVDS I/O (Discrete, Serializer/De-serializer)

– SERDES capable of 8 Gbps

Adopted by GSFC for their laser altimeter program

6




Virtex I RCC Block Diagram

COP D

Xilinx V1000

COP C

Xilinx V1000

COP B

Xilinx V1000

SD

RA

M

256M

byt

es

COP A

Xilinx V1000

SD

RA

M

256M

byt

es

SD

RA

M

256M

byt

es

SD

RA

M

256M

byt

es

Config

Control

SRAM

FlashFlashFlash

Power

Switch PCI-PCI

Bridge

LV

DS

SE

RD

ES

LV

DS

SE

RD

ES

LV

DS

SE

RD

ES

LV

DS

SE

RD

ES

cPCI

PCI

SelectMap

Common Bus

Port A Port B Port C Port D

PMC

J1 J2 J3

7




Virtex II RCC Block Diagram

SRAM

FlashFlashFlash

Power

Switch

PCI-PCI

Bridge /

Config

J1 J2

cPCI

Internal PCISelectMap

COP A

Xilinx V2

Ports A1&A2

SERDES A1

SERDES A2

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

mezz

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

mezz

COP B

Xilinx V2

Ports B1&B2

SERDES B1

SERDES B2

COP C

Xilinx V2

Ports C1&C2

SERDES C1

SERDES C2

COP D

Xilinx V2

Ports D1&D2

SERDES D1

SERDES D2

LVDS Ring Bus

J3

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

mezz

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

mezz

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

mezz

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

mezz

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

mezz

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

SD

RA

M

32M

x 8

0

mezz

Common Interconnect Bus

J8

8




V2-RCC Four CoProcessors (COPS)

• Xilinx XC2V6000 CO-Processors (24M Programmable gates) – 1144 CGA Package

• 6 Gb SDRAM per COP (on board and mezzanine).

• 25 GFLOPs Radiation Tolerant System by Design (RTSD)

• FPGA mitigation techniques

• SEU and TID radiation techniques for memories

• Radiation Tolerant power conversion Non-Volatile memory for 32 different configurations Data Buses

• Internal PCI bus (~1Gbps)

• Shared COP Interconnect Bus (~4.224 Gbps)

• Pipelined COP bus (~10.0 Gbps) – LVDS

• cPCI 32/64 33/66 Mhz LVDS SERDES (24 Gbps aggregate bandwidth)

• TX 12 Gbps. RX 12 Gbps Mezzanine Card

• 12 Gbps data rates

• 4 Gb SDRAM card with aggregate bandwidth of 19.2 Gbps.

9




Network Based RCC

SEAKR has performed a trade study on network based RCC processing architectures.

Our Network based design leverages much of our existing architecture and interface.

• Builds on our existing V2 RCC architecture but changes some of the physical partitioning due to greater Actel AX device capability and adds an 6 to 8 port network switch

• PCI interface and functionality remains intact.• Configuration scrubbing and SEE mitigation is identical• Uses existing interface GUI and drivers for configuration control and

FPGA communication.

High Speed Serial I/O Network protocol

10




NT-RCC-R Block Diagram

COP A

Xilinx V2Pro

DDRII

FlashFlashFlash

Power

Switch

PCI-PCI

Bridge /

Config

J1 J2 J3

cPCI

PCI

COP

SelectMap

RIO A

6 Port

Switch

Xilinx V2Pro

(NIC)

DDR II

SDRAM

512 Mbyte

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36


Parallel

RIO


NIC SelectMap

11




SEAKR NT-RCC-R

NT RCC-R

Network IF Chip (NIC)Parallel Rapid IO Port(4) 3.125Gbps serial links off board(4) 3.125Gbps serial links to COP

Parallel RIO Port

Configuration Controller/PCI-PCI Bridge

Up to 1Gbit NV memory

512MBytes

DDRII SDRAM

Quad Data Rate SRAMs

CO-Processor (COP)2VP70~8Mbits embedded RAMHSIO to NIC2 PPC 405 processors

HSIO

12




NT-RCC Block Diagram

COP D

XilinxV2Pro

COP C

Xilinx V2Pro

COP B

Xilinx V2Pro

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36

COP A

Xilinx V2Pro

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36

DDRII

FlashFlashFlash

Power

Switch

PCI-PCI

Bridge /

Config

J1 J2 J3

cPCI

PCI

COP

SelectMap

Common Bus

RIO A RIO B

6 Port

Switch

Xilinx V2Pro

(NIC)

DDR II

SDRAM

512 Mbyte

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36

QD

R S

RA

M

1M x

36


4X3.125 Gbps

Parallel

RIO Parallel

RIO


NIC SelectMap

4X3.125 Gbps4X3.125 Gbps

13




NT-RCC Layout

SEAKR NT-RCC

24 Layer board MicroVias, blind vias, via-in-padHigh speed 3.125 Gbps Serial links82 pages of schematic capture10 weeks of PCB layout time

14




CGA Qualification Developments

Virtex II CGA Qual CF1144• GSFC Program• 52 boards each with four Xilinx

Virtex2 CF1144 BGA packages• 283 thermal cycles from 0 to 100 C• Vibration and shock testing • 35mm x 35mm, 1144 pin CGA,

1mm pitch.

MPC7457 CGQ Qual• 18 boards with 6 CGA

packages/board. • 456 thermal cycles -40C to 95C • 29mm x 29mm, 483 pin, 1.27mm

BGA pitch

Plastic BGA

ceramic CGA

micro BGA

15




Thermal Management

Design supports 8 watts per FPGA without heat pipes or other active cooling

Enclosure Fitting

Thermal Plate (Integral part of Fitting)

CGA

Thermal Plug

Copper Shims

Plug Height

CGA Depth

T-Putty 504

CGA

.007” Thick Etched Shim

Stack

Thermal “Plug”

Enclosure Fitting

PBA

Thermal Plate Feature

16




Low Voltage High Current DC/DC Converters

SEAKR has also developed a Point of Load power supply for low voltage, high current systems.

• Programmable voltage down to 1.0V at 12A

• 85% efficiency• Mezzanine card for design reuse and

flexibility• Originally developed for G4 SBC

VPC Back ViewPOL

Power Supply

17




PCI Chassis Application

Client application to interface with SBC Determines PCI chassis configuration Sends RCC commands to the SBC Used for hardware debug and FPGA configuration

18




RCC Built-in Self Test Application

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