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An adaptable FPGA-based System for Regular Expression Matching

Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C.

Authors: Ivano Bonesana, Marco Paolieri, Marco D. Santambrogio

Publisher: DATE (Design, Automation and Test in Europe) 2008

Present: Chung-Chan Wu

Date: April 23 2008

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Outline

Introduction ReCPU Framework Flow ReCPU Instruction Structure Architecture Description Experimental Result

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Introduction

RE： Regular Expression We do not build either Deterministic nor Nondetermin

istic Finite Automaton of the RE The architecture is optimized to execute computation

s in a parallel and pipelined way VLIW design style (Very long instruction word ) We developed a compiler to translate REs into bitwis

e instructions.

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ReCPU Framework Flow

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Regular Expression

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Compilation Phase

By modifying the number of clusters (parameters) in the ReCPU • Performance

• Power

• area

The compiler • written in Python

• starting from the high level description of the RE

• generates the files

• be loaded in the instruction memory

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ReCPU Instruction Structure

Operators like * and + correspond to loop instructions. Nested parentheses (e.g. (((ab)*(c|d))|(abc))) are managed as function calls. An open parenthesis inside an RE is a call instruction while the closed one i

s a return instruction.

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Architecture Description

ReCPU uses two separate memories: • Data memory for the input text

• instruction memory for the RE

In the Data Path are placed all the different parallel comparators organized in Clusters.

Cluster Width ： The total number of elements in a cluster

The processor is composed of several Clusters - the total number is indicated as NCluster

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Block Diagram of ReCPU (4 Clusters)

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Comparator Cluster

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Finite State Machine of the Control Unit

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Experimental Result

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Experimental Result