1 b. bruidegom chapter five single cycle & multicycle implementation
TRANSCRIPT
![Page 1: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/1.jpg)
1B. Bruidegom
Chapter Five
Single Cycle & Multicycle Implementation
![Page 2: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/2.jpg)
2B. Bruidegom
MIPS Single Cycle Implementation
MemtoReg
MemRead
MemWrite
ALUOp
ALUSrc
RegDst
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
RegWrite
4
16 32Instruction [15– 0]
0Registers
WriteregisterWritedata
Writedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Signextend
ALUresult
Zero
Datamemory
Address Readdata M
ux
1
0
Mux
1
0
Mux
1
0
Mux
1
Instruction [15– 11]
ALUcontrol
Shiftleft 2
PCSrc
ALU
Add ALUresult
32 bit Harvard machine32 bit Instruction Memory
32 bit Data Memory
Separate memory
![Page 3: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/3.jpg)
3B. Bruidegom
MIPS Single Cycle Implementation
• Verschillen met de Harvard machine• For MIPS, a word is 32 bits or 4 bytes.
MemtoReg
MemRead
MemWrite
ALUOp
ALUSrc
RegDst
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
RegWrite
4
16 32Instruction [15– 0]
0Registers
WriteregisterWritedata
Writedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Signextend
ALUresult
Zero
Datamemory
Address Readdata M
ux
1
0
Mux
1
0
Mux
1
0
Mux
1
Instruction [15– 11]
ALUcontrol
Shiftleft 2
PCSrc
ALU
Add ALUresult
![Page 4: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/4.jpg)
4B. Bruidegom
MIPS Single Cycle Implementation
• Verschillen met de Harvard machine• For MIPS, a word is 32 bits or 4 bytes.• Hoe implementeer je: data = data << 2 ?
MemtoReg
MemRead
MemWrite
ALUOp
ALUSrc
RegDst
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
RegWrite
4
16 32Instruction [15– 0]
0Registers
WriteregisterWritedata
Writedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Signextend
ALUresult
Zero
Datamemory
Address Readdata M
ux
1
0
Mux
1
0
Mux
1
0
Mux
1
Instruction [15– 11]
ALUcontrol
Shiftleft 2
PCSrc
ALU
Add ALUresult
![Page 5: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/5.jpg)
5B. Bruidegom
MIPS Single Cycle Implementation
• Verschillen met de Harvard machine• Sign extension
MemtoReg
MemRead
MemWrite
ALUOp
ALUSrc
RegDst
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
RegWrite
4
16 32Instruction [15– 0]
0Registers
WriteregisterWritedata
Writedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Signextend
ALUresult
Zero
Datamemory
Address Readdata M
ux
1
0
Mux
1
0
Mux
1
0
Mux
1
Instruction [15– 11]
ALUcontrol
Shiftleft 2
PCSrc
ALU
Add ALUresult
![Page 6: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/6.jpg)
6B. Bruidegom
MIPS Single Cycle Implementation
• Verschillen met de Harvard machine• R-type en I-type instucties
MemtoReg
MemRead
MemWrite
ALUOp
ALUSrc
RegDst
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
RegWrite
4
16 32Instruction [15– 0]
0Registers
WriteregisterWritedata
Writedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Signextend
ALUresult
Zero
Datamemory
Address Readdata M
ux
1
0
Mux
1
0
Mux
1
0
Mux
1
Instruction [15– 11]
ALUcontrol
Shiftleft 2
PCSrc
ALU
Add ALUresult
![Page 7: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/7.jpg)
7B. Bruidegom
• simple instructions all 32 bits wide
• very structured, no unnecessary baggage
op rs rt rd shamt funct
op rs rt/rd 16 bit constant/address
op 26 bit address
R
I
J
MIPS only three instruction formats
shamt = shift amount
6 5 5 5 5 6
![Page 8: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/8.jpg)
8B. Bruidegom
MIPS Single Cycle Implementation
• Verschillen met de Harvard machine
• Jump instructie geimplementeerd?
MemtoReg
MemRead
MemWrite
ALUOp
ALUSrc
RegDst
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
RegWrite
4
16 32Instruction [15– 0]
0Registers
WriteregisterWritedata
Writedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Signextend
ALUresult
Zero
Datamemory
Address Readdata M
ux
1
0
Mux
1
0
Mux
1
0
Mux
1
Instruction [15– 11]
ALUcontrol
Shiftleft 2
PCSrc
ALU
Add ALUresult
![Page 9: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/9.jpg)
9B. Bruidegom
MIPS Single Cycle Implementation
• Verschillen met de Harvard machine• Jump instructie. Extra mux. nodig. Welke bits van instruction register?
MemtoReg
MemRead
MemWrite
ALUOp
ALUSrc
RegDst
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
RegWrite
4
16 32Instruction [15– 0]
0Registers
WriteregisterWritedata
Writedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Signextend
ALUresult
Zero
Datamemory
Address Readdata M
ux
1
0
Mux
1
0
Mux
1
0
Mux
1
Instruction [15– 11]
ALUcontrol
Shiftleft 2
PCSrc
ALU
Add ALUresult
Mux
![Page 10: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/10.jpg)
10B. Bruidegom
MIPS Single Cycle Implementation
• Verschillen met de Harvard machine• ALU control
MemtoReg
MemRead
MemWrite
ALUOp
ALUSrc
RegDst
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Instruction [20– 16]
Instruction [25– 21]
Add
Instruction [5– 0]
RegWrite
4
16 32Instruction [15– 0]
0Registers
WriteregisterWritedata
Writedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Signextend
ALUresult
Zero
Datamemory
Address Readdata M
ux
1
0
Mux
1
0
Mux
1
0
Mux
1
Instruction [15– 11]
ALUcontrol
Shiftleft 2
PCSrc
ALU
Add ALUresult
2 bits
4 bits
![Page 11: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/11.jpg)
11B. Bruidegom
Control
• Selecting the operations to perform (ALU, read/write, etc.)
• Controlling the flow of data (multiplexor inputs)
• Information comes from the 32 bits of the instruction
• Example:
add $8, $17, $18 Instruction Format:
000000 10001 10010 01000 00000 100000
op rs rt rd shamt funct
• ALU's operation based on instruction type and function code
![Page 12: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/12.jpg)
12B. Bruidegom
What’s wrong with our CPI=1 processor?
• Long Cycle Time
– All instructions take as much time as the slowest
– Real memory slower than idealized memory
• Duplicate Resources
PC Inst Memory mux ALU Data Mem mux
PC Reg FileInst Memory mux ALU mux
PC Inst Memory mux ALU Data Mem
PC Inst Memory cmp mux
Reg File
Reg File
Reg File
Arithmetic & Logical
Load
Store
Branch
Critical Path
setup
setup
CPI (Clock cycles Per Instruction = 1 Single-Cycle machine
![Page 13: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/13.jpg)
13B. Bruidegom
• Instruction Fetch
• Instruction Decode and Register Fetch
• Execution, Memory Address Computation, or Branch Completion
• Memory Access or R-type instruction completion
• Write-back step
INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!
Five Execution Steps
![Page 14: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/14.jpg)
14B. Bruidegom
Where we are headed
• Single Cycle Problems:– what if we had a more complicated instruction like floating point?– wasteful of area
• One Solution:– use a “smaller” cycle time– have different instructions take different numbers of cycles– a “multicycle” datapath:
PC
Memory
Address
Instructionor data
Data
Instructionregister
Registers
Register #
Data
Register #
Register #
ALU
Memorydata
register
A
B
ALUOut
Von Neumann machine
Common memory for instruction & data
![Page 15: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/15.jpg)
15B. Bruidegom
PC
Memory
Address
Instructionor data
Data
Instructionregister
Registers
Register #
Data
Register #
Register #
ALU
Memorydata
register
A
B
ALUOut
![Page 16: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/16.jpg)
16B. Bruidegom
• We will be reusing functional units
– ALU used to compute address and to increment PC
– Memory used for instruction and data
• Our control signals will not be determined solely by instruction
– e.g., what should the ALU do for a “subtract” instruction?
• We’ll use a finite state machine for control
Multicycle Approach
![Page 17: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/17.jpg)
17B. Bruidegom
Five Execution Steps
• Instruction Fetch• Instruction Decode and Register Fetch• Execution, Memory Address Computation, or Branch Completion• Memory Access or R-type instruction completion• Write-back step
PC
Memory
Address
Instructionor data
Data
Instructionregister
Registers
Register #
Data
Register #
Register #
ALU
Memorydata
register
A
B
ALUOut
![Page 18: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/18.jpg)
18B. Bruidegom
Five Execution Steps
• Instruction Fetch• Instruction Decode and Register Fetch• Execution, Memory Address Computation, or Branch Completion• Memory Access or R-type instruction completion• Write-back step
PC
Memory
Address
Instructionor data
Data
Instructionregister
Registers
Register #
Data
Register #
Register #
ALU
Memorydata
register
A
B
ALUOut
![Page 19: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/19.jpg)
19B. Bruidegom
Five Execution Steps
• Instruction Fetch• Instruction Decode and Register Fetch• Execution, Memory Address Computation, or Branch Completion• Memory Access or R-type instruction completion• Write-back step
PC
Memory
Address
Instructionor data
Data
Instructionregister
Registers
Register #
Data
Register #
Register #
ALU
Memorydata
register
A
B
ALUOut
![Page 20: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/20.jpg)
20B. Bruidegom
Five Execution Steps
• Instruction Fetch• Instruction Decode and Register Fetch• Execution, Memory Address Computation, or Branch Completion• Memory Access or R-type instruction completion• Write-back step
PC
Memory
Address
Instructionor data
Data
Instructionregister
Registers
Register #
Data
Register #
Register #
ALU
Memorydata
register
A
B
ALUOut
![Page 21: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/21.jpg)
21B. Bruidegom
Five Execution Steps
• Instruction Fetch• Instruction Decode and Register Fetch• Execution, Memory Address Computation, or Branch Completion• Memory Access or R-type instruction completion• Write-back step
PC
Memory
Address
Instructionor data
Data
Instructionregister
Registers
Register #
Data
Register #
Register #
ALU
Memorydata
register
A
B
ALUOut
![Page 22: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/22.jpg)
22B. Bruidegom
• Finite state machines:– a set of states and – next state function (determined by current state and the input)– output function (determined by current state and possibly input)
• We’ll use a Moore machine (output based only on current state)
Review: finite state machines
Next-statefunction
Current state
Clock
Outputfunction
Nextstate
Outputs
Inputs
Bladz C-22
![Page 23: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/23.jpg)
23B. Bruidegom
Review: finite state machines
Next-statefunction
Current state
Clock
Outputfunction
Nextstate
Outputs
Inputs
Bladz C-22
AddrCtl
Outputs
PLA or ROM
State
Address select logic
Op
[5–
0]
Adder
Instruction registeropcode field
1
Control unit
Input
PCWritePCWriteCondIorD
MemtoRegPCSourceALUOpALUSrcBALUSrcARegWriteRegDst
IRWrite
MemReadMemWrite
BWrite
![Page 24: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/24.jpg)
24B. Bruidegom
• Break up the instructions into steps, each step takes a cycle– balance the amount of work to be done– restrict each cycle to use only one major functional unit
• At the end of a cycle– store values for use in later cycles (easiest thing to do)– introduce additional “internal” registers
Multicycle Approach
Shiftleft 2
PC
Memory
MemData
Writedata
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Mux
0
1
Mux
0
1
4
Instruction[15– 0]
Signextend
3216
Instruction[25– 21]
Instruction[20– 16]
Instruction[15– 0]
Instructionregister
1 Mux
0
3
2
Mux
ALUresult
ALUZero
Memorydata
register
Instruction[15– 11]
A
B
ALUOut
0
1
Address
![Page 25: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/25.jpg)
25B. Bruidegom
• Instruction Fetch
• Instruction Decode and Register Fetch
• Execution, Memory Address Computation, or Branch Completion
• Memory Access or R-type instruction completion
• Write-back step
INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!
Five Execution Steps
![Page 26: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/26.jpg)
26B. Bruidegom
• Use PC to get instruction and put it in the Instruction Register.
• Increment the PC by 4 and put the result back in the PC.
• Can be described succinctly using RTL "Register-Transfer Language"
IR = Memory[PC];PC = PC + 4;
Can we figure out the values of the control signals?
What is the advantage of updating the PC now?
Step 1: Instruction Fetch
![Page 27: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/27.jpg)
27B. Bruidegom
Multicycle Approach
Shiftleft 2
PC
Memory
MemData
Writedata
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Mux
0
1
Mux
0
1
4
Instruction[15– 0]
Signextend
3216
Instruction[25– 21]
Instruction[20– 16]
Instruction[15– 0]
Instructionregister
1 Mux
0
3
2
Mux
ALUresult
ALUZero
Memorydata
register
Instruction[15– 11]
A
B
ALUOut
0
1
Address
![Page 28: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/28.jpg)
28B. Bruidegom
• Read registers rs and rt in case we need them
• Compute the branch address in case the instruction is a branch
• RTL:
A = Reg[IR[25-21]];B = Reg[IR[20-16]];ALUOut = PC + (sign-extend(IR[15-0]) << 2);
• We aren't setting any control lines based on the instruction type (we are busy "decoding" it in our control logic)
Step 2: Instruction Decode and Register Fetch
![Page 29: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/29.jpg)
29B. Bruidegom
Multicycle Approach
Shiftleft 2
PC
Memory
MemData
Writedata
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Mux
0
1
Mux
0
1
4
Instruction[15– 0]
Signextend
3216
Instruction[25– 21]
Instruction[20– 16]
Instruction[15– 0]
Instructionregister
1 Mux
0
3
2
Mux
ALUresult
ALUZero
Memorydata
register
Instruction[15– 11]
A
B
ALUOut
0
1
Address
![Page 30: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/30.jpg)
30B. Bruidegom
• ALU is performing one of three functions, based on instruction type
• Memory Reference:
ALUOut = A + sign-extend(IR[15-0]);
• R-type:
ALUOut = A op B;
• Branch:
if (A==B) PC = ALUOut;
Step 3 (instruction dependent)
![Page 31: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/31.jpg)
31B. Bruidegom
Multicycle Approach
Shiftleft 2
PC
Memory
MemData
Writedata
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Mux
0
1
Mux
0
1
4
Instruction[15– 0]
Signextend
3216
Instruction[25– 21]
Instruction[20– 16]
Instruction[15– 0]
Instructionregister
1 Mux
0
3
2
Mux
ALUresult
ALUZero
Memorydata
register
Instruction[15– 11]
A
B
ALUOut
0
1
Address
![Page 32: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/32.jpg)
32B. Bruidegom
• Loads and stores access memory
MDR = Memory[ALUOut];or
Memory[ALUOut] = B;
• R-type instructions finish
Reg[IR[15-11]] = ALUOut;
The write actually takes place at the end of the cycle on the edge
Step 4 (R-type or memory-access)
![Page 33: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/33.jpg)
33B. Bruidegom
Multicycle Approach
Shiftleft 2
PC
Memory
MemData
Writedata
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Mux
0
1
Mux
0
1
4
Instruction[15– 0]
Signextend
3216
Instruction[25– 21]
Instruction[20– 16]
Instruction[15– 0]
Instructionregister
1 Mux
0
3
2
Mux
ALUresult
ALUZero
Memorydata
register
Instruction[15– 11]
A
B
ALUOut
0
1
Address
![Page 34: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/34.jpg)
34B. Bruidegom
• Reg[IR[20-16]]= MDR;
Write-back step
![Page 35: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/35.jpg)
35B. Bruidegom
Summary:
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction for branches
Action for jumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)
Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completion
Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
![Page 36: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/36.jpg)
36B. Bruidegom
• How many cycles will it take to execute this code?
lw $t2, 0($t3)lw $t3, 4($t3)beq $t2, $t3, Label #assume notadd $t5, $t2, $t3sw $t5, 8($t3)
Label: ...
• What is going on during the 8th cycle of execution?• In what cycle does the actual addition of $t2 and $t3 takes place?
Simple Questions
![Page 37: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/37.jpg)
37B. Bruidegom
• Value of control signals is dependent upon:
– what instruction is being executed
– which step is being performed
• Use the information we’ve acculumated to specify a finite state machine
– specify the finite state machine graphically, or
– use microprogramming
• Implementation can be derived from specification
Implementing the Control
![Page 38: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/38.jpg)
• How many state bits will we need?
Graphical Specification of FSM
PCWritePCSource = 10
ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCWriteCond
PCSource = 01
ALUSrcA =1ALUSrcB = 00ALUOp= 10
RegDst = 1RegWrite
MemtoReg = 0
MemWriteIorD = 1
MemReadIorD = 1
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
RegDst = 0RegWrite
MemtoReg =1
ALUSrcA = 0ALUSrcB = 11ALUOp = 00
MemReadALUSrcA = 0
IorD = 0IRWrite
ALUSrcB = 01ALUOp = 00
PCWritePCSource = 00
Instruction fetchInstruction decode/
register fetch
Jumpcompletion
BranchcompletionExecution
Memory addresscomputation
Memoryaccess
Memoryaccess R-type completion
Write-back step
(Op = 'LW') or (Op = 'SW') (Op = R-type)
(Op
= 'B
EQ')
(Op
= 'J
')
(Op = 'SW
')
(Op
= 'L
W')
4
01
9862
753
Start
![Page 39: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/39.jpg)
39B. Bruidegom
• Implementation:
Finite State Machine for Control
PCWrite
PCWriteCond
IorD
MemtoReg
PCSource
ALUOp
ALUSrcB
ALUSrcA
RegWrite
RegDst
NS3NS2NS1NS0
Op5
Op4
Op3
Op2
Op1
Op0
S3
S2
S1
S0
State register
IRWrite
MemRead
MemWrite
Instruction registeropcode field
Outputs
Control logic
Inputs
![Page 40: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/40.jpg)
40B. Bruidegom
PLA Implementation
• If I picked a horizontal or vertical line could you explain it?Op5
Op4
Op3
Op2
Op1
Op0
S3
S2
S1
S0
IorD
IRWrite
MemReadMemWrite
PCWritePCWriteCond
MemtoRegPCSource1
ALUOp1
ALUSrcB0ALUSrcARegWriteRegDstNS3NS2NS1NS0
ALUSrcB1ALUOp0
PCSource0
![Page 41: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/41.jpg)
41B. Bruidegom
• ROM = "Read Only Memory"– values of memory locations are fixed ahead of time
• A ROM can be used to implement a truth table– if the address is m-bits, we can address 2m entries in the ROM.– our outputs are the bits of data that the address points to.
m is the "heigth", and n is the "width"
ROM Implementation
m n
0 0 0 0 0 1 10 0 1 1 1 0 00 1 0 1 1 0 00 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 11 1 0 0 1 1 01 1 1 0 1 1 1
![Page 42: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/42.jpg)
42B. Bruidegom
• How many inputs are there?6 bits for opcode, 4 bits for state = 10 address lines(i.e., 210 = 1024 different addresses)
• How many outputs are there?16 datapath-control outputs, 4 state bits = 20 outputs
• ROM is 210 x 20 = 20K bits (and a rather unusual size)
• Rather wasteful, since for lots of the entries, the outputs are the same
— i.e., opcode is often ignored
ROM Implementation
![Page 43: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/43.jpg)
43B. Bruidegom
• Break up the table into two parts
— 4 state bits tell you the 16 outputs, 24 x 16 bits of ROM
— 10 bits tell you the 4 next state bits, 210 x 4 bits of ROM
— Total: 4.3K bits of ROM
• PLA is much smaller
— can share product terms
— only need entries that produce an active output
— can take into account don't cares
• Size is (#inputs #product-terms) + (#outputs #product-terms)
For this example = (10x17)+(20x17) = 460 PLA cells
• PLA cells usually about the size of a ROM cell (slightly bigger)
ROM vs PLA
![Page 44: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/44.jpg)
44B. Bruidegom
• Complex instructions: the "next state" is often current state + 1
Another Implementation Style
AddrCtl
Outputs
PLA or ROM
State
Address select logic
Op
[5–
0]
Adder
Instruction registeropcode field
1
Control unit
Input
PCWritePCWriteCondIorD
MemtoRegPCSourceALUOpALUSrcBALUSrcARegWriteRegDst
IRWrite
MemReadMemWrite
BWrite
![Page 45: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/45.jpg)
45B. Bruidegom
DetailsDispatch ROM 1 Dispatch ROM 2
Op Opcode name Value Op Opcode name Value000000 R-format 0110 100011 lw 0011000010 jmp 1001 101011 sw 0101000100 beq 1000100011 lw 0010101011 sw 0010
State number Address-control action Value of AddrCtl
0 Use incremented state 31 Use dispatch ROM 1 12 Use dispatch ROM 2 23 Use incremented state 34 Replace state number by 0 05 Replace state number by 0 06 Use incremented state 37 Replace state number by 0 08 Replace state number by 0 09 Replace state number by 0 0
State
Op
Adder
1
PLA or ROM
Mux3 2 1 0
Dispatch ROM 1Dispatch ROM 2
0
AddrCtl
Address select logic
Instruction registeropcode field
![Page 46: 1 B. Bruidegom Chapter Five Single Cycle & Multicycle Implementation](https://reader035.vdocument.in/reader035/viewer/2022062620/551a75bf550346b52d8b5151/html5/thumbnails/46.jpg)
46B. Bruidegom
MicroprogrammingBehoort niet tot de stof
• What are the “microinstructions” ?
PCWritePCWriteCondIorD
MemtoRegPCSourceALUOpALUSrcBALUSrcARegWrite
AddrCtl
Outputs
Microcode memory
IRWrite
MemReadMemWrite
RegDst
Control unit
Input
Microprogram counter
Address select logic
Op[
5–
0]
Adder
1
Datapath
Instruction registeropcode field
BWrite