1 chapter 8 the operational amplifier (part i) ~ using pspice the ideal op amp noninverting ideal op...
TRANSCRIPT
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Chapter 8 The Operational Amplifier (Part I) ~ Using PSpice
The Ideal Op Amp Noninverting Ideal Op Amp Op Amp Giving Voltage Difference Output Frequency Response of the Op Amp Using a Subcricuit for the Op Amp Op Amp differentiator Circuit Op Amp Integrator Circuit Response to Unit Step Function Double Op Amp Circuit
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The Ideal Op Amp High input resistance, zero output
resistance, and high voltage gain
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The Ideal Inverting Op Amp
Negative feedback connection
PSpice version of the circuit
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Input FileIdeal Operational AmplifierVS 1 0 1VE 3 0 0 2 200E3RI 2 0 1GR1 1 2 1KR2 3 2 10K.OP.OPT nopage.TF V(3) VS.END
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Run the Analysis and Verify Run V(3)/VS=-9.999 Verify Vo/Vs=-R2/R1=-10K/1K=-10
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Noninverting Ideal Op Amp
Noninverting ideal op amp
Noninverting ideal op amp model
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Input FileIdeal Operational Amplifier, NoninvertingVS 1 0 1VE 3 0 1 2 200E3RI 1 2 1GR1 2 0 1kR2 3 2 9k.op.opt nopage.TF V(3) VS.END
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Run and Verify V(3)/VS=10, Vo/Vs=1+R2/R1=1+9K/1K=10
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Op Amp Giving Voltage Difference Output
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Input FileOp Amp Giving Voltage Difference OutputVA 1 0 3VVB 4 0 10VE 5 0 3 2 200E3RI 2 3 1GR1 1 2 5kR2 5 2 10kR3 4 3 5kR4 3 0 10k.OP.OPT nopage .TF V(5) VB.END
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Run and Verify Verify that Vo=R2(Vb-Va)/R1=10k(10v-3v)/5k=14v V(5)=14V
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Frequency Response of the Op Amp
Model for the frequency response of an op amp
fc=10Hz
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Input FileOp Amp Model with 3-dB frequency at 10 Hz for Open-Loop
GainVS 2 0 AC 1mVEG 3 0 2 1 1E5E 6 0 4 0 1RI1 3 4 1kRO 6 5 50 R1 0 1 10kRL 5 0 22kRIN 1 2 1MEGC 4 0 15.92uF.AC DEC 40 1 1MEG.PROBE.END
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Run and View Output
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Modify Input FileOp Amp Model with 3-dB frequency at 10 Hz for Open-Loop
GainVS 2 0 AC 1mVEG 3 0 2 1 1E5E 6 0 4 0 1RI1 3 4 1kRO 6 5 50 R1 0 1 10kR2 5 1 240k RL 5 0 22kRIN 1 2 1MEGC 4 0 15.92uF.AC DEC 40 1 1MEG.PROBE.END
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Parameter Setting
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Run and View Output
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Using a Subcircuit for the Op Amp.subckt opamp m p voeg a 0 p m 1e5e c 0 b 0 1rin m p 1megril a b 1kc b 0 15.92uFrol c vo 50.ends
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Op Amp Analysis Using SubcircuitOp Amp Analysis Using SubcircuitVS 2 0 AC 1mVR1 1 0 10kR2 3 1 240kX 1 2 3 opamp.AC DEC 40 100 1MEG.PROBE.subckt opamp m p voeg a 0 p m 1e5e c 0 b 0 1rin m p 1megril a b 1kc b 0 15.92uFrol c vo 50.ends.END
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Op Amp Differentiator Circuit Vo=-dv/dt
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Input FileDifferentiator CircuitV 1 0 PWL (0, 0 1s, 1V 2s, 0)C 1 2 2FR 2 3 0.5X 2 0 3 iop.subckt iop m p vori m p 1mege vo 0 p m 2e5.ends.TRAN 0.05s 2s.PROBE.END
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Run and View OutputsV(1
)
Vo
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Op Amp Integrator Circuit
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Input FileIntegrator CircuitV 1 0 PWL (0 0 0.01ms, -1V 1s, -1V 1000.01ms, 0V 2s, 0V 2000.01ms, 1V 3s, 1V)R 1 2 0.5C 2 3 2 X 2 0 3 iop.subckt iop m p vori m p 1mege vo 0 p m 2e5.ends.TRAN 0.05s 3s.PROBE.END
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Run and View Output
Vo
V(1)
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Response to Unit Step Function
By definition, it remains at zero volts until t=0, and from that time forward it is 1V.
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Response of first-order circuit to unit step function
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Input FileResponse to Unit Step Functi
on Vs 1 0 PWL (0, 0 1us, 1v 5s, 1v)C 2 3 0.125R 2 3 2 R1 2 0 1 X 2 1 3 iop.subckt iop m p vori m p 1mege vo 0 p m 2e5.ends.TRAN 0.05s 3s.PROBE.END
Vo(t)=(3-2e-4t)u(t)
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Run and View Outputs
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Double Op Amp Circuit
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Input FileDouble Op Amp Circuit for Gain-Bandwidth Analysi
sVS1 2 0 AC 1mVR1 1 0 10kR2 3 1 240kX1 1 2 3 opampVS2 5 0 AC 1mVR3 4 0 10kR4 6 4 15kX2 4 5 6 OPAMP.AC DEC 40 100 10MEG.PROBE.subckt opamp m p voeg a 0 p m 1e5e c 0 b 0 1rin m p 1megril a b 1kc b 0 15.92uFrol c vo 50.ends.END
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Run and View Outputs
OP Amp 1
OP Amp 2
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Chapter 8 The Operational Amplifier (Part II) ~ Using Capture
Noninverting Ideal Op Amp Op Amp for Voltage-Difference Output Frequency Response of the Op Amp Frequency Response of the uA741 The uA741 as a Level Detector
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Noninverting Ideal Op Amp
3
0
1mA
-+
+-
E1
E R2
9k2
R1
1k
1mA
Gain = 200,000
Ri
1G
0
Vs1V
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Ideal op amp in Capture
Ideal op amp
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Run and View Output
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Op Amp for Voltage-Difference Output
2R1
5k Ri1G5
R4
10k
0
Vb10V
R2
10k1
Gain = 200,000
Va3V 4
R3
5k 3
-+
+-
E2
E
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Run and View Output
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Frequency Response of the Op Amp
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Op amp model for fc=10Hz
R1
10k
5R2
240k
0
Vs1mV0Vdc
2
4Gain = 100,000
Gain = 1
Ro
50
-+
+-
EG
E
3 6
Rin
1Meg
C15.92uF
-+
+-
E
E
Ri1
1k
1
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Simulation Setting
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Run and View Output
20*log10(V(5)/V(2))
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DB(V(5)/V(2))
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Frequency Response of the uA741
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V+
15V
V-
15V
R1
10k
R2
240k
2
5
1
0
3
U1
uA741
3
2
74
6
1
5+
-
V+
V-
OUT
OS1
OS2
Vs1mV0Vdc
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Run and View OutputFrequency response of the uA741
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The uA741 as a Level Detector
R1
1k
V-9V
5
U1
uA741
3
2
74
6
1
5+
-
V+V-
OUT
OS1
OS2
4
V1
1
V+9V
Vref
3V
3
2
0
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V1 (VPWL) Settings
(0v, 0s), (3v, 0.2s), (5v, 0.4s), (-5v, 0.6s), (-3v, 0.8v), (0v, 1s)
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Simulation Settings
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Run and View Output
V(5) Output
V(1) input
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Question & Answer