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Chapter Seven

CACHE MEMORY

AND VIRTUAL MEMORY

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• SRAM:

– value is stored on a pair of inverting gates

– very fast but takes up more space than DRAM (4 to 6 transistors)

• DRAM:

– value is stored as a charge on capacitor (must be refreshed)

– very small but slower than SRAM (factor of 5 to 10)

Memories: Review

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Users want large and fast memories! 1997

SRAM access times are 2 - 25ns at cost of $100 to $250 per Mbyte.DRAM access times are 60-120 ns at cost of $5 to $10 per Mbyte.Disk access times are 10 to 20 million ns at cost of $.10 to $.20 per Mbyte.

2005

SRAM access times are 1.25 ns at cost of $1000 per Gbyte.DRAM access times are 2.5 ns at cost of $100 per Gbyte.Disk access times are 200,000 ns at cost of $1 per Gbyte.

Try and give it to them anyway- build a memory hierarchy

Exploiting Memory Hierarchy

Levels inmemoryhierarchy

Increasingdistance fromCPU in accesstime.

Size of memory

CPU

CPU Cache (1M)

RAM (1G)

Disk Cache (.5G)

Disk (100 GB)

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Locality

• A principle that makes having a memory hierarchy a good idea

• If an item is referenced,

temporal locality: it will tend to be referenced again soonspatial locality: nearby items will tend to be referenced soon.

Why does code have locality?

• Our initial focus: two level model (upper, lower)– block: minimum unit of data – hit: data requested is in the upper level– miss: data requested is not in the upper level

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• Two issues:

– How do we know if a data item is in the cache?

– If it is, how do we find it?

• Our first example:

– block size is one word of data

– "direct mapped"

For each item of data at the lower level, there is exactly one location in the cache where it might be.

e.g., lots of items at the lower level share locations in the upper level

Cache

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• Mapping: address is modulo the number of blocks in the cache

Direct Mapped Cache

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• For MIPS:

What kind of locality are we taking advantage of?

Direct Mapped Cache

Data

Address, showing bit positions

Hit Tag

Index Valid Tag Data

Index = Addr & 0…0111111111100Blocks = 0…010000000000, B-1 = 0…001111111111

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• Taking advantage of spatial locality:

Direct Mapped Cache

Block OffsetDataHit Tag

Address, showing bit positions

V (valid) Tag

Index = (Addr >> (2+W)) & 0000000000000000111111111111 Index Mask = (Blocks-1)Tag Mask = Address >> (2 + W + log2(Blocks) )

W=log2(Words per Block)

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Bits Sizes for Calculations

Cache Size (Words)

log2 Cache Size (bits)

Cache Width

(words)

log2 Cache Width (bits)

First Shift( >>N)

Index Size (bits)

Tag Size

S W W+2 S-W 30 - S

128 7 1 0 2 7 232 1 3 6 234 2 4 5 238 3 5 4 23

256 8 1 0 2 8 222 1 3 7 224 2 4 6 228 3 5 5 22

512 9 1 0 2 9 212 1 3 8 214 2 4 7 218 3 5 6 21

1,024 10 1 0 2 10 202 1 3 9 204 2 4 8 208 3 5 7 20

2,048 11 1 0 2 11 192 1 3 10 194 2 4 9 198 3 5 8 19

4,096 12 1 0 2 12 182 1 3 11 184 2 4 10 188 3 5 9 18

8,192 13 1 0 2 13 172 1 3 12 174 2 4 11 178 3 5 10 17

16,384 14 1 0 2 14 162 1 3 13 164 2 4 12 168 3 5 11 16

32,768 15 1 0 2 15 152 1 3 14 154 2 4 13 158 3 5 12 15

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• Read hits

– this is what we want!

• Read misses

– stall the CPU, fetch block from memory, deliver to cache, restart

• Write hits:

– can replace data in cache and memory (write-through)

– write the data only into the cache (write-back the cache later)

• Write misses:

– read the entire block into the cache, then write the word

Hits vs. Misses

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• Make reading multiple words easier by using banks of memory

• It can get a lot more complicated...

Hardware Issues

a. One-word-wide memory organization.

b. Wide memory organization.

c. Interleaved memory organization.

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Performance

ProgramBlock size in words

Instruction miss rate Data miss rate

Effective combined miss rate

gcc 1 6.1% 2.1% 5.4%4 2.0% 1.7% 1.9%

spice 1 1.2% 1.3% 1.2%4 0.3% 0.6% 0.4%

Mis

s R

ate

(%

)

Block Size (bytes)

4 16 64 256

Cache Size (kbyte) 1

8 16 64128

• Increasing the block size tends to decrease miss rate:

• Use split caches because there is more spatial locality in code:

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Performance

• Simplified model:

execution time = (execution cycles + stall cycles) cycle time

stall cycles = # of instructions miss ratio miss penalty

• Two ways of improving performance:

– decreasing the miss ratio

– decreasing the miss penalty

What happens if we increase block size?

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Compared to direct mapped, give a series of references that:– results in a lower miss ratio– assuming we use the “least recently used” replacement strategy

Decreasing miss ratio with associativity

1-way Set Associative (direct mapping)

2-way Set Associative)

4-way Set Associative

8-way Set Associative (fully associative)

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An implementation

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Performance

Mis

s R

ate

(%

)

Associativity

1-way 2-way 4-way 8-way

Cache Size (kbyte) 1

2 4 8 16 32 64128

15%

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Decreasing miss penalty with multilevel caches

• Add a second level cache:

– often primary cache is on the same chip as the processor

– use SRAMs to add another cache above primary memory (DRAM)

– miss penalty goes down if data is in 2nd level cache

• Example:– CPI of 1.0 on a 500Mhz machine with a 5% miss rate, 200ns DRAM access– Adding 2nd level cache with 20ns access time decreases miss rate to 2%

• Using multilevel caches:

– try and optimize the hit time on the 1st level cache

– try and optimize the miss rate on the 2nd level cache

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Virtual Memory

• Main memory can act as a cache for the secondary storage (disk)

• Advantages:– illusion of having more physical memory– program relocation – protection

Memory Address

Physical Addresses

Disk Addresses

Address Translation

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Pages: virtual memory blocks

• Page faults: the data is not in memory, retrieve it from disk

– huge miss penalty, thus pages should be fairly large (e.g., 4KB)

– reducing page faults is important (LRU is worth the price)

– can handle the faults in software instead of hardware

– using write-through is too expensive so we use writeback

Memory Address

Virtual Page Number

Page Offset

Page Offset

Physical Page Number

Physical Address

32

28

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Page Tables

Virtual Page No.

Page Table

Physical Page (ram) or disk

address

Physical (ram & cache) Memory

Disk Storage

V

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Page Tables

Virtual Page No.

Page Table Register

Page Offset

Memory Address

Virtual Page Number

Page Offset

Page Offset

Physical Page Number

Physical Address

31

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Physical Page Number

Physical Page Number

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Making Address Translation Fast

• A cache for address translations: translation lookaside buffer

Fig. 7.23

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TLBs (Translation Lookaside Buffers) and caches

Fig. 7.25

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Modern Systems

• Very complicated memory systems:Characteristic Intel Pentium Pro PowerPC 604Virtual address 32 bits 52 bitsPhysical address32 bits 32 bitsPage size 4 KB, 4 MB 4 KB, selectable, and 256 MBTLB organizationA TLB for instructions and a TLB for data A TLB for instructions and a TLB for data

Both four-way set associative Both two-way set associativePseudo-LRU replacement LRU replacementInstruction TLB: 32 entries Instruction TLB: 128 entriesData TLB: 64 entries Data TLB: 128 entriesTLB misses handled in hardware TLB misses handled in hardware

Characteristic Intel Pentium Pro PowerPC 604Cache organization Split instruction and data caches Split intruction and data cachesCache size 8 KB each for instructions/data 16 KB each for instructions/dataCache associativity Four-way set associative Four-way set associativeReplacement Approximated LRU replacement LRU replacementBlock size 32 bytes 32 bytesWrite policy Write-back Write-back or write-through

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• Processor speeds continue to increase very fast— much faster than either DRAM or disk access times

• Design challenge: dealing with this growing disparity

• Trends:

– synchronous SRAMs (provide a burst of data)

– redesign DRAM chips to provide higher bandwidth or processing

– restructure code to increase locality

– use prefetching (make cache visible to ISA)

Some Issues