1 cis 665: gpu programming lecture 2: the cuda programming model
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CIS 665: GPU Programming
Lecture 2: The CUDA Programming Model
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Slides References
• Nvidia (Kitchen)• David Kirk + Wen-Mei Hwu (UIUC)• Gary Katz and Joe Kider
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VertexIndex
Stream
3D APICommands
AssembledPrimitives
PixelUpdates
PixelLocationStream
ProgrammableFragmentProcessor
ProgrammableFragmentProcessor
Tra
nsf
orm
ed
Vert
ices
ProgrammableVertex
Processor
ProgrammableVertex
Processor
GPUFront End
GPUFront End
PrimitiveAssembly
PrimitiveAssembly
Frame Buffer
Frame Buffer
RasterOperations
Rasterizationand
Interpolation
3D API:OpenGL orDirect3D
3D API:OpenGL orDirect3D
3DApplication
Or Game
3DApplication
Or Game
Pre
-transfo
rmed
Vertice
s
Pre
-transfo
rmed
Fragm
en
ts
Tra
nsf
orm
ed
Fragm
en
ts
GPU
Com
mand &
Data
Stre
am
CPU-GPU Boundary (AGP/PCIe)
Fixed-function pipeline
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• The GPU has evolved into a very flexible and powerful processor:– It’s programmable using high-level languages– It supports 32-bit floating point precision– It offers lots of GFLOPS:
• GPU in every PC and workstation
GF
LOP
S
G80 = GeForce 8800 GTX
G71 = GeForce 7900 GTX
G70 = GeForce 7800 GTX
NV40 = GeForce 6800 Ultra
NV35 = GeForce FX 5950 Ultra
NV30 = GeForce FX 5800
Why Use the GPU for Computing ?
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What is Behind such an Evolution?• The GPU is specialized for compute-intensive, highly data
parallel computation (exactly what graphics rendering is about)– So, more transistors can be devoted to data processing rather than
data caching and flow control
• The fast-growing video game industry exerts strong economic pressure that forces constant innovation
DRAM
Cache
ALUControl
ALU
ALU
ALU
DRAM
CPU GPU
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What is (Historical) GPGPU ?
• General Purpose computation using GPU and graphics API in applications other than 3D graphics– GPU accelerates critical path of application
• Data parallel algorithms leverage GPU attributes– Large data arrays, streaming throughput
– Fine-grain SIMD parallelism
– Low-latency floating point (FP) computation
• Applications – see //GPGPU.org– Game effects (FX) physics, image processing
– Physical modeling, computational engineering, matrix algebra, convolution, correlation, sorting
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Previous GPGPU Constraints• Dealing with graphics API
– Working with the corner cases of the graphics API
• Addressing modes– Limited texture size/dimension
• Shader capabilities– Limited outputs
• Instruction sets– Lack of Integer & bit ops
• Communication limited– Between pixels
– Scatter a[i] = p
Input Registers
Fragment Program
Output Registers
Constants
Texture
Temp Registers
per threadper Shaderper Context
FB Memory
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CUDA
• “Compute Unified Device Architecture”
• General purpose programming model– User kicks off batches of threads on the GPU
– GPU = dedicated super-threaded, massively data parallel co-processor
• Targeted software stack– Compute oriented drivers, language, and tools
• Driver for loading computation programs into GPU– Standalone Driver - Optimized for computation
– Interface designed for compute – graphics-free API
– Data sharing with OpenGL buffer objects
– Guaranteed maximum download & readback speeds
– Explicit GPU memory management
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An Example of Physical Reality Behind CUDA
CPU(host)
GPU w/ local DRAM
(device)
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Parallel Computing on a GPU
• 8-series GPUs deliver 25 to 200+ GFLOPSon compiled parallel C applications– Available in laptops, desktops, and clusters
• GPU parallelism is doubling every year• Programming model scales transparently
• Programmable in C with CUDA tools• Multithreaded SPMD model uses application
data parallelism and thread parallelism
GeForce 8800
Tesla S870
Tesla D870
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Overview
• CUDA programming model – basic concepts and data types
• CUDA application programming interface - basic
• Simple examples to illustrate basic concepts and functionalities
• Performance features will be covered later
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CUDA – C with no shader limitations!• Integrated host+device app C program
– Serial or modestly parallel parts in host C code
– Highly parallel parts in device SPMD kernel C code
Serial Code (host)
. . .
. . .
Parallel Kernel (device)
KernelA<<< nBlk, nTid >>>(args);
Serial Code (host)
Parallel Kernel (device)
KernelB<<< nBlk, nTid >>>(args);
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CUDA Devices and Threads
• A compute device– Is a coprocessor to the CPU or host
– Has its own DRAM (device memory)
– Runs many threads in parallel
– Is typically a GPU but can also be another type of parallel processing device
• Data-parallel portions of an application are expressed as device kernels which run on many threads
• Differences between GPU and CPU threads – GPU threads are extremely lightweight
• Very little creation overhead
– GPU needs 1000s of threads for full efficiency• Multi-core CPU needs only a few
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L2
FB
SP SP
L1
TF
Th
rea
d P
roc
es
so
r
Vtx Thread Issue
Setup / Rstr / ZCull
Geom Thread Issue Pixel Thread Issue
Input Assembler
Host
SP SP
L1
TF
SP SP
L1
TF
SP SP
L1
TF
SP SP
L1
TF
SP SP
L1
TF
SP SP
L1
TF
SP SP
L1
TF
L2
FB
L2
FB
L2
FB
L2
FB
L2
FB
• The future of GPUs is programmable processing• So – build the architecture around the processor
G80 – Graphics Mode
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G80 CUDA mode – A Device Example• Processors execute computing threads• New operating mode/HW interface for computing
Load/store
Global Memory
Thread Execution Manager
Input Assembler
Host
Texture Texture Texture Texture Texture Texture Texture TextureTexture
Parallel DataCache
Parallel DataCache
Parallel DataCache
Parallel DataCache
Parallel DataCache
Parallel DataCache
Parallel DataCache
Parallel DataCache
Load/store Load/store Load/store Load/store Load/store
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Extended C• Declspecs
– global, device, shared, local, constant
• Keywords– threadIdx, blockIdx
• Intrinsics– __syncthreads
• Runtime API– Memory, symbol,
execution management
• Function launch
__device__ float filter[N];
__global__ void convolve (float *image) {
__shared__ float region[M]; ...
region[threadIdx] = image[i];
__syncthreads() ...
image[j] = result;}
// Allocate GPU memoryvoid *myimage = cudaMalloc(bytes)
// 100 blocks, 10 threads per blockconvolve<<<100, 10>>> (myimage);
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gcc / cl
G80 SASSfoo.sass
OCG
Extended C
cudaccEDG C/C++ frontend
Open64 Global Optimizer
GPU Assemblyfoo.s
CPU Host Code foo.cpp
Integrated source(foo.cu)
Mark Murphy, “NVIDIA’s Experience with Open64,”www.capsl.udel.edu/conferences/open64/2008/Papers/101.doc
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Arrays of Parallel Threads
• A CUDA kernel is executed by an array of threads– All threads run the same code (SPMD)– Each thread has an ID that it uses to compute
memory addresses and make control decisions
76543210
…float x = input[threadID];float y = func(x);output[threadID] = y;…
threadID
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…float x = input[threadID];float y = func(x);output[threadID] = y;…
threadID
Thread Block 0
……float x = input[threadID];float y = func(x);output[threadID] = y;…
Thread Block 0
…float x = input[threadID];float y = func(x);output[threadID] = y;…
Thread Block N - 1
Thread Blocks: Scalable Cooperation
• Divide monolithic thread array into multiple blocks– Threads within a block cooperate via shared memory,
atomic operations and barrier synchronization
– Threads in different blocks cannot cooperate
76543210 76543210 76543210
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Thread Batching: Grids and Blocks• A kernel is executed as a grid of
thread blocks– All threads share data memory
space
• A thread block is a batch of threads that can cooperate with each other by:
– Synchronizing their execution• For hazard-free shared memory
accesses
– Efficiently sharing data through a low latency shared memory
• Two threads from two different blocks cannot cooperate
Host
Kernel 1
Kernel 2
Device
Grid 1
Block(0, 0)
Block(1, 0)
Block(2, 0)
Block(0, 1)
Block(1, 1)
Block(2, 1)
Grid 2
Block (1, 1)
Thread(0, 1)
Thread(1, 1)
Thread(2, 1)
Thread(3, 1)
Thread(4, 1)
Thread(0, 2)
Thread(1, 2)
Thread(2, 2)
Thread(3, 2)
Thread(4, 2)
Thread(0, 0)
Thread(1, 0)
Thread(2, 0)
Thread(3, 0)
Thread(4, 0)
Courtesy: NDVIA
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Block and Thread IDs
• Threads and blocks have IDs– So each thread can decide what data
to work on– Block ID: 1D or 2D– Thread ID: 1D, 2D, or 3D
• Simplifies memoryaddressing when processingmultidimensional data
– Image processing– Solving PDEs on volumes– …
Device
Grid 1
Block(0, 0)
Block(1, 0)
Block(2, 0)
Block(0, 1)
Block(1, 1)
Block(2, 1)
Block (1, 1)
Thread(0, 1)
Thread(1, 1)
Thread(2, 1)
Thread(3, 1)
Thread(4, 1)
Thread(0, 2)
Thread(1, 2)
Thread(2, 2)
Thread(3, 2)
Thread(4, 2)
Thread(0, 0)
Thread(1, 0)
Thread(2, 0)
Thread(3, 0)
Thread(4, 0)
Courtesy: NDVIA
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CUDA Device Memory Space Overview
• Each thread can:– R/W per-thread registers– R/W per-thread local memory– R/W per-block shared memory– R/W per-grid global memory– Read only per-grid constant memory– Read only per-grid texture memory
(Device) Grid
ConstantMemory
TextureMemory
GlobalMemory
Block (0, 0)
Shared Memory
LocalMemory
Thread (0, 0)
Registers
LocalMemory
Thread (1, 0)
Registers
Block (1, 0)
Shared Memory
LocalMemory
Thread (0, 0)
Registers
LocalMemory
Thread (1, 0)
Registers
Host• The host can R/W global,
constant, and texture memories
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Global, Constant, and Texture Memories(Long Latency Accesses)
• Global memory– Main means of communicating
R/W Data between host and device
– Contents visible to all threads
• Texture and Constant Memories– Constants initialized by host – Contents visible to all threads
(Device) Grid
ConstantMemory
TextureMemory
GlobalMemory
Block (0, 0)
Shared Memory
LocalMemory
Thread (0, 0)
Registers
LocalMemory
Thread (1, 0)
Registers
Block (1, 0)
Shared Memory
LocalMemory
Thread (0, 0)
Registers
LocalMemory
Thread (1, 0)
Registers
Host
Courtesy: NDVIA
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Host
Kernel 1
Kernel 2
Device
Grid 1
Block(0, 0)
Block(1, 0)
Block(0, 1)
Block(1, 1)
Grid 2
Courtesy: NDVIA
Figure 3.2. An Example of CUDA Thread Organization.
Block (1, 1)
Thread(0,1,0)
Thread(1,1,0)
Thread(2,1,0)
Thread(3,1,0)
Thread(0,0,0)
Thread(1,0,0)
Thread(2,0,0)
Thread(3,0,0)
(0,0,1) (1,0,1) (2,0,1) (3,0,1)
Block IDs and Thread IDs
• Each thread uses IDs to decide what data to work on– Block ID: 1D or 2D– Thread ID: 1D, 2D, or 3D
• Simplifies memoryaddressing when processingmultidimensional data– Image processing– Solving PDEs on volumes– …
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CUDA Memory Model Overview
• Global memory– Main means of
communicating R/W Data between host and device
– Contents visible to all threads
– Long latency access
• We will focus on global memory for now– Constant and texture
memory will come later
Grid
Global Memory
Block (0, 0)
Shared Memory
Thread (0, 0)
Registers
Thread (1, 0)
Registers
Block (1, 0)
Shared Memory
Thread (0, 0)
Registers
Thread (1, 0)
Registers
Host
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CUDA API Highlights:Easy and Lightweight
• The API is an extension to the ANSI C programming language
Low learning curve
• The hardware is designed to enable lightweight runtime and driver
High performance
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CUDA Device Memory Allocation
• cudaMalloc()– Allocates object in the
device Global MemoryGlobal Memory– Requires two parameters
• Address of a pointer to the allocated object
• Size of of allocated object
• cudaFree()– Frees object from device
Global Memory• Pointer to freed object
Grid
GlobalMemory
Block (0, 0)
Shared Memory
Thread (0, 0)
Registers
Thread (1, 0)
Registers
Block (1, 0)
Shared Memory
Thread (0, 0)
Registers
Thread (1, 0)
Registers
Host
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CUDA Device Memory Allocation (cont.)
• Code example: – Allocate a 64 * 64 single precision float array– Attach the allocated storage to Md– “d” is often used to indicate a device data structure
TILE_WIDTH = 64;Float* Mdint size = TILE_WIDTH * TILE_WIDTH * sizeof(float);
cudaMalloc((void**)&Md, size);cudaFree(Md);
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CUDA Host-Device Data Transfer
• cudaMemcpy()– memory data transfer
– Requires four parameters• Pointer to destination
• Pointer to source
• Number of bytes copied
• Type of transfer
– Host to Host
– Host to Device
– Device to Host
– Device to Device
• Asynchronous transfer
Grid
GlobalMemory
Block (0, 0)
Shared Memory
Thread (0, 0)
Registers
Thread (1, 0)
Registers
Block (1, 0)
Shared Memory
Thread (0, 0)
Registers
Thread (1, 0)
Registers
Host
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CUDA Host-Device Data Transfer(cont.)
• Code example: – Transfer a 64 * 64 single precision float array
– M is in host memory and Md is in device memory
– cudaMemcpyHostToDevice and cudaMemcpyDeviceToHost are symbolic constants
cudaMemcpy(Md, M, size, cudaMemcpyHostToDevice);
cudaMemcpy(M, Md, size, cudaMemcpyDeviceToHost);
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GeForce 8800 Series Technical Specs
• Maximum number of threads per block: 512• Maximum size of each dimension of a grid: 65,535• Number of streaming multiprocessors (SM):
– GeForce 8800 GTX: 16 @ 675 MHz– GeForce 8800 GTS: 12 @ 600 MHz
• Device memory:– GeForce 8800 GTX: 768 MB– GeForce 8800 GTS: 640 MB
• Shared memory per multiprocessor: 16KB divided in 16 banks• Constant memory: 64 KB• Warp size: 32 threads (16 Warps/Block)
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CUDA Keywords
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CUDA Function Declarations
hosthost__host__ float HostFunc()
hostdevice__global__ void KernelFunc()
devicedevice__device__ float DeviceFunc()
Only callable from the:
Executed on the:
• __global__ defines a kernel function– Must return void
• __device__ and __host__ can be used together
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CUDA Function Declarations (cont.)
• __device__ functions cannot have their address taken
• For functions executed on the device:– No recursion– No static variable declarations inside the function– No variable number of arguments
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Calling a Kernel Function – Thread Creation
• A kernel function must be called with an execution configuration:
__global__ void KernelFunc(...);
dim3 DimGrid(100, 50); // 5000 thread blocks
dim3 DimBlock(4, 8, 8); // 256 threads per block
size_t SharedMemBytes = 64; // 64 bytes of shared memory
KernelFunc<<< DimGrid, DimBlock, SharedMemBytes >>>(...);
• Any call to a kernel function is asynchronous from CUDA 1.0 on, explicit synch needed for blocking
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Technical details
• NVIDIA’s CUDA development tools provide three key components to help you get started: the latest CUDA driver, a complete CUDA Toolkit, and CUDA SDK code samples.
• 1. CUDA Driver • 2. CUDA Toolkit • 3. CUDA SDK code samples
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A Simple Running ExampleMatrix Multiplication
• A simple matrix multiplication example that illustrates the basic features of memory and thread management in CUDA programs– Leave shared memory usage until later
– Local, register usage
– Thread ID usage
– Memory data transfer API between host and device
– Assume square matrix for simplicity
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Programming Model:Square Matrix Multiplication Example
• P = M * N of size WIDTH x WIDTH
• Without tiling:– One thread calculates one element of P
– M and N are loaded WIDTH times from global memory
M
N
P
WID
TH
WID
TH
WIDTH WIDTH
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M2,0
M1,1
M1,0M0,0
M0,1
M3,0
M2,1 M3,1
Memory Layout of a Matrix in C
M2,0M1,0M0,0 M3,0 M1,1M0,1 M2,1 M3,1 M1,2M0,2 M2,2 M3,2
M1,2M0,2 M2,2 M3,2
M1,3M0,3 M2,3 M3,3
M1,3M0,3 M2,3 M3,3
M
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Step 1: Matrix MultiplicationA Simple Host Version in C
M
N
P
WID
TH
WID
TH
WIDTH WIDTH
// Matrix multiplication on the (CPU) host in double precisionvoid MatrixMulOnHost(float* M, float* N, float* P, int Width){ for (int i = 0; i < Width; ++i) for (int j = 0; j < Width; ++j) { double sum = 0; for (int k = 0; k < Width; ++k) { double a = M[i * width + k]; double b = N[k * width + j]; sum += a * b; } P[i * Width + j] = sum; }}
i
k
k
j
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void MatrixMulOnDevice(float* M, float* N, float* P, int Width)
{ int size = Width * Width * sizeof(float); float* Md, Nd, Pd; …
1. // Allocate and Load M, N to device memory cudaMalloc(&Md, size); cudaMemcpy(Md, M, size, cudaMemcpyHostToDevice);
cudaMalloc(&Nd, size); cudaMemcpy(Nd, N, size, cudaMemcpyHostToDevice);
// Allocate P on the device cudaMalloc(&Pd, size);
Step 2: Input Matrix Data Transfer(Host-side Code)
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Step 3: Output Matrix Data Transfer(Host-side Code)
2. // Kernel invocation code – to be shown later …
3. // Read P from the device cudaMemcpy(P, Pd, size, cudaMemcpyDeviceToHost);
// Free device matrices cudaFree(Md); cudaFree(Nd); cudaFree (Pd); }
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Step 4: Kernel Function
// Matrix multiplication kernel – per thread code
__global__ void MatrixMulKernel(float* Md, float* Nd, float* Pd, int Width)
{ // Pvalue is used to store the element of the matrix // that is computed by the thread float Pvalue = 0;
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Nd
Md Pd
WID
TH
WID
TH
WIDTH WIDTH
Step 4: Kernel Function (cont.)
for (int k = 0; k < Width; ++k) { float Melement = Md[threadIdx.y*Width+k]; float Nelement = Nd[k*Width+threadIdx.x]; Pvalue += Melement * Nelement; }
Pd[threadIdx.y*Width+threadIdx.x] = Pvalue;}
ty
tx
ty
tx
k
k
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// Setup the execution configuration
dim3 dimGrid(1, 1); dim3 dimBlock(Width, Width);
// Launch the device computation threads! MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
Step 5: Kernel Invocation(Host-side Code)
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Only One Thread Block Used
• One Block of threads compute matrix Pd
– Each thread computes one element of Pd
• Each thread– Loads a row of matrix Md– Loads a column of matrix Nd– Perform one multiply and
addition for each pair of Md and Nd elements
– Compute to off-chip memory access ratio close to 1:1 (not very high)
• Size of matrix limited by the number of threads allowed in a thread block
Grid 1
Block 1
3 2 5 4
2
4
2
6
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Thread(2, 2)
WIDTH
Md Pd
Nd
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Step 7: Handling Arbitrary Sized Square Matrices
• Have each 2D thread block to compute a (TILE_WIDTH)2 sub-matrix (tile) of the result matrix– Each has (TILE_WIDTH)2 threads
• Generate a 2D Grid of (WIDTH/TILE_WIDTH)2 blocks
Md
Nd
Pd
WID
TH
WID
TH
WIDTH WIDTH
ty
tx
by
bx
You still need to put a loop around the kernel call for cases where WIDTH/TILE_WIDTH is greater than max grid size (64K)!
TILE_WIDTH
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Some Useful Information on Tools
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Compiling a CUDA Program
NVCC
C/C++ CUDAApplication
PTX to TargetCompiler
G80 … GPU
Target code
PTX CodeVirtual
Physical
CPU Code
• Parallel Thread eXecution (PTX)– Virtual Machine
and ISA– Programming
model– Execution
resources and state
float4 me = gx[gtid];me.x += me.y * me.z;
ld.global.v4.f32 {$f1,$f3,$f5,$f7}, [$r9+0];mad.f32 $f1, $f5, $f3, $f1;
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Compilation
• Any source file containing CUDA language extensions must be compiled with NVCC
• NVCC is a compiler driver– Works by invoking all the necessary tools and
compilers like cudacc, g++, cl, ...
• NVCC outputs:– C code (host CPU Code)
• Must then be compiled with the rest of the application using another tool
– PTX• Object code directly• Or, PTX source, interpreted at runtime
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Linking
• Any executable with CUDA code requires two dynamic libraries:– The CUDA runtime library (cudart)
– The CUDA core library (cuda)
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Debugging Using theDevice Emulation Mode
• An executable compiled in device emulation mode (nvcc -deviceemu) runs completely on the host using the CUDA runtime– No need of any device and CUDA driver– Each device thread is emulated with a host thread
• Running in device emulation mode, one can:– Use host native debug support (breakpoints, inspection, etc.)– Access any device-specific data from host code and vice-versa– Call any host function from device code (e.g. printf) and vice-
versa– Detect deadlock situations caused by improper usage of
__syncthreads
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Device Emulation Mode Pitfalls• Emulated device threads execute sequentially, so
simultaneous accesses of the same memory location by multiple threads could produce different results.
• Dereferencing device pointers on the host or host pointers on the device can produce correct results in device emulation mode, but will generate an error in device execution mode
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Floating Point
• Results of floating-point computations will slightly differ because of:– Different compiler outputs, instruction sets
– Use of extended precision for intermediate results• There are various options to force strict single precision on the host