1 copyright © monash university atm switch design philip branch centre for telecommunications and...

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Copyright © Monash University

ATM Switch Design

Philip BranchCentre for Telecommunications and Information

Engineering (CTIE)

Monash Universityhttp://www.anspag.monash.edu.au/~pbranch/masters.ppt

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ATM Switching Outline

• Switching terms and requirements

• Switch Architectures– cross bar, multiple bus, multistage– routing in multistage switches

• Buffering schemes in switches

• Buffer management

• Performance Measures

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ATM Switching Terms

• Switching

• Switching Element

• Switching Fabric

• Switching System

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ATM Switch Requirements

• Flexible switching rates

• Broadcast and Multicast

• Low cell loss probability

• Cell Sequence integrity.

• High speed switching.

• Cell header processing.– VPI/VCI translation

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Switch types

• Workgroup switches

• Campus switches

• Core switches

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Types of Switching Backplane

• Blocking– Routing Conflicts– Cells are lost if no internal buffers.– Cells are stored in a queue if there are

internal buffers.

• Non-blocking– No internal blocking.– Buffers at the inputs and/or outputs.

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ATM Switch Architectures

• Crossbar– Most campus switches

• Multiple Bus– Most workgroup switches

• Multistage – Most core switches

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• Best performance

• Very expensive for large switches

• Cost increases as where NXN is the switch size.

Crossbar

O N( )2

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Multiple Bus

• Lowest cost

• Poor scalability

• Poor performance due to bus contentionInputs

Outputs

Busses

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Multistage Switches

• Interconnection of a number of crossbar switching elements.

• Single path or multiple path.

• Buffers required to store packets.

• Very cost effective.

• Highly scalable.

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Multistage Switching Fabric

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Routing in Multistage Switches

• Self routing using destination tags

• Internal routing conflicts may – reduce the throughput, – increase the delay and – increase the cell loss in a switch.

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Self-Routing Principle

• VPI/VCI translation only at the input of the switching network

• Cell extended by a switching network internal header

• Cell header extension requires increased internal speed.

• Suitable for large multistage networks

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Self-routing (contd.)

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Self Routing: Example

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Multicast with Self-Routing

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Tree Saturation• Hot spot traffic

– A lot of traffic may be directed to a particular output.

• Tree saturation reduces the performance of the switch

• Saturated tree blocks traffic to other (non hot) outputs as well.

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Contention in a Multi-stage Switch

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Batcher-Banyan Switch

• A Banyan network has no internal conflict if cells are arranged in ascending or descending order of output destination.

• A Batcher network is used to sort cells in ascending order.

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Batcher-Banyan (contd.)

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Table-controlled VPI/VCI translation

• VPI/VCI translation at each switching element.

• Cell length need not be altered.

• Table contents are updated during connection set-up.

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Table-controlled (contd.)

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Buffering in Switches

• Buffers store the cells that lose routing conflicts.

• Location of buffers:– Internally, Externally– Input, Output, Shared, Crosspoint

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Input Buffered Switch

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Input Buffers

• Head of line blocking reduces throughput

• Inefficient utilisation of buffer space

• Simple buffer management

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Head-of-Line Blocking

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Output Buffered Switch

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Output Buffers

• No head of line blocking


• Requires expensive high speed buffers

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Shared Buffer

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Shared Buffer

• High buffer utilisation.

• Needs least amount of buffer space.

• Buffer hogging with non uniform traffic.

• Complex buffer management strategy.

• Needs expensive high speed buffers.

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Crosspoint Buffer

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Crosspoint Buffer

• Combines the advantages of input and output buffers


• Simple buffer management

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Buffer Size Requirements

• Buffer sizes for average load of 85% at each input and a permissible cell loss probability of 10-9

SizeTYPE 16 x 16 32 x 32

Sha re d Me m o ry 113 199Inp u t Buffe r 320 640O utp u t Buffe r 896 1824

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Buffer Management

• Queuing– How to organise buffered cells

• Scheduling– When and in what order to service queues

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Buffer Management

• Which cell to transmit next?

• Arbitration strategies based on– Random– fairness– minimise cell loss– minimise cell delay variation

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Arbitration Strategies

• State dependent:– Longest queue served first– Lengths of buffers have to be compared

• Delay dependent:– Queue having the maximum delay served

first– Overhead in storing order of arrival

information

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Buffer Queuing Policies

• First in - First out (FIFO)

• Strict Priority

• Fair Queueing (Per VC queueing)

• Weighted Round Robin

• Weighted Fair Queuing

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Performance Measures• Throughput: Number of cells switched per

unit time.

• Cell loss probability: Loss from routing conflicts or insufficient capacity

• Cell delay: Delay inside switch.– Switching delay: fixed– Queueing delay: variable– jitter: Cell delay variation.

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Conclusion– Switching terms and requirements– Switch architectures– Multistage switches

• self routing

• Batcher-Banyan switch

– Buffering schemes• Input, output, shared, crosspoint

– Output buffer management– Performance measures

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Questions

• An ATM switch is functioning normally, until a video server and video client are connected to it. When the video is played back from the server through the switch, other (low bandwidth) applications using the switch fail. The video delivered is jerky. What are some possible explanations for this?

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