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Design of 4- BIT ALU

Swetha ChallawarAnupama BhatLeena KulkarniSatya Kattamuri

Advisor: Dr.David Parent05/11/2005

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Agenda

• Abstract• Introduction

– Why– Simple Theory

• Objectives• Project (Experimental) Details• Results• Cost Analysis• Conclusions

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Abstract

• We designed a 4- bit ALU that operates with a power of 18.96mW/cm2 on an area of 534*459 μm2.

• It can drive a load up to 30Ff.

• ALU performs 16 arithmetic and logical functions .

• Operation frequency is 200Mhz

• Setup time is 0.63ns and hold time is 0.23ns.

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Introduction

• We all know that the ALU is an important component of the CPU. It is the ALU that performs all calculations and comparisons, on the basis of which the computer is able to take further actions.

• The 4 bit ALU is controlled by four function select inputs(S0 to S3) and the mode Control Input (M). It can perform all the 16 possible logical operations or 16 different arithmetic operations.

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Objectives

• To design 4-bit ALU using Cadence Tools

• To implement the concepts learned in EE166

• To learn accurate decision making during design

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Design Flow Process

• Implementation of gate level schematic in Cadence to verify the logic using NC Verilog.

• Finding the Longest Path.• Cell based designing followed by checking for

10% specification.• Implementation of transistor level schematic in

Cadence. • Spice Simulation for transistor level• Layout• DRC • Extraction• LVS• Post Extraction

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Project Summary

• Implemented the concepts learnt in EE166 class.

• Tried to make accurate decisions during the design process.

• Met all specifications.

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Gate Level Schematic

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Functional Table

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Longest Path CalculationsCELL WN Load WP Load Cint

Cg or Cin of load

Cg+Cint phl A WN WP

Unit (cm) (cm) F F s cm cmNOR2 2.00E-14 3.0000E-14 5.0000E-14 1.70E-10 4.46E-04 8.91E-04NAND2 4.46E-04 8.91E-04 2.00E-14 2.2442E-14 4.2442E-14 1.70E-10 9.93E-04 9.93E-04AOI21 9.93E-04 9.93E-04 2.00E-14 3.3331E-14 5.3331E-14 3.90E-10 4.76E-04 9.51E-04NOR2 4.76E-04 9.51E-04 2.00E-14 4.7883E-14 6.7883E-14 1.90E-10 4.74E-04 9.49E-04NOR2 4.74E-04 9.49E-04 2.00E-14 2.3886E-14 4.3886E-14 1.60E-10 4.50E-04 9.01E-04INV 4.50E-04 9.01E-04 2.00E-14 4.5357E-14 6.5357E-14 1.20E-10 5.42E-04 9.69E-04NOR2 5.42E-04 9.69E-04 2.00E-14 2.5358E-14 4.5358E-14 1.60E-10 4.64E-04 9.28E-04NOR2 4.64E-04 9.28E-04 2.00E-14 4.6702E-14 6.6702E-14 1.90E-10 4.67E-04 9.34E-04NAND2 4.67E-04 9.34E-04 2.00E-14 7.0500E-14 4.3000E-14 2.90E-10 3.41E-04 3.41E-04NOR2 3.41E-04 3.41E-04 2.00E-14 2.2899E-14 4.2899E-14 2.10E-10 2.62E-04 5.24E-04INV 2.62E-04 5.24E-04 2.00E-14 1.3179E-14 3.3179E-14 1.39E-10 2.33E-04 4.18E-04NAND2 2.33E-04 4.18E-04 2.00E-14 2.1864E-14 4.1864E-14 1.80E-10 8.50E-04 8.50E-04INV 8.50E-04 8.50E-04 2.00E-14 5.6000E-14 9.1000E-14 2.60E-10 2.76E-04 4.87E-04INV 2.76E-04 4.87E-04 2.00E-14 2.5610E-14 4.5610E-14 1.39E-10 3.15E-04 5.65E-04

No. of Logic Levels = 14 +4= 18Total Tphl = 5 ns /18= 2.7ns

Note: All capacitance values are in fF

Wn (H.C) Wp (H.C)

cm cm

3.66E-04 9.20E-04

6.87E-04 2.60E-04

2.49E-04 9.55E-04

3.71E-04 9.75E-04

3.88E-04 6.35E-04

3.89E-04 8.29E-04

3.40E-04 8.11E-04

2.75E-04 2.48E-04

2.20E-04 5.27E-04

2.70E-04 4.27E-04

5.57E-04 6.27E-04

2.89E-04 4.19E-04

3.42E-04 5.58E-04

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XOR

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Top level Schematic

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Transistor level Schematic

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Logic Verification for A+B

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Layout

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LVS Report

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Simulations

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Simulations

Power – 18.96mW

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Cost Analysis

– verifying logic: 2 weeks– verifying timing: 1 week– Layout: 2 weeks– post extracted timing: 2 days

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Conclusion• Challenges Encountered

– Debugging for LVS and DRC errors– Changed set of XORs to NAND and Inverter

• What we learnt from this project?– Basic CAD skills– Implementation of metal contacts: when, where and

how?– Design flow process– Enhanced decision making skills

• To select appropriate Wn and Wp Values• To define correct cell height in layout.

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Acknowledgements

• Thanks to Dr. David Parent for valuable guidance and constant encouragement

• Thanks to John and EE166 Classmates