1 digital logic circuits

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Ted Borys - CSI 404 2/3/2004 -1

© 2004 by Ted Borys. All rights reserved.

1

Digital Logic CircuitsDigital Logic Circuits

Section 1Section 1

2

Digital Computer Digital Computer

Binary

Two discrete values True 1 3.0 volts

False 0 0.5 volts

Very reliable

Hardware

Electronic components

Electromechanical devices

Software

Instructions and data manipulated by hardware

3

HardwareHardware

Central Processing Unit (CPU)

Arithmetic and logic unit (ALU)

Registers – holding data

Fetch and execute control circuits

Random Access Memory (RAM)

Input Output Processor (IOP)

Transfer data between computer and outside world

Input, output, and input/output (I/O) devices

4

DefinitionsDefinitions

Computer organization

How hardware components interoperate within thecomputer system

Computer design

Determine which hardware should be used and how parts are connected

Computer architecture

User perspective of computer structure and behavior

Design deals with component specs and combining

them to build a computer

5

Logic GateLogic Gate

Input

One or two signal lines

Naming convention: A and B Output

One signal line

Naming convention: x

Process

Binary logic function

6

Logic GatesLogic Gates

AND

OR

Exclusive-OR

Buffer

NAND

NOR

Exclusive-NOR

Inverter



Ted Borys - CSI 404 2/3/2004 Page 1-2


7

AND AND

algebraic function

x = AB 111

001

010

000

x B A

truth table

graphic symbol

A B

x

8

OROR

algebraic function

x = A + B 111

101

110

000

x B A

truth table

graphic symbol

A B

x

9

ExclusiveExclusive--OROR

algebraic function

x = A ⊕ B x = A′ B + AB′

011

101

110

000

x B A

truth table

graphic symbol

x A

B

10

Buffer Buffer

graphic symbol

algebraic function

x = A

11

00

x A

truth table

A x

11

NANDNAND

algebraic function

x = ( AB)′ 011

101

110

100

x B A

truth table

graphic symbol

A B

x

12

NORNOR

algebraic function

x = ( A + B)′ 011

001

010

100

x B A

truth table

graphic symbol

A B

x





13

ExclusiveExclusive--NORNOR

111

001

010

100

x B A

truth table

graphic symbol

A B

x

algebraic function

x = ( A ⊕ B)′ x = A′ B′ + AB

14

Inverter Inverter

graphic symbol

algebraic function

x = A′

01

10

x A

truth table

A x

15

Logic Gates > 2 InputsLogic Gates > 2 Inputs

AND

x = 1 if and only if all inputs = 1

OR

x = 1 if any input = 1

Exclusive-OR

x = 1 if an odd number of inputs = 1

16

Logic Gates > 2 InputsLogic Gates > 2 Inputs

NAND

Complement of AND

NOR

Complement of OR

Exclusive-NOR

Complement of exclusive-OR

17

Boolean AlgebraBoolean Algebra

Deals with binary variables and logic operations

Variable naming convention: A, B, x, y

Boolean function can yield either 0 or 1

Truth table for n variables has 2n rows

Algebraic expression can be expressed as a

combination of AND, OR, and Inverter gates

Goal is to simplify circuits by reducing gates

18

F = x +F = x + yzyz′ ′

0110

1001

1101

1011

1

0

0

0

x

111

101

010

000

F z y

x

y

z

F





19

Boolean Algebra IdentitiesBoolean Algebra Identities

Basic postulates

1 x = x identity element

0 + x = x identity element xx′ = 0 inverse element

x + x′ = 1 inverse element

xy = yx commutative law

x + y = y + x commutative law

x( y + z ) = xy + xz distributive law

x + yz = ( x + y)( x + z ) distributive law

20

Boolean Algebra IdentitiesBoolean Algebra Identities

Derivations

x0 = 0

x + 1 = 1 xx = x

x + x = x

x( yz ) = ( xy) z associative law

x + ( y + z ) = ( x + y) + z associative law

( xy)′ = x′ + y′ DeMorgan’s theorem

x + yz = ( x + y)( x + z ) DeMorgan’s theorem

( x′)′ = x

21

Reduction ExampleReduction Example

F = ABC + ABC ′ + A′C 6 gates

F = AB(C + C′) + A′C

F = AB + A′C 4 gates

22

Another Reduction Example Another Reduction Example

F = ABC + AB′C + AC ′ 6 gates

F = AC ( B + B′) + AC ′

F = AC + AC ′

F = A(C + C ′)

F = A no gates!

23

KarnoughKarnough MapMap

Helps reduce Boolean function complexity

Transforms a Boolean function truth table

into a picture Combination of input variable values for each

truth table row is called a minterm

It is a binary number that is converted to decimal

Truth table can be expressed at the sum of theminterms that generate a value of 1

24

MintermMinterm ExampleExample

0110

1001

1101

1011

1

0

0

0

x

111

101

010

000

F z y F = x + yz ′

F ( x, y, z ) = ∑ (2, 4, 5, 6, 7)





25

TwoTwo--Variable MapVariable Map

321

100

10 A

B

A

B

26

ThreeThree--Variable MapVariable Map

67541

23100

10110100 A

BC

A

C

B

27

Four Four --Variable MapVariable Map

10119810

1415131211

675401

231000

10110100 AB

CD

A

B

D

C

28

Simplification RulesSimplification Rules

Insert a “1” into each square that the functiongenerates a value of 1

Form one or more rectangles by groupingtogether adjacent squares containing a 1

Number of squares in each rectangle must be a power of 2

Top and bottom squares in a column are adjacent

Left- and right-most squares in a row are adjacent

All four corner squares are adjacent

Minimize number of rectangles

29

Redo Reduction ExampleRedo Reduction Example

F = ABC + ABC ′ + A′C

111

110

10110100 A BC

A

C

B

1110

0001

0101

1011

1

0

0

0

A

111

001

110

000

F C B

F = AB + A′C 30

Logically EquivalentLogically Equivalent

Sum of products

Function generates a 1

F = AB + A′C Two AND gates ORed together

Product of sums

Function complement generates a 0

F ′ = AB′ + A′C ′

F = ( A′ + B)( A + C )

Two OR gates ANDed together





31

Complement ExampleComplement Example

F = AB + A′C

111

110

10110100 A BC

A

C

B

F ′ = AB′ + A′C ′

F = ( A′ + B)( A + C ) 32

DonDon’’tt--Care ConditionsCare Conditions

Sometimes it doesn’t matter if the function

generates a 1 or a 0 for a given minterm

Mark those squares on the map with an X Can use the don’t care squares to further

simplify the algebraic expression

33

Combinational CircuitCombinational Circuit

Cluster of logic gates with some number of

inputs and outputs

Output values are determined by the binary

computations performed on the input values

Can be described by

A truth table

A Boolean function for each output

34

Half Half -- Adder Adder

Add 2 bits of input and generate 2 bits of output

Input bits are called augend and addend

Input symbols are x and y

Output bits are called sum and carry

Output symbols are S and C

35

Half Half -- Adder Adder

1

0

0

0

C

0

1

1

0

S

11

01

10

00

y x

truth table x

y

S

C

S = x′ y + xy′ = x ⊕ y

C = xy

•

•

36

FullFull-- Adder Adder

Add 3 bits of input and generate 2 bits of

output

Input bits are called augend, addend, and carry

Input symbols are x, y, and z

Output bits are called sum and carry

Output symbols are S and C





37

FullFull-- Adder Adder

01110

10001

01101

01011

1

1

0

0

y

1

0

0

0

C

1

1

1

0

S

11

00

10

00

z x

S = x ⊕ y ⊕ z

C = xy + ( x ⊕ y) z

x

y z

S

C FA

38

FlipFlip--FlopsFlops

Binary cell that can hold the value of one bit

Two outputs

Normal value

Complement

Maintains state until next clock pulse

39

FlipFlip--Flop TypesFlop Types

SR

Set Reset

D

Data

JK

Like Set Reset, except both on causes output bit flip

T

Toggle

40

SRSR FlipFlip--FlopFlop

Indeterminate?11

Set to 1101

Clear to 0010

No changeQ(t )00

Q(t +1) RS

41

DD FlipFlip--FlopFlop

Set to 111

Clear to 000

Q(t +1) D

42

JKJK FlipFlip--FlopFlop

ComplementQ′(t )11

Set to 1101

Clear to 0010

No changeQ(t )00

Q(t +1)K J





43

TT FlipFlip--FlopFlop

ComplementQ′(t )1

No changeQ(t )0

Q(t +1)T T

44

EdgeEdge--Triggered FlipTriggered Flip--FlopFlop

Synchronize state change during clock pulsetransition

Rising edge (positive)

Falling edge (negative)

can’t changecan change

45

FlipFlip--Flop Excitation TableFlop Excitation Table

What input values generate a given pair of

current and next values of Q?

46

SRSR FlipFlip--FlopFlop

Indeterminate?11

Set to 1101

Clear to 0010

No changeQ(t )00

Q(t +1) RS

X

0

1

0

S

011

101

010

X00

RQ(t +1)Q(t )

ExcitationCharacteristic

47

DD FlipFlip--FlopFlop

Set to 111

Clear to 000

Q(t +1) D

1

0

1

0

D

11

01

10

00

Q(t +1)Q(t )


48

JKJK FlipFlip--FlopFlop

ComplementQ′(t )11

Set to 1101

Clear to 0010

No changeQ(t )00

Q(t +1) K J

X

X1

0

J

011

101X10

X00

K Q(t +1)Q(t )






49

TT FlipFlip--FlopFlop

ComplementQ′(t )1

No changeQ(t )0

Q(t +1)T

0

11

0

T

11

0110

00

Q(t +1)Q(t )


50

Sequential CircuitSequential Circuit

Flip-flops and gates connected together

Combinational circuit block

Gates only Input from external sources and flip-flop output

Output goes to external destinations and flip-flops

Flip-flops

Input from clock and combinational circuit

Output to external destinations and combinationalcircuit

51

Sequential Circuit Block DiagramSequential Circuit Block Diagram

Combinational

circuit

Flip-flopsClock

InputsOutputs

Time sequence of external inputs, external outputs,

and internal flip-flop binary states

52

Sequential Circuit DiagramSequential Circuit Diagram

Q

QSET

CLR

D

Q

QSET

CLR

D

Clock

A

A′

B

B′

x

y

D A = Ax + Bx

D B = A′ x

y = Ax′ + Bx′

53

State Table for Sequential CircuitState Table for Sequential Circuit

001111

100011

001101

100001

011110

100010

010100

000000

y B A x B A

Out NextInPresent D A = Ax + Bx

D B = A′ x

y = Ax′ + Bx′

54

State DiagramState Diagram

Same information as state table

Different representation

Circle is state

Flip-flop values inside

Line connecting circles is transition

“input value / output value” for present state





55

State Diagram of Sequential CircuitState Diagram of Sequential Circuit

00 10

01 11

001111

100011

001101

100001

011110

100010

010100000000

y B A x B A

Out NextInPresent0/0 1/0

1/0

1/0

0/1

0/11/0

56

Design ProblemDesign Problem

Clocked sequential circuit that is a two bit binary counter

Increment when input x is 1 Remain unchanged when input x is 0

Construct

State diagram

Excitation table

Logic circuit diagram

57

Binary Counter State DiagramBinary Counter State Diagram

00

01

10

11

x = 0

x = 0

x = 0

x = 0

x = 1 x = 1

x = 1 x = 1

58

Binary Counter Excitation TableBinary Counter Excitation Table

1

0

0

0

X

X

X

X

K A

X

X

1

0

X

X

1

0

J B

X

X

X

X

1

0

0

0

J A

100111

011011

X11101

X01001

101110

010010

X10100

X00000

K B B A x B A

Flip-flop inputs NextInPresent

59

Map For Each FlipMap For Each Flip--Flop InputFlop Input

XXXX

1

A

x

B

J A = Bx

XX1

XX1

A

x

B

J B = x

1

XXXX

A

x

B

K A = Bx

1XX

1XX

A

x

B

K B = x60

Binary Counter Logic DiagramBinary Counter Logic Diagram

J A = Bx

K A = Bx

J B = x

K B = x

J

Q

Q

K

SET

CLR

J

Q

Q

K

SET

CLR

Clock

x A

B

1 digital logic circuits

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