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Fitting ATE Channels with Scan Fitting ATE Channels with Scan Chains: a Comparison between a Test Chains: a Comparison between a Test

Data Compression Technique and Data Compression Technique and Serial Loading of Scan ChainsSerial Loading of Scan Chains

LIRMM LIRMM CNRS / University of Montpellier IICNRS / University of Montpellier II

FRANCEFRANCE

J. DALMASSO, M.L. FLOTTES , B. ROUZEYRE

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Outline

• Introduction and motivation

• Serialization vs compression ?

• Compression technique

• Results

• Conclusion

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Needs for Test Data Compression

Integration density

• Number of transistors • Number of faults to test

• Test data volume • Test time => Multiple scan chains

ATE limits:• Memory depth• # ATE channels

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Issue

N scan chains,M ATE channels, N > M

How to fit M with N ?CUT

ATE

N

M

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1) Serialization of test data

1 Test slice

1 Pattern

Short test sequences (No X's)

1 test pattern = L test slices

1 test slice = divided into N/M slices of M bits in ATE

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2) Horizontal (de)compression

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Test pattern compression

Virtual scan chains (VTS'00)

Illinois scan architecture (DATE'02)

Ring generator+phase shifter (ITC'02)

Circular scan (DATE'04)

Test data mutation encoding (DATE'02)

Xor network (DAC'01)

Reconfigurable Switch (ITC'01)

Dictionnary based methods (TDAES'03 / & ITC'04)

Netlist dependent

Test data dependent

Specific tool dependent

Long test sequences (due to X's, low fill rate)

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Issues

Given: M ATE channels, N scan chains, N > M

Fitting M with N ?– Serialization : short test sequences (No X's)– Compression: long test sequences (X's)

What is the best solution ?

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Proposed horizontal compression method

FeaturesCircuit netlist independent (suitable for IPs)Test data independent (additional test patterns)Specific tools independentLow cost hardware decompressor

Input: test data sequence actually applied to CUTNo impact on fault coverage

Take advantage of X's in test sequence

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Decompressor architecture

N

0 0 0 0Add Cells

OutputShift Register

To scan chains

From ATEM

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aN-1…………………………………..…...…….a0

Decompression principle

Let Si = aN-1………………..…...…….a0

Let Si+1 = bN-1…………………..………b0

1/ it exists Sci = cM-1……c0 / Si+1 = Si + Sci

0 0 0 0c0c1

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c0c1

bN-1…………………………………………..…b0

Decompression principle

Let Si = aN-1………………..…...…….a0

Let Si+1 = bN-1…………………..………b0

1/ it exists Sci = cM-1……c0 / Si+1 = Si + Sci

1 slice on N bits (Si+1) => 1 slice of M bits (Sci) in ATE

0 0 0 0

Remark : P(cj: aibi) = 1/ 2dist => uniform distribution of inputs over adders

dist

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Decompression principle

Let Si = aN-1………………..…...…….a0 Let Si+1 = bN-1…………………..………b0

2/ it does not exist Sci = cM-1……c0 => serial loading of Si+1

b2M

bM

b0

b2M+1

bM+1

b1

A slice on N bits (Si+1) => N/M slices of M bits in ATE

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Compression

• Case 1 : it exists Sci on M bits => 1 slice of M bits

• Case 2 : it does not exist Sci => N/M slices of M bits

• Compression – Maximize case 1 occurrences– Presence of X's

• Columns ordering• X's assignment• Pattern ordering

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S1: 0 X 1 X

S2: 1 1 X X

S3: X 1 X 0

S4: 1 X X X

S1: 1 X X 0

S2: X 1 X 1

S3: X 1 0 X

S4: X X X 1

Scan Chains Scan Chains

ATE Channels ATE Channels

Compression algorithm: columns ordering

P(cj: aibi) = 1/ 2dist

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Compression algorithm: X's assignment

I = 1

If SCi

Initialization of Si

Si+1 = Si + SCi

i++

i++

NO

YES

SCi coded

on M bits

shift mode

add mode

Si coded

on N bits

SCi assignment

END

while i< #Slices

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Initialization and assignment

SC1: 0 1 0

SC2: 0 1 0

SC3 : 1 1 0

SC4 : - - -

S1: 1 X X 0 X 1 X X 0S2: X X 1 X X 0 X 0 X

S3: X 0 X X X 1 X X X

S4: X 1 X X 0 0 0 X X

S5: X X 0 1 X 0 1 X X

S1: 1 0 1 0 0 1 0 0 0

S2: 1 0 1 0 1 0 0 0 0

S3: 1 0 1 0 1 1 0 0 0

S4: 1 1 0 1 0 0 0 0 0

S5: X X 0 1 X 0 1 X X

Init =>

Init =>

ATE Channels

Scan chains

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Compression algorithm: X's assignment

I = 1

If SCi

Initialization of Si

Si+1 = Si + SCi

i++

i++

NO

YES

SCi coded

on M bits

shift mode

add mode

Si coded

on N bits

SCi assignment

END

while i< #Slices

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Compressed Slice assignment

000100101S1X0X0XX1XXS2XXX1XXX0XS3XX000XX1XS4XX10X10XXS5

?

a b c

S1

S2 S2

S4

S3 S3

S4

S5

0 1 1

0 1 1

1 1 1

0 0 1

0 1 0

0 1 0

1 1 0

a b c

S5

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Example

SC1 : 0 1 1

SC2 : 0 1 1

SC3 : 1 1 1

SC4 : 0 0 1

S1: 1 X X 0 X 1 X X 0S2: X X 1 X X 0 X 0 X

S3: X 0 X X X 1 X X X

S4: X 1 X X 0 0 0 X X

S5: X X 0 1 X 0 1 X X

S1: 1 0 1 0 0 1 0 0 0

S2: 1 0 1 0 1 0 0 0 1

S3: 1 0 1 0 1 1 0 1 0

S4: 1 1 0 1 0 0 0 1 1

S5: 1 1 0 1 0 0 1 0 0

Init =>

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Pattern ordering

V0

V1V1 V2V2 V3V3 V4V4

V1V1 V2V2 V4V4

V2V2 V4V4

V2V2

• Pattern order has an influence on the number of compressed slices Comparison of Pattern

Ordering Algorithm: Greedy algorithm Simulated Annealing

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Decompression synchronization

0 0

Scan enable Control

CLK

S1 1 0 0 0

S2 1 0 0 1

S3 1 1 1 0

S4 0 1 1 0

S1 -> S2 : 0 1

S2 -> S3 : 1 1

S3 -> S4 : - -

X X X X

XXXX

X X X X

1 0

X 1 X 0

1 1

X X X X

XXXX

X X X X

0 0

1 0 0 0

1 1

1 0 0 0

XXXX

X X X X

0 1

1 0 0 1

1 0

1 0 0 1

0001

X X X X

1 1

1 1 1 0

1 0

1 1 1 0

1001

1 0 0 0

0 1

1 0 0 1

1 1

1 1 1 0

1001

1 0 0 0

1 0

0 1 1 0

1 1

0 1 1 0

0111

1 0 0 1

0 1

0 1 1 1

1 0

Original test Sequence

Compressed test Sequence

FSM

Sc1 1 0Sc2 0 0Sc3 0 1Sc4 1 1Sc5 0 1Sc6 1 0

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Compression vs serialization

CC SS NT

1M

NNT

NCNC SS

2SS PL1M

NNNT

NCC

MNVCC SS M

M

NVV

NCNC SS

M

NNNMV

NCC SS

Test Time (loading) = Depth

Data Volume

With Compression Serialization

11 PL1M

NLPT

1PM

NLMV

1slice

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Experiments: Compression vs Serialization

• Test data sequences– Compression : X's needed

• type 1 : no compaction – long test sequences (very low fill rate)

• type 2 : compaction during ATPG – medium size test sequences

– Serialization : No X's, • type 3 : all ATPG optimizations enabled (fault

dropping, random filling, compaction …)– short test sequences (fully specified)

– ATPG

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Experimental results

S5378 circuit (214 flip-flops)

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Experimental results

s5378 214 7 217 83,19 1519 48608 21992 54.76 1109 3383 160 1120 35840 5767 38,64 41,34

s9234 247 8 215 77,3 1720 55040 30176 45.17 1036 4679 186 1488 47616 7634 36,63 38,71

s13207 699 22 272 93 5984 191488 65296 65.9 5258 9182 250 5500 176000 27772 62,9 66,94

s15850 611 20 142 84 2840 90880 42520 53.21 2015 6302 126 2520 80640 12746 47,27 50,56

s35932 1763 56 26 50 1456 46592 28256 39.35 764 4306 25 1400 44800 7081 36,93 39,19

s38417 1664 52 440 93,83 22880 732160 244192 66.65 20332 33564 145 7540 241280 37897 -1,2 11,43

s38580 1464 46 189 85,49 8694 278208 119448 57.07 6615 17245 142 6532 209024 32848 42,85 47,5

Gain

Volume %

Time %

#comp. Slices

Time (cycles)

serial loading

#Pat #SlicesVolume

(bits)Time

(cycles)% X #Slices

compression

Circuit FF L#Pat

original volume (bits)

comp. volume (bits)

comp ratio %

N= 32 scan chains , M = 8 ATE channels

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Comparison with Circular Scan [*]

[*] B. Arslan, A. Orailoglu, "CircularScan: a scan architecture for test cost reduction", DATE'04, pp: 1290-1295.

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Post process for regular circuits (not for IPs):Fault simulation => Pattern Dropping

Pattern rejection algorithm

Compression & X’s Assignment

Test Sequence with X’s

Fully specified Test Sequence : T

1 XX1 0 X0 1

XX1 XX1 0 X

P1:

P2:

f1, f2

f3

11 0 1 0 0 0 1

10 1 1 0 1 0 1

P1:

P2:

f1, f2

f3, f1, f2

T T*P Pattern

P* Pattern

With P* ≤ P

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Pattern Dropping Algorithm

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Conclusion

• Simple horizontal compression techniqueCircuit netlist independent (suitable for IPs)Test data independentSpecific tool independent

• Effective alternative to serializationCompacted test sequences vs fully specified

sequences

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Pattern Dropping Algorithm

For i=1 to #Pi in T

If fdi > fdi-1

Add Pi to T*

Fault simulation of T*

Number of detected faults: fdi

i++

i++

End For

NO

YES

Remove Pi from T*

New test sequence T*

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Column Ordering

Pattern Ordering

Compression

Pattern Dropping standard circuits only

Compression process summary

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Perspectives

Other sequential decompressor structuresCo-optimization test architecture / compression

test time: tam sizing / wrapper sizing / decompressor

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State Of The Art

At the CUT inputs (when test vectors are applied)

At the CUT outputs (when the test responses are checked)

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State of The ArtOutput Compression

• Time compaction (MISR based solutions)• Risk of aliasing

• Diagnosis difficult» Koenemann (IBM) ITC’01

• Spatial compaction (Xor trees based solutions)• Presence of unknown values

» Mitra ITC’02

• Mixed methodse.g. Convolutional compactors

» Rajski (MENTOR) ITC’04