1 imec / khbo june 2004 imec / khbo. 2 becoming an associated laboratory of imec was possible due to...
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IMEC / KHBOIMEC / KHBO
June 2004
IMEC / KHBOIMEC / KHBO
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IMEC / KHBOIMEC / KHBO
Becoming an associated laboratory of IMEC was possible due to the expertise built up in the Microelectronics group in the following fields: analogue and digital IC-design System integration (System-on-board, SoC) Higher level system integration methodologies
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Design methodologiesDesign methodologies
“nature of systems” change
Past - now FutureSmall block reuse Intelligent test benchesLarge block reuse Embedded system-levelIC implementation tools technologyPLDSystem-on-Chip
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Design history : evolution in the pastDesign history : evolution in the past
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From idea to a specificationFrom idea to a specificationHierarchical design flowHierarchical design flow
TOP DOWN
CAD-TOOLS BOTTOM UP
SYSTEM SIMULATION, SYNTHESIS,
LAYOUT TOOLS
ASIC, PLD SoC
System on board SUBSYSTEM SIMULATION,
SYNTHESIS, LAYOUT TOOLS
HIGH LEVEL IP BLOCKS
(e.g.ADC, MEMORIES) SUBSYSTEM GA & SC TOOLS
SIMULATION LAYOUT
LOW LEVEL IP BLOCKS
(e.g. GATES)
SUBSYSTEM TRANSISTOR LEVEL TOOLS
POLYGONES (LAYERS)
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Small block IP : basic building blocksSmall block IP : basic building blocks
SCHEMATIC LAYOUT
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Large block IP : 12-bit ADCLarge block IP : 12-bit ADC
•12-bit ADC
• current mode folding and interpolation
• 50 MHz
• 0.35 µm CMOS AME
• 34,5 mm2
• for telecom applications
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System-on-Board
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Example system-on-board (Coware)Example system-on-board (Coware)
DSP56002
FPGA
ROMRAM
EPROM
Supply
Analogue part
RS232 interfaceA/D
converter
D/Aconverter
DSP mode & IRQ
TestpinsTestpins
Testpins
Clock & Reset
Testpins
Digital part
Demonstrator for Coware development tools
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ESA project for PCDF-equipment in ISS
International Space Station (ISS)
Example of complete system developmentExample of complete system development
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Integration in the space-moduleIntegration in the space-module
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System-on-chipSystem-on-chip
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Example System-on-chip (FPLSIC)Example System-on-chip (FPLSIC)
FPLSIC = Field Programmable Level System Integration Circuit
3 basic components integrated in 1 integrated circuit :
SRAMPFGA Processor
Co-verification Build in power management
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FPSLIC embedded blocksFPSLIC embedded blocks
Configurable SRAM
SRAM interface
AVR/AT40
K inte
rface
• Software configurable interface between blocks already implemented• Pre-implemented Interface blocks save 2000-5000 FPGA gates
AT40K FPGA8 Bit RISC MCU
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User-Defined LogicUser-Defined Logic SpectrumSpectrum
ATF22V10ATF16V8ATF20V8
ATV2500BATF1500 FamATV750B
AT6000AT40K
ATL25 SeriesATL35 Series ATL50 SeriesATL60 Series
Decoders,Glue Logic
State machines,Timing, Control
RAM/Logic,Computing,Co-processing System Level Integration
De
nsi
ty
Macrocells0.25, 0.35, 0.5, 0.6 Analog / Digital
Analog / Digital/NV Memory, RF
PAL-Type
CPLD
FPGA
GateArray
Custom ASIC
FPSLIC
AT94K
Cell based ASIC
High Volume/Low Cost
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FPLSIC design flow from AtmelFPLSIC design flow from Atmel
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Co-verification, why ?Co-verification, why ?
Iteration Loop 1 to 3 Months
HardwareDevelopment
SoftwareDevelopment
SystemIntegration
PhysicalImplementation
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Co-verificationCo-verification
PhysicalImplementation
HardwareDevelopment
SoftwareDevelopment
Release to
Manufacturing
SystemIntegration
System Designer
Iteration Loop 1 to 3 Hours
Co-Verification
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Student diploma work with FPLSICStudent diploma work with FPLSIC
Low current contact sensing for reliability test of bonding wires
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Research Project : Test set-up for the study Research Project : Test set-up for the study of mechanical stress in chips of mechanical stress in chips
Test Equipment
Oven+
Wafer/Chip under test
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ContactContact
If you want to be informed about possible SOCRATES assignments
PLEASE CONTACT:
Ing.D.Gevaert, MPhilZeedijk 101, B-8400 OostendeTel 059/56 90 18e-mail: [email protected]