Broad family of TI’s 16-bit microcontrollers◦ from 1Kbytes ROM, 128 bytes RAM (approx. $1 )◦ to 60Kbytes ROM, 10Kbytes RAM ( $10)

Three subfamilies◦ MSP430x1xx: basic unit◦ MSP430x3xx: more features◦ MSP430x4xx: built-in LCD driver

The Family

Part numbering convention

F/C41xFx42x0

Fx42x

F44x

Perf

orm

ance

Integration

Future

Development

Sampling

Production

Device5xx-Next Gen• 25 MIPS• 32-256 KB • USB-RF

F21x1

2xx-Catalog• 16 MIPS• 1-120KB• 500nA Stand By

F13x-F14x

1xx-Catalog• 8 MIPS• 1-60KB

Fx43x

F20xx

F12xxF/C11xx

MSP430 Roadmap

F543x

F = FlashC = Custom ROM

4xx-LCD • 8/16 MIPS• 4-120KB• LCD Driver

F15x-F16x

F5xx RF

F21x2

F471x7

F23x-F24x

F5xx

F22xx

F261xF241x

CG461x

FG461x

F23x0

F563xUSB

F47x4

MSP430 Typical Applications

Handheld Measurement Air Flow measurement Alcohol meter Barometer Data loggers Emission/Gas analyser Humidity measurement Temperature measurement Weight scales

Medical Instruments Blood pressure meter Blood sugar meter Breath measurement EKG system

Home environment Air conditioning Control unit Thermostat Boiler control Shutter control Irrigation system White goods (Washing machine,..)

Misc Smart card reader Taxi meter Smart Batteries

Utility Metering Gas Meter Water Meter Heat Volume Counter Heat Cost Allocation Electricity Meter Meter reading system (RF)

Sports equipment Altimeter Bike computer Diving watches

Security Glass break sensors Door control Smoke/fire/gas detectors

MSP430G2231Architecture

RISC architecture with 27 instructions and 7 addressing modes. Full register access including program counter, status

registers, and stack pointer. Single-cycle register operations. Large 16-bit register file reduces fetches to memory. 16-bit address bus allows direct access and branching

throughout entire memory range. 16-bit data bus allows direct manipulation of word-wide

arguments. Constant generator provides six most used immediate values

and reduces code size. Direct memory-to-memory transfers without intermediate

register holding. Word and byte addressing and instruction formats.

CPU Introduction

CPU Registers

MSP430 16-bit RISC• Large 16-bit register file

eliminates single accumulator bottleneck

• High-bandwidth 16-bit data and address bus with no paging

• RISC architecture with 27 instructions and 7 addressing modes

• Single-cycle register operations with full-access

• Direct memory-memory transfer designed for modern programming

• Compact silicon 30% smaller than an ‘8051 saves power and cost

Complex Instruction Set Computer (CISC)◦ Memory in those days was expensive

bigger program->more storage->more money◦ Hence needed to reduce the number of

instructions per program◦ Number of instructions are reduced by having

multiple operations within a single instruction Reduced Instruction Set Computer (RISC)

◦ Provide minimal set of instructions that could carry out all essential operations

RISC vs. CISC

The difference between CISC and RISC becomes evident through the basic computer performance equation:

RISC systems shorten execution time by reducing the clock cycles per instruction (i.e. simple instructions take less time to interpret)

CISC systems shorten execution time by reducing the number of instructions per program

RISC vs. CISC

RISC vs. CISC Summary

RISC• Simple instructions, few in number• Fixed length instructions• Complexity in compiler• Only LOAD/STOREinstructions access memory• Few addressing modes

CISC• Many complex instructions• Variable length instructions• Complexity in microcode• Many instructions can access memory• Many addressing modes

Each instruction uses an even number of bytes (2, 4, or 6)

PC is word aligned (the LSB is 0)

MOV #LABEL,PC ; Branch to address LABEL

MOV LABEL,PC ; Branch to address contained in LABEL

MOV @R14,PC ; Branch indirect, indirect R14

Registers: PC (R0)

Registers: SP (R1)• Stack pointer for return addresses of

subroutines and interrupts• SP is word aligned (the LSB is 0)• Pre-decrement/post-increment scheme

PUSH #0123h ; Put 0123h onto TOSPOP R8 ; R8 = 0123h

CPE/EE 421/521 Microcomputers

15

◦ C: SR(0)◦ Z: SR(1)◦ N: SR(2)◦ GIE (Global interrupt enable): SR(3)◦ CPUOff: SR(4)◦ OSCOff: SR(5)◦ SCG1, SCG0: SR(7), SR(6)◦ V: SR(8)

Registers: SR (R2)

CPE/EE 421/521 Microcomputers

16

Status bits

17

As – source register addressing mode in the instruction word

Constant Generators

For example, consider an "increment" instruction "INC R2"; many architectures have a special instruction to implement this.  Others will implement it as "add #1, R2", where you'll have to have "1" in a memory location somewhere.  On the MSP430, the constant "1" comes from the constant generator, so it doesn't take any extra memory, nor a special instruction.

Constant Generators

19CPE/EE 42/521 Microcomputers

27 Core RISC Instructions

CPE/EE 421/521 Microcomputers

20

51 Total Instructions

21

Double operand instructions

22

Single Operand Instruction

23

Jump Instructions

24

3 Instruction Formats

25

Addressing Modes

Register Mode

RISC 16-Bit CPU

Indexed Mode

RISC 16-Bit CPU

Symbolic Mode

RISC 16-Bit CPU

Absolute Mode◦ This address mode is

mainly for hardware peripheral modules that are located at an absolute, fixed address.

◦ These are addressed with absolute mode to ensure software transportability (for example, position-independent code).

RISC 16-Bit CPU

Indirect Register Mode

RISC 16-Bit CPU

Indirect Autoincrement Mode

RISC 16-Bit CPU

Immediate Mode

RISC 16-Bit CPU

One address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory.

Memory Organization

Flash ROM:◦ The start address of

Flash/ROM depends on the amount of Flash/ROM present and varies by device. The end address for Flash/ROM is 0FFFFh.

◦ Flash can be used for both code and data.

◦ The interrupt vector table is mapped into the the upper 16 words of Flash/ROM address space, with the highest priority interrupt vector at the highest Flash/ROM word address (0FFFEh).

Memory Organization

RAM:◦ RAM starts at 0200h.◦ The end address of

RAM depends on the amount of RAM present and varies by device.

◦ RAM can be used for both code and data.

Memory Organization

Peripheral Modules 16 bits:◦ The address space

from 0100 to 01FFh is reserved for 16-bit peripheral modules. These modules should be accessed with word instructions.

◦ If byte instructions are used, only even addresses are permissible, and the high byte of the result is always 0.

Memory Organization

Peripheral Modules 8 bits:◦ The address space from

010h to 0FFh is reserved for 8-bit peripheral modules.

◦ These modules should be accessed with byte nstructions. Read access of byte modules using word instructions results in unpredictable data in the high byte.

◦ If word data is written to a byte module only the low byte is written into the peripheral register, ignoring the high byte.

Memory Organization

Special Function Registers (SFRs):◦ Some peripheral

functions are configured in the SFRs. The SFRs are located in the lower 16 bytes of the address space, and are organized by byte.

◦ SFRs must be accessed using byte instructions only. See the device-specific data sheets for applicable SFR bits.

Memory Organization

Bytes are located at even or odd addresses.

Words are only located at even addresses as shown.

When using word instructions, only even addresses may be used.

The low byte of a word is always an even address. The high byte is at the next odd address.◦ For example, if a data word is

located at address xxx4h, then the low byte of that data word is located at address xxx4h, and the high byte of that word is located at address xxx5h.

Memory Organization

If the selected time interval expires, a system reset is generated.

If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

Watchdog Timer

Features:◦ Four software-selectable time intervals◦ Watchdog mode◦ Interval mode◦ Access to WDT control register is password

protected◦ Selectable clock source◦ Can be stopped to conserve power◦ Clock fail-safe feature in WDT+

Watchdog Timer

Watchdog Timer

WDTCTL