1 introduction to analog ic design

7/27/2019 1 Introduction to analog IC design

1/41

Puebla, December 2004

ICTP Microprocessor Laboratory

Second Central American Regional Course on Advanced VLSI Design Techniques

Benemrita Universidad Autnoma de Puebla, Puebla, Mexico

29 November 17 December 2004

Introduction to Analog Design

in SubmicronCMOS Technologies

Giovanni AnelliCERN - European Organization for Nuclear Research

Physics Department

Microelectronics GroupCH-1211 Geneva 23 Switzerland

[email protected]


2/41

Giovanni Anelli, CERNPuebla, December 2004

The MOST important thing


3/41


A second tip

sRC

1

)s(V

)s(V)s(H

in

out gs

mmax

C

g

2

1f f

R

kT4i2n = 2/T 2/T 2av dt)t(xT1limP

2

2

2

)x(

e2

1

)x(p

)e1(eL

WII t

DS

t

GS

n

V

n

V

0DDS f1WLC Kg1kTn4fv 2ox am2

in

2

t

DS

n2

I.C.I

q

kTt =

( ) 21.C.I414

1

.C.I

6

1

2

1.)C.I(F

++

2

2

BGD,n

2

TOT,n

DUT,n

)f(G

)f(V)f(V)f(E

=

LW

A

LW

A2

C2

ox+2 /

LWtConst oxVth

4

N

d)l

d(FnL 2

A

dn

A

lR w

22204

0

2

nnh8

qmZE =

2

TGSDS )VV(n2

I =

DSTGS

GS

DSm I

n2)VV(

nVIg === )VV(1 TGS

0 =

SAT_DS

E

SAT_DSds

0I

LV

I

1

g

1r =


4/41Giovanni Anelli, CERNPuebla, December 2004

The last warning before we start

The transparencies I wil l show you are sometimes quite

full of details. You wil l not have the time to digest all

these details this week, but I wanted to prepare thetransparencies so that you will have a COMPLETE

material for future reference.

During the presentation, I will help you in identifying inthe transparencies and in the formulas the most

important issues that you should retain.

I also made a special effort in referencing all the sources

(books and papers) I have been using when preparing the

lectures. This should help you in finding easily what you

do not find in the transparencies



Outline

Semiconductor physics

Silicon and silicon dioxide properties

Band diagram concept

Intrinsic and doped semiconductors

Carrier mobility in silicon

CMOS technology: an analog designer perspective

The MOS transistor

DC characteristics

Important formulas

Small signal equivalent circuit

Some cross sections of real integrated circuits



Outline







The MOS transistor

DC characteristics

Important formulas





Insulators and (semi)conductors

S. M. Sze, Semiconductor Devices, Physics and Technology , John Wiley and Sons, 1985, p. 1



Physical Properties of Si and SiO2

at room temperature (300 K)

Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambr idge Universi ty Press, 1998, p. 11.



Silicon crystalline structure

Diamond

lattice

structure

Covalentbonding

Orbitals

filling

3p2

3s2

2p6

2s2

1s2

a = 0.513 nm

for Silicon

NucleusS. M. Sze, Semiconductor Devices, Physics and Technology , John Wiley and Sons, 1985, p. 5.

Linus Pauling, General Chemistry, Dover, 1988, p. 128.



From energy levels to bands

Allowed

energy levels

E1

E2

E3

En

E0 (reference)

222

0

4

0

2

nnh8

qmZE =

putting more

atoms together

(and rememberingPaulis exclusion

principle)

Allowedenergy bandZ: atomic number

m0: free electron mass

q: electron charge

0: permittivity free spaceh: Plancks constant

n: positive integers

(level number)

Forbidden

energy gap

x


11/41


Energy-band diagrams

Insulator Semiconductor Conductor Conductor

Valence

Band

ConductionBand

Energy

Gap

Valence

Band

ConductionBand

Valence

Band

Conduction

Band

Energy Gap

Conduction

Band

Empty allowed

energy band

Full allowed

energy band


12/41


Intrinsic and doped silicon

Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge Univers ity Press, 1998, pp. 10, 13, 14.

E. S. Yang, Microelectronic Devices, McGraw-Hill International Editions, 1988, pp. 9, 15.

Fictitious particle


13/41


Donors and acceptors

Intrinsic Semiconductor: small amount of impurit ies compared to the

thermally generated electrons and holes

Donor level: the allowed energy level provided by a donor is neutral

when occupied by an electron and positively charged when empty

Acceptor level: the allowed energy level provided by an acceptor is

neutral when empty (= occupied by a hole) and negatively charged

when occupied by an electron (= empty)Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambr idge Universi ty Press, 1998, p. 15.


14/41


Carrier density vs Temperature

N-type semiconductor

Electrons are themajority carriers

Intrinsic carrier density

(= hole density)

kT

E

vc

2

i

g

eNNn

S. M. Sze, Semiconductor Devices, Physics and Technology , John Wiley and Sons, 1985, p. 27


15/41


Mobility vs T and ND

ND: doping concentration

EEm

qv n

e

md

vd = drift velocity

m = mean free time between coll isionsme = conductivity effective mass

E = electric field

S. M. Sze, Semiconductor Devices, Physics and Technology , John Wiley and Sons, 1985, p. 33.


16/41


Mobility vs doping


SIL

1111 = total mobil ityL = mobil ity due tolattice scattering

I = mobility due toimpurity scatteringS = mobil ity due tosurface scattering

(the dominating

factor in MOStransistors)

It is like for resistors

in parallel: the

smaller dominates!


17/41


Carrier velocity vs Electric Field

R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits , 2nd Edition, John Wiley and Sons, 1986, p. 36.


18/41


Resistivity vs doping

)pn(q1

pn q = electronic charge = resistivity

n, p = carrier concentration

n, p = carrier mobil ity



19/41


Outline







The MOS transistor

DC characteristics

Important formulas



Th MOS i


20/41


The MOS transistor

x

y

z

GATE

SOURCE

DRAIN

SUBSTRATE GSmDS

vgi Transconductance

Y. Tsivid is, Operation and Modeling of The MOS Transistor, 2nd edit ion, McGraw-Hill, 1999, p. 35

CMOS t h l


21/41


CMOS technology

NMOS PMOS

GG

n+ n+p+ p+ p+ n+

S Dsub S D well

n-wellp-substrate

Polysilicon

OxideElectrons

Holes

n+ source

n+ drain

NMOS

layoutG

Li d S t ti i


22/41


Linear and Saturation regions

LINEAR REGION (Low VDS):

Electrons (in l ight blue) are attracted to

the SiO2 Si Interface. A conductive

channel is created between source anddrain. We have a Voltage Controlled

Resistor (VCR).

G

n+ n+

S D

SATURATION REGION (High VDS):

When the drain voltage is high enough

the electrons near the drain are

insuff iciently attracted by the gate, andthe channel is pinched off. We have a

Voltage Control led Current Source

(VCCS).

G

n+ n+

S D

D i t D i lt


23/41


Drain current vs Drain voltage

0.0E+00

5.0E-06

1.0E-05

1.5E-05

2.0E-05

2.5E-05

3.0E-05

0.0 0.5 1.0 1.5 2.0 2.5

VDS [ V ]

IDS

[A

]

Saturation region (VCCS)

Linear region (VCR)

Output conductance

@ three

different VGS

Locus of IDS_SAT vs VDS_SAT

E ti t i i


24/41


Equations: strong inversion

DSDS

TGSDS V)2

nVVV(I LINEAR REGION:

SAT_DSTGS

DS Vn

VVV =

Transconductance:

L

WCoxx.1g

ggn

m

mbm =ox

SiO

oxtC

2

=BS

DSmb

V

Ig

=

D i t G t lt


25/41


Drain current vs Gate voltage

0.E+00

2.E-04

4.E-04

6.E-04

8.E-04

1.E-03

1.E-03

1.E-03

2.E-03

-0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4

VGS [ V ]

IDS[

A

]

Subthreshold

region

Linearreg

ion(green)and

saturatio

nregion(red)

High field

(vertical andlongitudinal)

effects

Log(I ) vs V


26/41


Log(IDS) vs VGS

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4

VGS [ V ]

IDS[

A

]

LEAKAGE

CURRENT

THRESHOLD

VOLTAGE

STRONGINVERSION

WEAK

INVERSION

SUBTHRESHOLD

SLOPE

Equations: weak inversion


27/41


Equations: weak inversion

)e1(eL

WII t

DS

t

GS

n

V

n

V

0DDS

then the drain current does not depend on

VDS any longer (saturation)If tDS n4V

t

GSnV

0DDS eL

WII =t

DS

GS

DSm

n

I

V

Ig =Almost like a bipolar transistor!

K300mV25q

kTt @

Transcond vs Gate voltage


28/41


Transcond. vs Gate voltage

0.E+00

1.E-05

2.E-05

3.E-05

4.E-05

5.E-05

6.E-05

7.E-05

8.E-05

9.E-05

1.E-04

-0.35 0.05 0.45 0.85 1.25 1.65 2.05 2.45

VGS [ V ]

gm

[S]

Measurement

made in the linear

region

Output conductance


29/41


Output conductance

0.0E+00

5.0E-06

1.0E-05

1.5E-05

2.0E-05

2.5E-05

3.0E-05

0.0 0.5 1.0 1.5 2.0 2.5

VDS [ V ]

IDS[

A

]

VI

VDS

VD

VD

IDS

ID

ID

n+ n+

SG

D

LL

Dashed lines:ideal behavior

L-L

L

V

I

V

IG

D

out =

=

Equations: output conductance


30/41


Equations: output conductance

)V1()VV(n2

I DS2

TGSDS =

2

SAT_DS

2

TGSSAT_DSnV

2)VV(

n2I

==

nVVV TGSSAT_DS =

0.0E+00

5.0E-06

1.0E-05

1.5E-05

2.0E-05

2.5E-05

3.0E-05

0.0 0.5 1.0 1.5 2.0 2.5

VDS [ V ]

IDS[

A

]

SAT_DS

DS

DSdsout I

VIgg =

SAT_DS

E

SAT_DSds

0I

LVI

1g1r =

)N,V(fLLL

L

V

1DopingDS

DSwhere =

Equations: addendum


31/41


Equations: addendum

( )SiSisbT VV ox

aSi

C

Nq2 =Bulk effect

Sm

m'

mRg1

gg +Source parasiticresistance

)VV(1 TGS

0 = Vertical electricfield effect)VV(

nL2

1

C

g

2

1f TGS2

gs

mmax in s.i.Maximumfrequency

K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994, Chapter 1

Equations: velocity saturation


32/41


Equations: velocity saturation

For low values of the longitudinal electric field, the velocity of the

carriers increases proportionally to the electric field (and the

proportionality constant is the mobility). For high values of the electric

field (3 V/m for electrons and 10 V/m for holes) the velocity of thecarriers saturates.

s

cm10v)VV(vWCI 7satTGSsatox.S.V_DS with =

satox.S.V_m vWCg =L

v

2

1

C

g

2

1f sat

gs

m.S.Vmax_

g / I vs log(I / W)


33/41


gm / ID vs log(ID / W)

0

5

10

15

20

25

30

1E-11 1E-09 1E-07 1E-05 1E-03

ID / W

g

m

/ID

W.I.

M.I.

S.I.

&

V.S.

Weak Inversion (W.I.)

t

DSm

n

Ig = tD

m

n

1

I

g

=

Strong Inversion (S.I.)

DSm In

2g=

DSD

m

I

1

n2

I

g =

Velocity Saturation (V.S.)

satoxm vWCg =DS

satox

DS

m

I

vWC

I

g =

Log(g / ID) vs log(ID / W)


34/41


Log(gm / ID) vs log(ID / W)

0.1

1

10

100

1E-11 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04 1E-03

ID

/ W

gm

/ID

Slope = - 0.5

Strong inversion

Slope = - 1

Velocity saturation

The poor PMOS transistor


35/41


The poor PMOS transistor

G

DRAIN

SOURCE

2

TGSDS )VV(n2I

DS

TGS

GS

DSm

In2

)VV(n

V

Ig

=

==

-3.0E-05

-2.5E-05

-2.0E-05

-1.5E-05

-1.0E-05

-5.0E-06

0.0E+00

-2.5 -2.0 -1.5 -1.0 -0.5 0.0

VDS [ V ]

IDS[

A

]

p+ p+ n+

S D well VT < 0 V

VGS < 0 V

IDS < 0 V

GATE WELL

n-well

-2.E-03

-1.E-03

-1.E-03

-1.E-03

-8.E-04

-6.E-04

-4.E-04

-2.E-04

0.E+00

-2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4

VGS [ V ]

IDS[

A

]

Small-signal equivalent circuit


36/41



gsmvg 0r

G

S

D

GSmDS vgi 2

TGSQDSQ )VV(n2

I = This equation fixes the bias pointThis equation defines the small signal behavior

K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994, p. 24.

Small-signal equivalent circuit


37/41



gsmvg bsmbvg 0r

sbC

gsC

dbCgbC

gdC

DG

S

B

The real thing!


38/41


The real thing!

SOI technology from IBMhttp://www-3.ibm.com/chips/gallery/

The real thing!


39/41


The real thing!

Metallization exampleshttp://www-3.ibm.com/chips/gallery/

Why is CMOS so widespread?


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Why is CMOS so widespread?

The IC market is driven by digital circuits (memories,microprocessors, )

Bipolar logic and NMOS - only logic had a too high

power consumption per gate Progress in the manufacturing technology made CMOS

technologies a reality

Modern CMOS technologies offer excellent

performance (especially for digital): high speed, lowpower consumption, VLSI, low cost, high yield

CMOS technologies occupies anincreasing portion of the IC market

and this is why we will only talk about CMOS.

The next three lectures


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e e ee ec u es

Lecture 2: Noise and Matching in CMOS (Analog) Circuits

Lecture 3: Scaling Impact on Analog Circuit Performance

Lecture 4: Basic Building Blocks for Analog Design

1 introduction to analog ic design

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