1 kw solid-state power amplifier at 100 mhz for use in ...845119/...opportunity to perform this...
TRANSCRIPT
FREIA Report 2015/05
15 June 2015
Department of
Physics and Astronomy
Uppsala University
P.O. Box 516
SE – 751 20 Uppsala
Sweden
Papers in the FREIA Report Series are published on internet in PDF format.
Download from http://uu.diva-portal.org
DEPARTMENT OF PHYSICS AND ASTRONOMY
UPPSALA UNIVERSITY
1 kW Solid-State Power Amplifier at 100 MHz for Use in Cyclotron
Authors: David Johansson and Jacob Fredriksson
Supervisor: Dragos Dancila
FREIA, Uppsala University, Uppsala, Sweden
This report results from a Master thesis conducted at Uppsala University, FREIA Laboratory, in collaboration with General Electric Medical Systems (GEMS) PET. The thesis was examined
at Linköping University, campus Norrköping, at the department of science and technology.
Abstract The latest development in LDMOS transistor technology has enabled it as a replacement
for the traditional electron tube amplifiers, making the amplifiers more efficient and less
expensive. The thesis set out to investigate whether it was possible to achieve a 1 kW
amplifier at 100 MHz using LDMOS transistors. Moreover, the 1 kW amplifier has to
meet the demands of a cyclotron used in medical applications.
Two different power amplifiers have been designed, fabricated and measured, showing
promising results. The first one utilises a single-ended topology to make the design as
simple as possible. The second one is a push-pull amplifier using planar BALUN
structure for phase shift and impedance transformation. At relatively low frequency of
100 MHz, both the single-ended amplifier and the push-pull amplifier make use of
unusual design approaches. That makes this theses work within a relatively unexploited
research area.
Acknowledgements The thesis authors would like to give a thank you to everybody involved in the thesis.
Andriana Serban for help and support, Magnus Karlsson for his never-ending
engagement. Lars-Erik and Sone at the mechanical workshop at Uppsala University for
their help in making the heatsinks. The FREIA group and Anders Rydberg for letting us
use the facilities at Ångström laboratory.
A special thanks goes out to Andreas Bäcklund at GEMS PET for giving us the
opportunity to perform this project and his support during it. Also a special thanks to
Dragos Dancila for his support and help with the thesis.
Abbreviations and Acronyms ADS - Advanced Design System
BALUN – BALanced UNbalanced CAD – Computer Aided Design
CST – Computer Simulation Technology
CW – Continuous Wave
dB – DeciBel
dBm – Decibel-milliwatts
DC – Direct Current
DUT – Device Under Test EM – Electro Magnetic
GE – General Electric
GEMS - General Electric Medical Systems
HF – High Frequency
IDS – Current Drain Source IMD – InterModulation Distortion
kW – Kilo Watt
LDMOS – Laterally Diffused Metal Oxide Semiconductor
MHz – Mega Hertz
mW – milli Watt
NI AWR – National Instruments Applied Wave Research
PA – Power Amplifier
PAE – Power Added Efficiency
PCB - Printed Circuit Board
PET – Positron Emission Tomography
RF – Radio Frequency
VDS –Drain Source Voltage
VGS –Gate Source Voltage
Table of Contents Chapter 1 ............................................................................................................................................................. 3
Introduction ....................................................................................................................................................... 3 1.1 Background ............................................................................................................................................................. 3 1.2 Purpose and Objective ........................................................................................................................................ 4 1.3 Methodology ........................................................................................................................................................... 5
Chapter 2 ............................................................................................................................................................. 7
Theoretical Background................................................................................................................................ 7 2.1 RF Power Amplifiers ........................................................................................................................................... 7
2.1.1 Efficiency ......................................................................................................................................................... 8 2.1.2 Classes of Operation ................................................................................................................................... 8 2.1.3 Power Amplifier Parameters ................................................................................................................ 10
2.2 Matching Networks ........................................................................................................................................... 11 2.2.1 Matching Using Lumped Components .............................................................................................. 12 2.2.2 Matching Using Distributed Elements .............................................................................................. 13 2.2.3 Smith Chart .................................................................................................................................................. 14
2.3 BALUN Theory ..................................................................................................................................................... 16
Chapter 3 .......................................................................................................................................................... 19
Transistor Characteristics Evaluation .................................................................................................. 19 3.1 NXP BLF188XR .................................................................................................................................................... 19
3.1.1 DC Simulation .............................................................................................................................................. 19 3.1.2 Stability Analysis ....................................................................................................................................... 21 3.1.3 Load-pull Analysis ..................................................................................................................................... 21
3.2 NXP BLF571 .......................................................................................................................................................... 22 3.2.1 DC Simulation .............................................................................................................................................. 23 3.2.2 Stability Analysis ....................................................................................................................................... 24 3.2.3 Load-pull Analysis ..................................................................................................................................... 24
Chapter 4 .......................................................................................................................................................... 27
Single-Ended Design .................................................................................................................................... 27 4.1 Lower Dielectric Constant (𝜺𝒓 = 𝟑) Design ............................................................................................ 28 4.2 Higher Dielectric Constant (𝜺𝒓 = 𝟗) Design .......................................................................................... 30
Chapter 5 .......................................................................................................................................................... 35
Push-Pull Design ........................................................................................................................................... 35 5.1 Planar BALUN design ........................................................................................................................................ 35 5.2 Matching Network Push-Pull for Power Amplifier ............................................................................... 39 5.3 Push-Pull Amplifier ........................................................................................................................................... 40
Chapter 6 .......................................................................................................................................................... 43 Preamplifier Design .................................................................................................................................................. 43
6.1 Preamplifier Design...................................................................................................................................... 44
Chapter 7 .......................................................................................................................................................... 47
Manufacturing & Measurements ............................................................................................................ 47 7.1 PCB Manufacturing ............................................................................................................................................ 47 7.2 Heat Sink Design and Manufacturing ......................................................................................................... 47 7.3 Measurements Setup......................................................................................................................................... 48
7.3.1 Power Measurement Setup ................................................................................................................... 48 7.4 Single-Ended PA Measurements .................................................................................................................. 50 7.5 Push-Pull Measurements ................................................................................................................................ 54
Chapter 8 .......................................................................................................................................................... 57
Discussion and Conclusion ....................................................................................................................... 57 8.1 Conclusion of Single-ended Design ............................................................................................................. 57 8.2 Conclusion of Push-Pull Design .................................................................................................................... 58 8.3 Simulation and Measurement ....................................................................................................................... 59 8.4 Thesis Conclusion ............................................................................................................................................... 60
References ....................................................................................................................................................... 61
Appendix A .......................................................................................................................................................... i A.1 Harmonic Balance Simulations Equations ................................................................................................... i A.2 Stability Simulation Equation ........................................................................................................................... i
Appendix B - Heat Sink Drawings ............................................................................................................. ii B.1 Single-Ended Heat Sink Drawing ................................................................................................................... ii B.2 BALUN Heat Sink Drawing .............................................................................................................................. iii B.3 Heat Sink GE .......................................................................................................................................................... iv B.4 Single-Ended Amplifier ....................................................................................................................................... v B.5 Push-Pull amplifier ............................................................................................................................................... v
Appendix C ........................................................................................................................................................ vi C.1 Bill of Materials (BOM) ...................................................................................................................................... vi
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Chapter 1
Introduction Since 1993 General Electric (GE) has been developing, manufacturing and testing
cyclotrons for Positron Emission Tomography (PET) scanning in Uppsala. A cyclotron is
a machine used to accelerate particles to a very high kinetic energy by an alternating
current. The particles are then released in order to bombard a target. The target consists
of a fluid form of oxygen that transforms into a radioactive form of fluorine when it is
bombarded by radionuclides. The radioactive fluorine is later injected into patients
when scanning for cancer, since the tumours appear visible to a PET camera because of
beta decay when fluorine transforms back to oxygen.
1.1 Background General Electric is one of the world’s largest companies, with more than 300 000
employees and is present in 140 countries [1]. Their portfolio stretches from bank to
healthcare. It is only the healthcare division that is partly located in Uppsala. In Uppsala,
GE Healthcare is the second largest employer after Akademiska Sjukhuset. GE has two
sites, one is producing biological research solutions and the other one is General Electric
Medical Systems (GEMS) PET, producing cyclotrons.
In order to enable a greater access in emerging and developing countries to cancer and
neurodegenerative disease diagnosis, a new compact cyclotron is under development. A
further benefit with the new machine is that it could be installed in smaller hospitals
enabling them to produce their own radionuclides instead of having them delivered
there. The transportation is a problem because the half-life of the produced fluorine is
only one and a half hour. A sub-part of the cyclotron is the radio frequency (RF)
generator that is supplying the machine with a high voltage potential to the accelerator
cavity. In older GE cyclotrons the RF generator has been based on electron tube
technology. Now although, the developments of the LDMOS RF transistor has enabled
the design solution to be more efficient and less expensive and at the same time meet
the requirements when used in a particle accelerator.
Since running a cyclotron is based on a very high-technological equipment and demands
very narrow specifications, small deviations in the performance of the amplifier can
cause the cyclotron not to function. This has been a problem since the manufacturer of
the amplifier used in the prototype today, has been changing the design and replacing
components while claiming the same functionality. However, when running the
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cyclotron with the “same” amplifier GE has discovered that is not the case. Due to these
reasons GE has initiated this work enabling them to take control over the amplifier
design and manufacturing.
1.2 Purpose and Objective
The aim of this thesis is to design, fabricate and measure a prototype of a 1 kW solid-
state RF power amplifier for a new cyclotron that is producing radionuclides used in
PET scanning. The result includes theory of amplifier design and possible solutions,
choice of amplifier architecture and components, schematic and printed circuit board
(PCB) layout, simulations of the design in Advanced Design System (ADS), prototype
manufacturing and testing as well as documentation.
The development of the amplifier can be divided into three parts; design, fabrication and
measurements of a 5 W preamplifier and a 1 kW power amplifier (PA) both running at
100 MHz. A more thorough specification of the amplifiers can be found in Table 1. The
prototype amplifiers will be tested, evaluated and eventually implemented in the new
cyclotron that is under development.
Characteristics Test Conditions MIN MAX UNIT
Operating frequency 99 102 MHz
Flatness over frequency
band
0.1-1 kW output
power ±0.5 dB
Fundamental output
power 1.0 kW
Power gain 1 kW output power 50 dB
Power gain flatness 0.1-1 kW output power ±3 dB
Rise time To 80% output power 100 ns
Output VSWR tolerance @
any angle
Fail safe operation at CW
80% output power 4:1
Input VSWR 1.6:1
Input power (tolerance) 50 mW
Efficiency 1 kW output power 75 %
THD 1 kW output power 30* W*
THD 1 kW output power 18 %
Vdd max 50 V
W L H
Measurements In mm 75 270 27 * Harmonic absorber power rating
Table 1 Amplifier Specifications from GE
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1.3 Methodology
The design of RF power amplifiers requires theoretical knowledge of electronics,
physics and power amplifier parameters. The thesis will start with a theoretical study on
PA topologies and specific parameters. The sources of information will be various
textbooks, scientific articles and other technological information such as transistor data
sheets and applications notes. The significant theory is presented in this thesis and is
used as a foundation when selecting amplifier topologies.
Two PAs will be developed in parallel, so both authors can work on one amplifier each.
The amplifiers will be simulated from transistor level to finished amplifier to ensure that
the solution is solid and functional. Simulation results will be presented in the report for
the two different solutions. Apart from the main task of developing a power amplifier, a
preamplifier and a heat sinks should be produced.
The simulations and design will be made in different design and simulation computer
softwares. The main program used during this thesis will be Advanced Design System
(ADS). This simulation program is a useful tool when developing RF systems. For more
complex electrical 3D structures, Computer Simulation Technology (CST) will be used.
Mechanical designs will be performed in Sketchup, which is a Computer Aided Design
(CAD) program.
Printed circuit boards (PCB) for the amplifiers will be manufactured by professional
companies and manually assembled. However to advance to process, the authors will
manufacture a prototype in order to start the measurements. Measurements will be
performed stepwise in an electrical lab. To ensure the simulations are correlating with
the reality, different parameters will be measured before the design is tested as an
amplifier.
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DC bias networks
Input network
Output network
Transistor
Source ZS=50 Ω
Load ZL=50 Ω
Chapter 2
Theoretical Background This chapter provides theory about radio frequency (RF) power amplifiers (PA) design.
It will give theoretical insight on PA design as well as practical design guides on how to
implement the PA
2.1 RF Power Amplifiers An RF power amplifier basically consists of four blocks, a transistor as the active device,
input matching network, output matching network, and direct current (DC) bias
network. The block diagram of a general RF power amplifier is shown in Figure. 2.1. The
task of the input and output matching network is to transform the input and output
impedance of the transistor into the required reference impedance of 50 Ω. The
matching network also helps stabilise the amplifier and prevent it from oscillation. The
purpose of the DC bias network is to provide a quiescent point for the transistor,
thereby it can be operated under specified conditions and maintain a constant setting,
independent of transistor parameter variations. Depending on how it is biased,
amplifiers have different classification. This section will give a brief introduction to
amplifier classes and will further cover essential parameters for designing of amplifiers,
for example stability parameters, gain and gain flatness. [2]
Figure 2.1 Block diagram of a general RF power amplifier
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2.1.1 Efficiency The efficiency is an important parameter of a power amplifier, especially in devices
powered by battery where the amplifier is the main consumer of DC power. There are
several ways of deriving the efficiency. The most common way is to define the efficiency
𝜂 as the ratio between the RF power delivered to the load and the power supplied by the
DC source on the drain side of the transistor, as shown in (2.1).
𝜂 = 𝑃𝑂𝑢𝑡
𝑃𝐷𝐶 × 100 % (2.1)
However, this definition does not take into account how much RF power that is supplied
to the amplifier. By considering the input power, the Power Added Efficiency (PAE) is
measured and is defined as (2.2), where G is the gain of the amplifier, measured in dB.
[2, 3]
𝑃𝐴𝐸 = 𝑃𝑂𝑢𝑡−𝑃𝐼𝑛
𝑃𝐷𝐶= (1 −
1
𝐺)
𝑃𝑂𝑢𝑡
𝑃𝐷𝐶= (1 −
1
𝐺) 𝜂 (2.2)
2.1.2 Classes of Operation The classes of operation can be divided into two or three groups depending on how the
transistor is operated. If the transistor is operated as a dependent current source, the
classifications is either Class- A, AB, B or C. The difference between these classes is the
conduction angle of the drain current. The amplifier can also be operated in Class D, E
and DE, in these cases the transistor is operated as a switch. If the transistor is operated
in a combination of a dependent current source and a switch the class of operation for
the amplifier is Class F. [4] There are also a few more classes of operation that can be
added to the second and third group of amplifiers.
Class A: The bias point for the transistor is chosen so that the input signal swing never
exceeds the linear region for the transistor, the result is an output signal that is a
amplified copy of the input signal without harmonics. Harmonics will be added, if the
power of the input signal is increased making the transistor go into the non-linear
region. Class A amplifier have a conduction angle of 360° (θ = 2π), the transistor is
conducting the entire cycle of the input signal. Because the transistor is constantly open,
there will be a large quiescent current dissipating heat, which will decrees the efficiency.
The maximum theoretical efficiency for Class A is 50 %. [5]
Class B: The Class B amplifier is biased on the edge of conduction, the input signal is
driving the transistor into conduction during the positive half period of the signal. The
conduction angle is 180° (θ = π). No current will flow during the negative half period
when the transistor is closed; the result is lower heat dissipation in comparison to Class
A amplifiers. The maximum theoretical efficiency of Class B is 78.5 %. [5]
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Class AB: The Class AB amplifier is operated between Class A and B, the conduction
angle is between 180° and 360°. The efficiency is therefore between 50 % (biased as
Class A) to 78.5 % (Biased as Class B). [5]
Class C: A conduction angle of less than 180°, gives an amplifier operated in Class C.
Class C amplifier can reach efficiency values close to 100 %, depending on the bias point.
Harmonics will also be added to the output signal. [5]
Figure 2.2 Waveforms of the drain current iD in various classes of operation; (a) Class A (b) Class B
(c) Class AB (d) Class C [4]
A way to decrease the signal integrity in Class B is to drive the amplifier in a push-pull
configuration, by using two transistors in parallel to complement each other. The push-
pull amplifier cancels the second harmonic and lowers the impact on signal integrity.
One transistor is driving the positive half period of the signal and the other is driving the
negative half period of the signal. The transistors complement each other for a higher
efficiency. A simple push-pull configuration can be seen in Figure 2.3.
Figure 2.3 Class B push-pull configuration
Inp
Inn
Outp
Outn
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Pout ,dBm
1dB compression point Pout, 1dB
Pin, 1dB Pin ,dBm
2.1.3 Power Amplifier Parameters To achieve a good amplifier design, independent of amplifier topology there are several
parameters that has to be taken into consideration. This section of the report will cover
some of the most important parameters when designing a PA.
Designing a PA implies that the otherwise used small-signal S-parameters are not valid
and large-signal S-parameter have to be considered. When operated at higher power,
the amplifier is no longer operating in the linear region; therefore a small signal
approximation is not valid anymore. However, small-signal S-parameters can be used
for analysing the stability of the transistor and for Class A PA.
Another important parameter for characterizing the PA is the 1-db compression point.
Where the theoretical characteristic of the amplifier is compared to a simulated one to
calculate the gain compression. At lower input power levels, these curves are
proportional. As the power increases the gain of the non-theoretical amplifier decreases.
The transistor begins to compress when it reaches the saturated region, i.e, the output
no longer follows the input linearly. To avoid distortion and other undesired factors that
could create noise the amplifier should not be driven with input power beyond the 1-dB
compression point. This point is located where the simulated curve deviates by 1-dB
from the theoretical curve. This relationship is illustrated in Figure 2.4, where the dotted
line is the theoretical amplifier performance and the solid line is the actual performance.
Figure 2.4 1 dB compression point
Since power amplifiers are operated in or close to the nonlinear region, they create
harmonic distortion, a kind of noise that is a multiple of the fundamental frequency. The
harmonic distortion is increased with the class of operation when the efficiency
increases. This is an undesired effect, which decreases the efficiency of the amplifier.
However, in Class F the harmonics are used to increase the efficiency of the amplifier,
which can be as high as 90-100 % depending on how many harmonics that are utilized.
Another undesired effect occurring in power amplifiers is the intermodulation
distortion (IMD). IMD has its highest effect in the high power region where the
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transistor is in the nonlinear region. This type of distortion is noticeable when two input
signals of different frequencies are applied to an amplifier. The two signals undergoing a
non-linear amplification generate other signals of frequency, 𝑓1and𝑓2. That creates apart
from the predictable output signals extra signals that is a mixture of the two input
signals. Equation (2.3) defines the intermodulation distortion, as the point where the
IMD is at the proportion of the square wave of the input power is called intercept point
(IP3). [2]
𝐼𝑀𝐷[𝑑𝐵] = 𝑃𝑜𝑢𝑡(𝑓2)[𝑑𝐵𝑚] − 𝑃𝑜𝑢𝑡(2𝑓2 − 𝑓1)[𝑑𝐵𝑚] (2.3)
Stability is another important factor when designing a power amplifier and is something
that has to be achieved over the entire frequency range. If the stability conditions are
not fulfilled the amplifier may start to oscillate, an undesired effect that is potentially
harmful for the amplifier. To ensure amplifier stability, two factors, 𝑘 and ∆, are used.
The factors are calculated from the S-parameters of the amplifier but can easily be
simulated in most simulation tools. For a stable design, 𝑘 should be bigger than 1 and ∆
smaller than 1, Equations (2.4) and (2.5).
|∆| = |𝑆11𝑆22 − 𝑆12𝑆21| < 1 (2.4)
𝑘 = 1−|𝑆11|2−|𝑆22|2+ |∆|2
2|𝑆12||𝑆21|> 1 (2.5)
2.2 Matching Networks When designing amplifiers at high frequencies, input and output impedance matching is
required. At a frequency of 100 MHz, the wavelength (λ) of the signal becomes 3 m. This
probably is longer than the whole system itself. Matching networks are needed to
transform the source and load impedances into the complex conjugated values of the
input and output impedance of the transistor. This according to the maximum power
transfer theorem, Equation (2.6). Where the load impedance that is required for
developing a specified power is calculated.
𝑍𝐿 =𝑉𝐷𝑆
2
𝑃𝑜𝑢𝑡=
502
1000= 2.5 Ω (2.6)
In chapter 3 further investigation was performed by using load-pull simulation to
determine the optimal load impedances. The principle for matching networks are
displayed in Figure 2.4.
Page | 12
Figure 2.4 Principle for matching network
When impedance matching is used, several benefits can be achieved; the loss of power
will be minimized which means that the system will be able to deliver maximum power,
reduction of amplitude and phase errors, and improvements in the signal-to-noise ratio.
Another thing that is improved with matching networks are the reflections in the
system, which will be almost zero if the matching is done correctly. Signal reflections in
the system can potentially harm different components not designed to conduct current
in the reversed direction. The reflection coefficients is defined as Equation (2.7).
Γ =𝑍1−𝑍2
𝑍1+𝑍2 (2.7)
Where Z1 is the impedance towards the load and where Z2 is the impedance towards the
active device. Matching networks can be designed either with lumped components or
with distributed elements, such as microstrip lines and stubs. There are three main ways
to design a matching network; analytical calculations, graphical using Smith Chart, and
by simulations. Although simulations are the easiest way, performing the analytical
calculations will provide a better understanding. The different ways of designing a
matching network is described in section 2.2.1 and 2.2.2. [2, 3]
2.2.1 Matching Using Lumped Components
The simplest way of designing a matching network is by using lumped components or L-
networks. These networks use two reactive components, capacitors and inductors, to
match the impedances on both sides of the network. Depending on the normalized load
impedance, there are two types of configurations possible for a L-type network. If the
normalized load impedance is smaller than 1+jx the configuration shown in Figure 2.5a
should be used, and if it is larger, the configuration in Figure 2.5b should be used
instead. To calculate the normalized load impedance, Equation (2.8) is used, were Z0 is
the characteristic impedance.
ZS
ZL
Input matching
Output matching
Active Device
Zin Zou
t ~
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(a) (b)
Figure 2.5 Different configurations depending on the normalized load impedance; (a) for small impedance and (b) for high impedance
𝑧𝐿 = 𝑍𝐿
𝑍0 (2.8)
Solving the matching network can be done by calculation, Smith chart or simulations. As
described in chapter 4, ADS was used in this project. In section 2.2.3 the Smith chart
solution is described [2, 3].
2.2.2 Matching Using Distributed Elements Another way of designing a matching network is by using distributed elements such as
microstrip transmission lines and stubs. This design technique is used when the system
has a higher frequency, at which the lumped components are more difficult to be
accurately modelled. When designing a matching network with lumped components for
higher frequencies the parasitic capacitances and inductances have to be considered,
which makes the design more complicated. But in distributed networks the parasitic
capacitances and inductances are embedded in the transmission line model and used to
transform the impedance. Further benefits with using distributed types of networks, are
that they can be manufactured directly on the PCB and also be made to fit the system
ideally whereas lumped components come in predefined values.
A matching network designed with distributed elements could be utilised differently by
different designers. One way is to design it with a combination of lumped and
distributed elements, for example transmission lines connected in series and capacitors
in shunt configuration. An advantage with this design is the possibility to change the
capacitors and move them along the transmission line in order to tune the circuit.
However, this type of design is not perfectly match for the system since the capacitors
are only available in fixed values. Therefore, a design containing only transmission lines
and stubs is preferable especially when the frequency increases. A stub is a transmission
line connected in parallel; it can be either open or short-circuited.
jX
jB ZL jB ZL
jX
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Designing a matching network using distributed components is done in a similar way as
for a network with lumped components. It can be done both with analytical calculations
and using the Smith chart. Another possible solution is to first design an L-network and
then transforms the lumped components into transmission lines and stubs. The most
significant parameter when designing a transmission line or a stub is the length, which
correlates to the electrical length that is a fraction of the wavelength λ. Other parameters
of importance are the width and the material of the PCB that changes the dielectric
constant εr. [2]
Changing substrate to a substrate that has another dielectric constant can give certain
advantages in a design, especially when dimensions are a critical factor. If it is possible
to only change the dielectric constant while keeping other parameters constant they can
be compared on how it would affect matching. When using distributed elements to
design a circuit it is common to consider the ratio between the width of the transmission
line (𝑤) and the height of the substrate (ℎ). Different dielectric constant of a substrate
gives different characteristic impedances, while the ratio (𝑤 ℎ)⁄ is kept constant. A
determined width to height ratio and a higher dielectric constant (𝜀𝑟) will give lower
characteristic impedance. This implies that if certain impedance is of essence, a higher
dielectric constant will give that at a smaller width. Equations (2.9) – (2.11) shows this
relation valid for a width to height ratio greater than 2.
𝑤
ℎ=
2
𝜋𝐵 − 1 − 𝑙𝑛(2𝐵 − 1) +
𝜀𝑅−1
2𝜀𝑅[ln(𝐵 − 1) + 0.39 −
0.61
𝜀𝑅] , 𝑤 ℎ⁄ > 2 (2.9)
where
𝐵 =𝑍𝑓𝜋
2𝑍0√𝜀𝑅 (2.10)
and
𝑍𝑓 = √𝜇0𝜀0
⁄ (2.11)
However, changing εr does not only provide advantages. A greater dielectric constant
implies that a transmission line will have a greater phase shift, which gives greater
losses. [2, 3]
2.2.3 Smith Chart The Smith chart is a tool for designing circuits with high frequency. There are several
parameters that can be found using a Smith chart, and therefore this part of the report
will explain how the Smith chart can be used to simplify the design of a matching
network. Instead of tedious analytical calculations the Smith chart provides the designer
with a graphical tool on how to design a matching network by knowing the impedances
that is supposed to be matched. In Figure 2.6 the Smith chart is displayed with the
impedance change by adding different components.
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Series L
Series C Shunt C
Shunt L
Figure 2.6 Smith chart with component directions
The easiest way to both explain and understand how the Smith chart works is by an
example; if the source impedance ZS = 50 Ω is supposed to be matched with a transistor
with a load impedance ZL = 2.94+j9.64 Ω in order for it to work optimally. The first step
is to normalize these impedances with the characteristic impedance Z0 = 50 Ω in this
case, this implies getting ZS,normalized = 1 and ZL,normalized = 0.059-j0.193 . Next, in the Smith
chart solution is to find ZL,normalized and Zs,normalized in the chart, this can be seen in Figure
2.7.
Figure 2.7 Source and load impedances in both schematic and smith chart
As shown in Figure 2.7 there is quite a distance between the load and the source in the
chart. Therefore, components have to be added in the matching network between the
source and load in order for the network to work properly. The solution is shown in the
following steps. Plotted in the Smith chart in Figure 2.8, is the line showing how the
impedance has travelled in the chart, corresponding to that is the capacitor and its value
added between source and load, see Figure 2.8.
zS
zL
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Figure 2.8 Source and load with added shunt capacitor
By adding a series inductor after the shunt capacitor completes the matching network
between the transistor and the source termination. Displayed in Figure 2.9, the inductor
has been added in the schematic and the smith chart. The matching network has
established a connection between source and load.
Figure 2.9 Shunt capacitor and series inductor added in the matching network
Although this example has shown a simple way of designing a matching network, which
will not work at RF-frequencies, it shows the principle of how to design a network and
what happens in the Smith chart when different components are added.
2.3 BALUN Theory
The input and output signal of a push-pull amplifier is unbalanced, but the transistors
are fed with a balanced signal. The balanced signal is often achieved by the use of a
BALUN (BALanced to UNbalanced). The BALUN is a three-port device with one
unbalanced port, transformed into a pair of balanced ports. A balanced signal consists of
two signals equal in frequency but opposite in polarity; the signals are 1800 out of phase.
The basic functionality of a BALUN can be seen in Figure 2.9.
zS
zL
zS
zL
Page | 17
Figure 2.9 Simple model of a BALUNs functionality
There are several different ways of constructing a BALUN, some of them will be
explained in this section. At lower frequencies, up to MHz-level, a simple transformer
made out of magnetically coupled coils can be used, as shown in Figure 2.10a. Moreover,
the coil is often winded around a ferrite material to increase the magnetic coupling [3].
At very high frequency (VHF) it is common to construct the BALUN from a coaxial cable
or twisted wires and ferrite material. The coaxial BALUN has it origin in antenna
applications, where balanced dipole antenna needs to be fed with unbalanced coaxial
cable [6]. For microwave frequencies, a 180° hybrid coupler or various types of coupled
line circuits can be used, for example a Marchand BALUN displayed in Figure 2.10b [3].
A difference between a conventional BALUN and a 180° hybrid coupler, is that the
hybrid coupler is terminated in 50 Ω and the BALUN can achieve an impedance
transformation from the input to the output. The impedance transformation is an
advantage when designing PA.
(a) (b) Figure 2.10 BALUN circuit; (a) Transformer BALUN, (b) Marchand BALUN
A coaxial BALUN makes use of a piece of 50 Ω semi-rigid cable, positioned above a
ground plane. The unbalanced input is connected to the inner conductor of the cable.
While the outer sheath at the same end is connected to ground to form a short-circuited
stub down to ground. Looking from the balanced end, places the required open-circuit to
ground at the resonance frequency of the stub. Transmission line equations can be used
to determine the characteristic impedance of the stub and the electrical length to
determine how it affects the performance of the BALUN at the desired frequency. The
easiest way of evaluating the performance is to use a simulation program. As stated in
[6] there is no problem to achieve a good result from a simulation program, however
this is not how it usually works in practice. Problems during manufacturing, when it
BALUN
Unbalanced
Balanced
Page | 18
comes to precision in cutting, stripping and soldering of the coaxial cable needs to be
taken into account. [6]
The coupled line circuits used at microwave frequency are constructed out of quarter
wavelength segments of transmission line. At a centre frequency of 100 MHz is 50 cm in
a 50 Ω transmission line and the reason why coupled line BALUNs are uncommon at
VHF range. However, it has been proven by [7] that it is possible to construct a planar
BALUN at VHF, by the use of double tuned transformers. D. Fitz Patrick [8] evaluates the
same planar structure further and presents an approach on how to proceed with the
design. Both [7] and [8] comes to the conclusion that the use of a mathematical approach
gets complex and therefore it is easier to use a simulation program and an iterative
approach.
Page | 19
Chapter 3
Transistor Characteristics Evaluation This chapter presents the transistor characteristics for both the transistors used in the
thesis. The simulations have mainly been performed with Advanced Design Systems
(ADS) from Keysight Technologies. The simulations performed on transistor level are
DC-characteristic, stability analysis and a load-pull simulations. Load-pull simulations
are used to determine load impedance (ZL) values that enable certain power to be
delivered to the load. Moreover, the necessary input power level are specified.
In this project, both transistors that are used are from NXP Semiconductors. For the
power amplifier (PA) design, the BLF188XR is used and for the preamplifier design, the
BLF571 is used. Simulation models for both transistors have been downloaded from
NXP Semiconductors home page and imported to ADS [13, 14]. The simulation models
contain both schematic symbols and S-parameter model. The models provided by NXP
Semiconductor are not compatible with the latest version of ADS and therefore an older
version of ADS has been used.
3.1 NXP BLF188XR
The transistor BLF188XR was chosen for the PA design. It is a power LDMOS transistor
produced for broadcast and industrial applications in the frequency range of high
frequency (HF) to 600 MHz range. What makes it suitable for this application is its
abilities to deliver a high gain and efficiency in the specified frequency range. [9]
3.1.1 DC Simulation To be able to control the DC bias of the transistor, DC simulation is performed. The DC
simulation setup is displayed in Figure 3.1, where the NXP model of the transistor is
used.
Page | 20
Figure 3.1 DC simulation setup on BLF188XR simulation model
The drain-source voltage (VDS) is kept constant at 50 V and the gate voltage (VGS) is
swept from 1 to 2 V. A current probe is used for measurement of drain current (IDS). The
result of the simulation can be seen in Figure 3.2, where IDS is plotted as a function of
VGS.
Figure 3.2 IDS as a function of VGS for BLF188XR
A suitable DC bias for the gate can be selected from the transfer characteristic with
respect to the class of operation. For this application, the transistor is supposed to
operate in Class B or AB; therefore the gate bias have to be as close as possible to the
threshold voltage where the transistor starts to open. At a gate voltage of 1.5 V the
transistor opens and current flows through the transistor. In the data sheet for NXP
BLF188XR [9], the threshold voltage is specified to range from 1.25 V to 2.25 V with a
typical value of 1.9 V. For the physical transistor the gate bias has to be tuned depending
on the characteristic of the specific transistor, in the simulations in ADS a gate bias
between 1.5 and 1.9 V has been used.
VGS (V)
I DS (
A)
Page | 21
3.1.2 Stability Analysis Two important parameters when investigating the stability of a transistor, is the k-factor
and the Δ-factor. These factors can be found by simulation in ADS. To find the k-factor, a
predefined equation in ADS is used called StabFact and to find the Δ-factor, a
measurement equation has to be added to the simulation setup, see Appendix A.2. The
result of the simulation is displayed in figure 3.3.
Figure 3.3 Stability simulation in ADS; simulation result: k-factor and Δ-factor
Both the conditions k > 1 and Δ < 1 is fulfilled at the design frequency 100 MHz and the
transistor will be unconditionally stable in this area. Further, Figure 3.3 shows that the
transistor will be conditionally stable for frequencies lower than 25 MHz, as k < 1. The
amplifier can be designed assuming that it is unconditionally stable at the design
frequency. However, it can be wise to check the stability at 25 MHz later in the design.
The conditions for stability may change during the design, due to changed operating
conditions for the transistor.
3.1.3 Load-Pull Analysis A load-pull simulation is performed on the transistor model; within the load-pull
simulation, the impedance presented to the transistor’s output, is varied in order to
select the optimal impedance. The load-pull can result in different impedance values,
depending on which parameter of the amplifier is prioritised in the design, e.g., gain,
efficiency, etc.. The same type of simulation can be performed on the input of the
amplifier, a so-called source-pull. The load-pull used sweeps the input power to achieve
the desired output power of the amplifier of 1 kW (60 dBm).
The impedance for the transistor operated in push-pull configuration is specified to ZL =
2.74+j*0.57 Ω, in accordance to the BLF188XR data sheet [9]. The impedance for a push-
push (single ended) operated transistor is approximated to a fourth of the push-pull
impedance. Therefore, the optimal value for a single ended amplifier would be close to
Frequency (GHz)
Δ-f
acto
r
K-f
acto
r
K
Δ
Page | 22
ZL = 0.7+j*0.14 Ω. This impedance is used in simulations. The setup for the simulation is
shown in Figure 3.4.
Figure 3.4 Load-pull setup in ADS
The input power is swept between 31 and 40 dBm, these values are estimated from the
power delivered by the preamplifier (5 W = 37 dBm). The result of the simulation is
displayed in Table 2 and shows two different impedances depending on if it is maximum
PAE or maximum gain stated as the most important design parameter. Furthermore, the
needed gain can be achieved for the output of a sufficient power at 60 dBm or more.
Table 2 Load-pull simulation, with maximum PAE and gain results
At load that gives max PAE At load that gives max gain
Bias current 27.905 A 30.307 A
ZLoad 0.967+j*0.772 Ω 0.860+j*0.621 Ω
Rho (𝜌) 0.5 / 44.997 Ωm 0.448 / 52.122 Ωm
PAE 83.240 % 76.953 %
ZIn 1.234-j*3.193 Ω 1.242-j*3.253 Ω
Power delivered 60.476 dBm 60.493 dBm
Gain compression 2.257 dB 1.605 dB
Gain 21.026 dB 21.143 dB
The result in Table 2 states that, the transistor can achieve a gain at approximately 21
dB and a PAE at 83 % with an impedance of ZL = 0.967+j*0.772, if the goal is to achieve
the best PAE. If the goal is to have a better gain, the design should aim to have a load
impedance of ZL = 0.860+j*0.621 according to the results of the load-pull simulation.
3.2 NXP BLF571
The transistor chosen for the preamplifier is the BLF571 from NXP [10]. It is as well as
the BLF188XR an LDMOS developed for industrial and other high-end applications. This
transistor has a lot of similarities with its big brother, the BLF188XR, although for a
Page | 23
lower power span. Another difference is that every capsule contains only one transistor,
which implies that the amplifier can only be designed in single-ended configuration. The
above-mentioned qualities made it suitable as the transistor of the preamplifier. The
following sections of the report will describe the transistor characteristics as
investigated to design the preamplifier.
3.2.1 DC Simulation A DC simulation determines the VGS for the preamplifier. The simulation setup using the
BLF571 model for the transistor is displayed in Figure 3.5.
The drain voltage (VDS) is kept constant at 50 V and the gate voltage (VGS) is swept from
1 to 10 V. A current probe is used for measurement of drain current (IDS). The result of
the simulation can be seen in Figure 3.6, where IDS is plotted as a function of VGS. An
optimal gate bias could be derive from the simulation result.
Figure 3.5 DC simulation setup with transistor model
VGS (V)
I DS (
A)
Page | 24
From Figure 3.6, it can be seen that the transistor opens at a VGS of about 2 V and that it
goes into the saturated region at about VGS = 5 V. The VGS can be chosen between these
values depending on class of operation. For the application in this thesis, the aim was to
operate the preamplifier in Class A, generating a pure sinusoidal wave with low noise
and harmonic distortion to the PA. To have the transistor operating in Class A, the gate
bias should push the input curve above the transistor threshold voltage. However, at the
same time keeping the peak of the curve below the saturation voltage. In this thesis, the
gate voltage will be around 3 V, though small changes could be made to fine-tune the
performance of the amplifier.
3.2.2 Stability Analysis To analyse the stability conditions of the BLF571 transistor, a stability simulation was
performed. The stability region of a transistor is specified by two parameters, the k-
factor and the Δ-factor. These factors can be found through a built in stability simulation
in ADS, called Stabfact. The result of this simulation for the preamplifier transistor can
be seen in Figure 3.7. The criteria of stability, k > 1 and Δ < 1, are satisfied throughout
the frequency range and the transistor is unconditionally stable at 100 MHz.
3.2.3 Load-pull Analysis
In the data sheet for the BLF571 transistor [10], the optimal source and load impedance
are given as 𝑍𝑠 = 9.7 + 𝑗31.5 Ω and 𝑍𝐿 = 31.7 + 𝑗29.3 Ω. However, in the data sheet the
design frequency is at 225 MHz, which is well above the 100 MHz, the operation
frequency of the amplifier in this thesis. To know the impedances that are optimal for
the transistor at 100 MHz, a load-pull simulation was used. The load-pull analysis was
setup to attain an output power between 35-40 dBm (3.16-10 W) at the input power of
10 dBm (10 mW) that was desired and stated in the specification. Presented in section
Figure 3.6 Drain current as a function of gate voltage for BLF571
Figure 3.7 Stability factors for BLF571
Frequency (GHz)
Δ-f
acto
r
K-f
acto
r K
Δ
Page | 25
3.1, the BLF188XR transistor had different load- and source impedances whether it
would be configured in push-pull or push-push configuration. However, the capsule of
the BLF571 only contains one transistor, which implies that the transistor can only be
designed as single-ended. The simulation setup is shown in Figure 3.8.
Figure 3.8 Load-pull simulation setup for the preamplifier transistor
Apart from what was mentioned above, the transistor was simulated with a gate bias of
3 V and drain bias of 50 V. The simulation was set to start at a load impedance of the one
specified in the data sheet for the transistor, which is the only value known that should
work although at the wrong frequency. The results of the load-pull simulation are
presented in Table 3, for both a desired high gain and efficiency.
At load that gives max PAE At load that gives max gain
Bias current 0.748 A 0.852 A
ZLoad 61.448 + j*12.079 Ω 43.769 + j*11.989 Ω
Rho (𝜌) 0.5 / 30.335 Ωm 0.5 / 44.997 Ωm
PAE 75.103 % 65.882 %
ZIn 1.919-j*47.075 Ω 0.620-j*52.870 Ω
Power delivered 44.483 dBm 44.484 dBm
Gain compression 2.911 dB 1.352 dB
Gain 34.833 dB 36.084 dB
From the results of the simulation presented in Table 3, the load impedance
𝑍𝐿 = 61.448 + j ∗ 12.079 Ω and input impedance 𝑍𝑆 = 1.919 − j ∗ 47.075 Ω should be
used if the best PAE is desired. If a good gain is desired the values presented in the right
column should be used instead.
Table 3 Load-pull results for BLF571
Page | 26
Page | 27
Chapter 4
Single-Ended Design In order to achieve a simple design, which was desired by GE, the first alternative
studied was a single-ended design. The simplicity is that it only consists of the transistor
in the middle with input and output matching networks on the corresponding side of the
transistor. The following chapter will go through the design steps taken in order to
achieve the single-ended design.
To be able to analyse whether it was possible at all to make a single-ended design
satisfying the output power, gain and efficiency conditions the transistor was simulated
with virtual matching networks. The virtual networks consist of terminations on both
sides of the transistors with the impedances from the load-pull simulations performed
in section 3.1.3. The impedances for input 𝑍𝑆 = 1.24 − 𝑗3.253 Ω and for output
𝑍𝐿 = 0.86 − 0.621 Ω. These simulations enabled the transistor to see the ideal
impedances on both sides and to run at optimal conditions. The simulation setup is
shown in Figure 4.1.
Figure 4.1 Simulation setup for transistor in single-ended mode
To determine the performance of the transistor running in single-ended mode, a
harmonic balance simulation was performed for the circuit in Figure 4.1. This type of
simulation sweeps the input power and calculate a defined number of harmonics of the
fundamental frequency at the output. How a harmonic balance simulation is configured
and which calculations are used to obtain the results, is described more thoroughly in
Appendix A.1. The result of the simulation performed on the circuit in Figure 4.1 is
shown in Figure 4.2. It can be seen that the transistor is able to produce over 1 kW at an
input power of 35 dBm with a gain of about 25 dB, which satisfied the demands, and
further work could be carried out on the single-ended design. However, the efficiency
was quite poor and a possible explanation could be that it is partially too loose of power
in form of harmonic signals, as shown in Figure 3.6a.
Page | 28
4.1 Lower Dielectric Constant (𝜀𝑟 = 3) Design
It was desired to design a solution with a low dielectric constant, the matching network
design started out with a substrate with a dielectric constant of 𝜀𝑟 = 3. A lower
dielectric constant has several benefits, one of them is the lower losses in the system as
explained in chapter 2. Further, theory on how the dielectric constant affects the system
can be found in section 2.2.2. However, at a frequency of 100 MHz a matching network
between the transistor and 50 Ω becomes both long and wide, on both sides of the
transistor. Further, values of components cannot exceed certain values for this kind of
application. Large capacitors, for example, have lower impedance resulting in a higher
current. Higher current means higher temperatures, which could destroy the capacitor.
A design goal was to keep capacitor values below 33 pF, which corresponds to 48 Ω at
100 MHz. Otherwise the capacitors would generate to much heat, which will break them.
To perform the design of the matching networks, ADS built in tools Smith Chart and
LineCalc Utility was used. These tools enable the designer to move freely in the Smith
chart and then convert the solution to transmission lines, which later can be
transformed into microstrip lines. A more thorough explanation of how the matching
network design is performed is explained in section 4.2. A matching network was
created for both the input and output side of the transistor and both sides showed
satisfying results in both impedance and transmission. The amplifier design can be
found in Figure 4.3.
Figure 4.3 Single-ended amplifier design
(a) (b)
Figure 4.2 Harmonic balance simulation results for the transistor with virtual networks
Frequency (MHz)
Po
ut (
W)
Pout (W)
Eff
icie
ncy
(%
)
Gai
n (
dB
)
Gain
Eff.
Input 50 Ω
Output 50 Ω
Transistor
Page | 29
When both the input and the output side of the matching network were fitted with the
transistor and DC-bias to create the entire amplifier design, the result was not satisfying.
The amplifier delivered an output power of about 200 W, which was a lot below the
desired 1 kW for the same input power, thereby the gain of the amplifier was well below
specifications. A graph showing the output performance of the amplifier is shown in
Figure 4.4.
Figure 4.4 Output performance of 𝜀𝑅 = 3 design
The poor performance of the amplifier is likely to have many different explanations,
however, the most probable is that the input and output match is not satisfying the
needs of the transistor which make losses appear in the system and the gain and output
power decreases. Since the performance of the amplifier was very poor, the design was
not further investigated to figure out the root to the poor performance. Since the
amplifier was underperforming, an iterative process to design a matching network
fulfilling the requirements of both power delivered to the load as well as the
measurements. The process found many solutions although none of them fulfilled the
power requirements, which was probably due to the impedance seen by the transistor,
was not low enough.
Figure 4.5 Output performance for the wide single-ended design
To prove that the problem with the design was too high impedance, due to width
limitations, a single-ended design was made without taking the measurements into
Eff
icie
ncy
(%
)
Gai
n (
dB
)
Pout (W)
Gain
Eff.
Pout (W)
Eff
icie
ncy
(%
)
Gai
n (
dB
)
Gain
Eff.
Page | 30
account. The design became very large but proved the point, it was possible to achieve
the output power if the design did not take the measurements into account.
Furthermore, this design had a lot of losses making the gain drop at higher power and
the design also needed slightly more power to produce 1 kW output power. Data from
simulations of this design can be found in Figure 4.5.
4.2 Higher Dielectric Constant (𝜀𝑟 = 9) Design
Presented in the section 4.1, the single-ended design with a low dielectric constant
would not satisfy the specification regarding output power and efficiency and at the
same time keep the design within the preferable size. Therefore the dielectric constant
of the substrate was increased to εr = 9, to enable matching of low impedance at a
smaller size. The first step in the single-ended design was to match the impedance of the
transistor with the output and input impedance of 50 Ω. However to minimize the
design, the input and output networks were matched to 40 Ω, since it is better to have an
almost perfect match at the transistor than at the terminations and that 50 Ω lines
become too thin for high power. The transistor impedances were taken from the load-
pull simulations presented in section 3.1.3. The simulations showed that the transistor
would run optimally with the input side impedance of 𝑍𝑆 = 1.24 − 𝑗3.253 Ω and a load
impedance of 𝑍𝐿 = 0.86 − 0.621 Ω. The built-in Smith chart tool in ADS was used for
matching. In this tool, the impedances supposed to be matched, are fixed and the user
can add different components in order to build the input and the output matching
networks. Since the difference in impedances to be matched is large and the space of the
board is limited according to the specification, the matching becomes a complex process
considering that to the impedance gets lower when the widths of the transmission lines
are increased. Another issue the designer has to consider when matching low
impedance with high impedance is that the matching cannot happen in one step. A one-
step match would create reflections and great losses in the system. Instead, the
matching has to be done using several sections, which is why there are a lot of small
steps close to the transistor in the Smith chart as shown in Figure 4.6.
Page | 31
In Figure 4.6, the small dots represent different components added to the matching
network. The distance between each dot represents the electrical length of the
transmission line. From the Figure 4.6 it can be seen that two components were created
longer than the other, in order to enable bending while keeping their length. Something
that is not possible with a shorter transmission line. However, one has to remember that
there are infinite number of ways the matching could be executed and this is just one of
them.
The next step in the design is to go from the Smith chart to components. ADS has a built-
in tool that generates a schematic from the Smith chart design. The tool only converts
from Smith chart to transmission lines, to achieve microstrip lines the transmission lines
have to be recalculated. To retrieve as realistic results as possible, ADS simulates
microstrip lines with a model containing substrate parameters. The conversion is
performed with support from a microstrip line calculator in ADS, converting electrical
length and impedance to physical length and width of the microstrip line. S-parameter
simulations were performed to control that the characteristics of the matching were
intact during the conversion. The microstrip line schematic is displayed in Figure 4.7a.
To achieve a layout component, the circuit was transferred from schematic to layout.
Instead of displayed as components the actual design are shown in layout. In order to
make it fit in the dimensions given, a tool in ADS enables the designer to bend the lines
without changing their length. Ports have also been fitted to the design to enable that
other components, such as capacitors and ground can be connected to the layout
component. With these design steps taken, the design looked like presented in Figure
4.7b.
Figure 4.6 Smith chart for input matching
zL
zS
Page | 32
(a)
(b)
Figure 4.7 The input matching network;
(a) Schematic (b) layout
Once the layout was finished, an electromagnetic (EM) simulation was performed, using
ADS Momentum tool, to see how the amplifier behaves with matching networks
modelled as layout components. The amplifier model can be simulated in the schematic
view in ADS. However, before that could be done the same design steps had to be taken
for the output side of the transistor. These steps have been excluded from the report
since the principle is identical to the input of the transistor.
The finished amplifier circuit design is shown in Figure 4.8, amplifier with the transistor
in the middle and matching networks on both sides of it. The amplifier is biased with
VGS at 1.9 V and VDS at 50 V, on the gate side respectively the drain side. In Figure 4.8,
the matching networks have been completed with capacitors.
Input 50 Ω Transistor
Page | 33
Figure 4.8 Single-ended amplifier design
Similarly to the other amplifier designs presented previously in this report, this design
was simulated with a harmonic balance tool to analyse the performance in form of gain,
efficiency and also the generated harmonics at the output of the amplifier. The results of
the harmonic balance simulation are displayed in Figure 4.9.
(a) (b)
Figure 4.9 Harmonic balance simulation result
From figure 4.9a, it can be found that the single-ended design with a εr = 9 can deliver
the required output power with a reasonable input power. The graph also shows that
the harmonics have been cancelled out in this design, which is a part of the explanation
of the good efficiency. Figure 4.9b shows that the amplifier has a stable gain over the
desired output and at the same time a satisfying efficiency.
Before the single-ended amplifier design was manufactured, the final changes were
made. DC-paths for bias networks were added on both the input and the output side of
the transistor. The first bend on the output side of the transistor was stretched to not get
to close to the edge of the card. Screw holes were also added to be able to attach the PCB
to the heat sink (See section 7.1.2) and via holes were added to ensure a good
connection to ground everywhere on the PCB. The final design can be seen in Figure
4.10.
Input 50 Ω
Transistor
Output 50 Ω
Po
ut (
W)
Gai
n (
dB
)
Frequency (MHz)
Eff.
Pout (W)
Gain
Eff
icie
ncy
(%
)
Page | 34
Figure 4.10 Final single-ended design for manufacturing
Input 50 Ω
Output 50 Ω
Transistor
Page | 35
Chapter 5
Push-Pull Design The second alternative for the PA, was a push-pull design with planar BALUNs. This chapter will go through the design steps for the push-pull amplifier.
5.1 Planar BALUN design
As stated in chapter 2, a traditional way of designing a push-pull amplifier is to use
BALUNs made of a coaxial cable wounded around a ferrite core. In this application, it
was desired to keep a simple design and therefore the BALUN was designed as a planar
structure.
The BALUN will be used as a part of the impedance transformation from 50 Ω to the
impedance that the transistor requires to produce the maximum power. The goal for the
BALUN is a 4:1 impedance transformation, on both the input and output side. The
remaining part of the matching from 12.5 Ω to the transistor will be matched with
microstrip lines and lumped components, similar to the single-ended design in chapter
4.
The design starts from an ideal model for a transformer, so rough parameters can be
achieved as a starting point for the planar BALUN. First, the reactive part of the
transistor impedance is transformed to an equivalent capacitance, see Equation (5.1).
𝑋 = 0.57 𝛺 ⇒ 𝐶 = 1
2𝜋𝑓𝑋𝐶 =
1
2𝜋∗100∗106∗0.57 ≈ 2.79 𝑛𝐹 (5.1)
𝐿𝑆 = (1
𝐶) ∗ (
1
2𝜋𝑓)
2
≈ 0.91 𝑛𝐻 (5.2)
The capacitance resonates with an inductance of 0.91 nH at the fundamental frequency,
this in accordance with Equation (5.2). The inductance with a source impedance of 50 Ω
and a coupling factor set to K = 0.8, makes it possible to calculate the second inductance
for the ideal transformer. As mentioned before, an impedance ratio of 4:1 is the goal, so
that ZL = 12.5 Ω. Equations (5.3) – (5.5) cover the calculations of the remaining values
for the ideal transformer.
𝐿𝑃 = 𝐿𝑆𝐾2 𝑅𝑆
𝑅𝐿= 0.91 ∗ 0.82 ∗
50
12.5≈ 2.33 𝑛𝐻 (5.3)
𝑀 = 𝐾 ∗ √𝐿𝑆𝐿𝑃 = 0.8 ∗ √0.91 ∗ 2.33 ≈ 1.16 𝑛𝐻 (5.4)
Page | 36
𝐶𝑃 = (1
𝐿𝑃) ∗ (
1
2𝜋𝑓)
2
= (1
2.33∗10−9) ∗ (
1
2𝜋𝑓)
2
≈ 1.1 𝑛𝐹 (5.5)
The calculated values in Equations (5.4)-(5.5) are used as starting values for simulations
of an ideal transformer model in ADS. The model is displayed in Figure 5.1, where
additional to the transformer, a shunt capacitor has been added to resonate with the
inductance on the input of the model.
Figure 5.1. Ideal transformer with resonating capacitor
The component values have to be tuned in order to operate at the centre frequency.
Figure 5.2 displays the result after the values have been tuned. As can be seen, the loss at
100 MHz are almost zero.
Figure 5.2 Result of tuned transformer with shunt capacitor
The next step is to convert the ideal transformer to a simple model of a planar BALUN.
This simplified planar BALUN consists of two straight microstrip lines placed on the
opposite side of a substrate. The length and width of the microstrip line are calculated
by using theory based on magnetic and electric coupling between microstrip lines and
by using the values retrieved from the ideal transformer as a starting point. For
simplicity in the calculations, the opposite lines will be seen as identical lines with the
same width and length.
Frequency (MHz)
S-p
aram
eter
s (d
B)
Page | 37
The characteristic impedance for two lines separated by a substrate can be calculated by
the use of Equation (5.6), where w and h is the width and height of the substrate and εr
is the dielectric constant. [11] If the width (w) is set to 10 mm, the characteristic
impedance 𝑍0 with Rogers RO3003 is calculated to be 𝑍𝐶 = 14.84 Ω, Equation (5.7). The
per unit length inductance can be calculated from the characteristic impedance and is
shown in Equation (5.9). Where v is the velocity of propagation in the medium
calculated by using Equation (5.8), v0 is the velocity of light in vacuum and εr is the
effective dielectric constant for Rogers RO3003.
𝑍𝐶 = 377
√ε𝑟(𝑤
ℎ+0.441+
ε𝑟+1
2𝜋ε𝑟(𝑙𝑛(
𝑤
ℎ+0.94)+1.451)+0.082
ε𝑟−1
(ε𝑟)2), w/h >1 (5.6)
𝑍𝐶 = 14.84 Ω (5.7)
𝑣 = 𝑣0
√𝜀𝑟′
= 3 ∗ 108
√4 𝑚 𝑠⁄ (5.8)
𝑙𝑖𝑛𝑑 = 𝑍𝐶
𝑣 =
14.84
1.5∗108 = 9.89 ∗ 10−8 𝐻/𝑚 (5.9)
The estimated length of the BALUN can be calculated by using the mutual inductance
from the ideal transformer simulation and the per unit length inductance in Equation
(5.9). The estimated BALUN length is given in Equation (5.10).
𝐿𝑀 = 𝑙 ∗ 𝑙𝑖𝑛𝑑
⇒ 𝑙 = 𝐿𝑀
𝑙𝑖𝑛𝑑=
4.7
99≈ 47.5 𝑚𝑚 (5.10)
The calculated length LM, simulated capacitances and predefined parameters can be
used in the simplified model of the BALUN shown in Figure 5.3a. NI AWR is used for this
simulation. Tuning of the variables, width, height and capacitance, is needed to achieve
the desired result, which is displayed in Figure 5.3b. The variables have been tuned to
the centre frequency but the transmission is not sufficient. Because of the result some
further investigation needs to be conducted with simulation of a planar BALUN in a 3D
simulation program.
(a) (b) Figure 5.3. Simple model of a planar BALUN; (a) Schematic in NI AWR, (b) Simulation result
W1
W2
1
2
3
4
SBCPLID=TL1W1=10 mmW2=5 mmL=114 mmOffs=0 mmAcc=1TSwitch=T2=-T
SSUBTEr1=1Er2=3Er3=1Tand1=0Tand2=0.001Tand3=0H1=5 mmH2=0.75 mmH3=5 mmT=0.035 mmRho=1Name=SSUBT1
CAPID=C2C=0.0001 uF
CAPID=C1C=0.000186 uF
PORTP=1Z=50 Ohm
PORTP=2Z=6.25 Ohm
PORTP=3Z=6.25 Ohm
1 101 201 301 400
Frequency (MHz)
Simulation of simple planar BALUN
-50
-40
-30
-20
-10
0
100.1 MHz-5.541 dB
DB(|S(2,1)|)Schematic 1
DB(|S(3,1)|)Schematic 1
Frequency (MHz)
S-p
aram
eter
s (d
B)
Page | 38
A planar BALUN with a two turn secondary is designed in CST Studio. The BALUN is
shown in Figure 5.4. A shunt capacitor is added on the output of the primary to resonate
with the inductance.
Figure 5.4 Planar BALUN layout in CST Studio; green: two turn secondary, yellow C shaped primary
Once again tuning was needed to achieve a desired result, the length of the BALUN,
width of conductors and the matching capacitor were varied. The result of the
optimisation process is shown in Figure 5.5. The transfer function displayed in Figure
5.5a gives an attenuation of -1.792 dB from input to output at 100 MHz. Figure 5.5b
shows the phase shift performance of the BALUN between the two balanced outputs.
The difference in phase between the two balanced ports are 178o and close to the ideal
180o phase difference.
(a) (b)
Figure 5.5 Characteristics of BALUN; (a) transfer function, (b) phase shift between input and output signal
Unbalanced port
Balanced ports
Frequency (MHz)
S-p
aram
eter
(d
B)
S12
Frequency (MHz)
Ph
ase
(o)
S12
S13
Page | 39
5.2 Matching Network Push-Pull for Power Amplifier
For the single-ended amplifier the matching network is designed to obtain an
impedance transformation from 50 Ω down to the lower impedance at the transistor,
about 3 Ω. Since the BALUN does a fourth of the impedance transformation for the push-
pull design, a matching network is needed to perform the last bit of impedance
transformation. The S-parameter values for the BALUN designed in section 5.1 were
exported to ADS from CST to perform further simulations on the BALUN and design of
matching network. The same BALUN was used on both the output and input of the
amplifier.
The matching network was designed with the same approach as the single-ended design
in chapter 4. To the microstrip line network lumped components were added and tuned
to achieve a good matching from the transistor to the BALUN. It was important to keep
the matching network short, so that the total length of the amplifiers was kept within
the presented dimensions, see Table 1.
Figure 5.6 Output matching network BALUN design in ADS
The output matching network is shown in Figure 5.6 and consists of the two element
microstrip line network with added lumped components. In addition to the matching
network, the BALUN was connected as a two port differential S-parameter block. The
values of the components were starting values for the simulations on the entire
amplifier. The input matching network is designed in the same manner, but ending up
with different configuration on the lumped components to match with the input
impedance of the transistor.
Page | 40
5.3 Push-Pull Amplifier
The next step in the design of the push-pull amplifier is to combine the input and output
matching network, BALUNs and the transistor to form the amplifier. In addition to the
mentioned components, series capacitors were added on the output and input to block
DC and shunt capacitors were added for tuning of the BALUN to resonate at the right
frequency. DC-bias network is also added to the schematic, it generates a VGS at 1.9 V
and VDS at 50 V, in accordance to the DC simulations in section 3.1.1. However, the bias
was not applied at the correct place in comparison to the final layout design, as will be
seen later in this section. The reason is that the BALUN was simulated as a block in ADS
and with only three ports, not a fourth for connection of bias.
Harmonic balance simulation setup was used to simulate the amplifier performance.
During the harmonic balance simulation the input power where swept from 30 to 40
dBm. At first the simulation did not give a satisfying result. Therefore, the built-in
optimisation tool in ADS was used to decrease the iteration time and simplify the tuning.
All lumped components in the design were added to the optimisation with limitation
values, to ensure that the values were kept within reasonable levels. The optimisation
was set to run until a goal, of output power above 1200 W, was reached.
(a) (b) Figure 5.8 Simulated output power and gain for the push-pull amplifier
As displayed in Figure 5.8a, the output power reaches a value of 1221.7 W with an input
power of 35 dBm, which satisfy the goal of 1200 W. The amplifier gain is displayed in
Figure 5.8b is above 28 dB at 1000 W. The efficiency curve is left out from the simulation
result; the problem probably depends on the mixture of data from different simulation
programs. The simulation drains DC current from the bias during simulation, which
results in misleading efficiency calculation. The other simulation result is still displayed
because they are not dependent of the DC supply.
Po
ut (
W)
Gai
n (
dB
)
Frequency (MHz)
Pout (W)
Page | 41
Figure 5.9 PCB layout of the BALUN design
The final step in the design is to merge BALUNs and matching networks into a PCB
layout, this is done in ADS. The BALUN is exported over to ADS workspace from CST as a
layout component. In addition to the designed block components DC-feed lines, ground
planes, via holes and mounting holes are added. The final layout is shown in Figure 5.9,
where there is a cut-out in the middle of the design to fit the transistor.
Top Layer
Bottom Layer
Page | 42
Page | 43
Chapter 6
Preamplifier Design
When the simulations of the transistor BLF571, intended to be used as the main
component in the preamplifier design, were finished the actual design work could start.
Since every transistor package only consists of one transistor, it is only possible to
design the preamplifier in single-ended configuration. This chapter will detailed the
design steps taken to achieve a preamplifier. The amplifier will generate a 5 W output
signal from the 50 mW of input signal.
The transistor model is simulated with a termination matching, to verify the impedance
given by the load-pull. In the simulation, the transistor was fitted to terminations on
both the drain and gate side with the impedance retrieved from the load-pull simulation.
The transistor was also fitted with bias networks to create a basic amplifier outline.
Figure 6.1 shows the circuit for the test simulation.
Harmonic balance simulation was then performed, which sweeps the input power to
determine the output power delivered at the load with some simple equations, see
Appendix A.1. The result of the harmonic balance simulation is shown in Figure 6.2.
(a) (b)
Figure 6.2 Harmonic balance simulation result for test circuit
Figure 6.1 Preamplifier test circuit for load-pull simulated impedances values
Gai
n (
dB
)
Eff
icie
ncy
(%
)
Po
ut (
W)
Frequency (MHz)
Pout (W)
Gain
Eff.
Page | 44
They show that the transistor could reach the desired output power to be able to
provide the power and hence to drive the amplifier. Figure 6.2a shows the power at the
load at 100 MHz and also the generated harmonics, which are low compared to the
fundamental frequency. Figure 6.2b shows that the transistor will reach an efficiency of
60 - 70 % at the desired load power, when it is matched to the required impedances. The
graphs also present a very high gain and a rapid drop at 42 dBm of output power.
6.1 Preamplifier Design When the determined impedances, retrieved from the load-pull simulation, would
satisfy the performance requirements that was set on the preamplifier the designing
could start. In the same way as the single-ended PA designed in chapter 4 the built-in
Smith chart tool in ADS was used to facilitate the design. When the transformation
between the source and the load impedance was established in the Smith chart the
design was generated as a schematic of transmission lines. The transmission lines were
converted to microstrip lines to get a more realistic result. The design was transformed
from a schematic to layout, where the actual shape of the amplifier was designed. The
shape of the amplifier was determined; a layout component was generated and exported
back to the schematic. Lumped components were fitted to be able to perform a more
realistic simulation. Figure 6.3 presents the finished layout combined with the necessary
passive and active components and voltage sources.
Figure 6.3 Preamplifier layout
The preamplifier was simulated with a harmonic balance simulation as described in the
previous sections, to get an estimation of its performance. The result of the simulation
are shown in Figure 6.4.
Transistor
Input 50 Ω
Output 50 Ω
Page | 45
(a) (b)
Figure 6.4 Harmonic balance simulation result for preamplifier component
Figure 6.4 shows that the amplifier has a stable gain and a high efficiency; however, it
does not deliver the desired power to the load. This could probably be managed by
tuning of the amplifier design, further.
Page | 46
Page | 47
Chapter 7
Manufacturing & Measurements This chapter presents the practical work made during the thesis. Primarily, the
measurements of the two PA designs are detailed, however, the chapter also provides
information about the manufacturing process of PCBs and heat sinks.
7.1 PCB Manufacturing
Manufacturing of prototype boards was both done by hand and by ordering from a PCB
manufacturer. Due to a relative long delivery time of ordering PCB from an external
manufacturer, one prototype PCB of the single-ended design was fabricated in the PCB
laboratory at the University. The measurements could begin, before the ordered PCBs
had arrived. A difference between the prototype and ordered PCB cards were that the
prototype were copper plated and the ordered cards were gold plated. The substrates
used were; Rogers RO3010 for the single-ended design, and for the BALUN design
Rogers RO3003. [12]
When both the single-ended amplifier and the BALUN amplifier had been manufactured,
the transistor, N-type connectors at each end and the DC bias networks were soldered.
However, the matching capacitors were not, due to that the matching could differ from
simulations in reality. Instead both designs were initially measured and capacitors were
chosen and fitted according to the initial measurement. The finished amplifiers can be
seen in Appendix B.4 and B.5.
7.2 Heat Sink Design and Manufacturing
The amplifier will produce excess heat, especially the transistor. To be able to ensure
stable working conditions for the components used in the amplifier it is necessary to
deflect the heat. For a fast spreading of the heat, away from the transistor and PCB it is
necessary to use a base plate with high thermal conductivity, i.e, a solid metal plate.
Because the BALUN design has conductors on both sides of the PCB card, in comparison
to the single-ended design that only has conductors on the topside. Furthermore, the
designs have different dimensions and therefore two different base plates have been
designed and manufactured, see Appendix B. Moreover, the base plates were made in
aluminium, to achieve the thermal dissipation needed. The base plates could have been
made in copper, if even better thermal conductivity. Another benefit with the base plate
is the support to the otherwise relatively fragile PCB card.
Page | 48
The heat sinks have a trench in the middle, where the transistor will fit, thereby the
transistor is levelled with the PCB. There are also screw holes for attachment of the PCB
card, thereby the amplifier can be pushed down thigh against the base plate for
increased thermal and ground conductivity. And on the sides there are screw holes for
attachment of N-type connectors. As shown in Appendix B the base plate for the BALUN
design have two milled trenches, where the BALUN´s will be placed above. Since there
will be a reduction in deflection of heat underneath the BALUN, a thermally conductive
non-electrical conductive material was placed in the trench.
The base plates with mounted amplifier are then fitted on top of a heat sink that is
water-cooled. The heat sink is used for increased transportation of heat away from the
amplifier, the heat sink can be seen in Appendix B.3.
7.3 Measurements Setup
In this section of the report all the practical measurements and how the measurements
was preformed will be presented. The measurements have been divided between the
single-ended and the BALUN amplifier, however the measurement setup is the same for
all the PA designs.
To be able to determine the quiescent point of the transistor, measurements of its drain
quiescent current, 𝐼𝐷𝑞, was performed. To find the quiescent current an ampere meter
was fitted in series with the drain power supply, while the drain voltage was kept
constant at 50 V the gate voltage was adjusted until the right current was found. When
preforming the measurements, 𝐼𝐷𝑞 was held at 200 mA if nothing else is stated. To avoid
breaking the transistor the measurements were stopped when the gain had dropped by
-3-dB. Normally measurements are stopped at -1-dB, however, since the transistors
used were extra rugged they could be driven further into compression.
7.3.1 Power Measurement Setup A measurement setup was designed to measure the power into/out from the device
under test (DUT). The setup can be seen in Figure 7.1 and displays all components used
in the measurement to be able to put in enough power to deliver more than 1 kW in
output power without damaging any of the measurement equipment. The components
in the measurement setup can be divided into passive and active components. The first
group of components is static and cannot be changed since it consists of directional
couplers, loads, power splitters and attenuators. The other group that is active
components, consists of measurement equipment, such as signal generator and power
meter.
Page | 49
Figure 7.1 Schematic of power measurement setup
The first stage in the measurement setup was a signal generator, able of generating both
pulsed and continues wave (CW). A 100 W preamplifier is attached after the signal
generator, since the signal generator maximum output is +20 dBm. The preamplifier
gives a gain of 50 dBm from 50-500 MHz. Directional couplers are attached on both
sides of the DUT, used as measurement points for input and output power. The signal
goes in to a 50 Ω load, after the DUT and the second directional coupler.
The directional couplers have two coupled output ports, one coupled in each direction.
The first directional coupler (I), on the input to the DUT, is connected to measure the
signal that goes in to the amplifier. The other coupled connection is coupled in reverse is
connected to a 50 Ω load, no signal will be reflected back into the amplifier. The first
coupled port on the second directional coupler (II) measures the signal going out from
the DUT and the second coupled connection is connected to a 50 Ω load.
A power meter was connected to the directional couplers to measure the power
delivered to and from the DUT. The power meter is connected to the directional
couplers via a pair of power sensors. Channel A of the power meter is connected to the
directional coupler at the input and channel B is connected to the output directional
coupler. A 3-dB power divider is also added to the output directional coupler, which
splits the signal with an attenuation of 3-dB. A spectrum analyser was connected in
addition to the power sensor. The spectrum analyser was used to measure harmonics
when testing the DUT in CW mode. Furthermore an attenuator was connected between
the output directional coupler and the power divider to ensure that the power delivered
to the measurement equipment was not too high, otherwise the equipment could be
damaged.
-10
dB
A B
Power Meter
~
DUT Preamplifier
Signal generator
I II
PS -3 dB
Spectrum Analyser
Page | 50
Before running any measurements on an actual amplifier, the attenuation from input to
measurement points A and B was measured with a network analyser. The output port
on the network analyser is connected to the input instead of the signal generator. The
input port on the network analyser was first connected at measurement point I instead
of the power probe and then the same procedure for measurement point II. These
measurements give the built in attenuation in the measurement setup and the actual
power level measured at the power meter can be calculated.
In addition, two separate DC supplies, one for the gate and one for the drain bias were
used to bias the amplifiers. They are feed directly on to the amplifiers via a pair of
cables. A current probe was used for measurement of DC current in the drain power
supply, to calculate the efficiency. The current probe constitutes of a Rogowski coil
attached to a multimeter, measuring the induced voltage. The efficiency can be
calculated by using Equation (2.1), where Pout is the output power read by channel B at
the power meter, IDC is the DC current and VD is the drain DC voltage.
The signal supplied to the amplifier during power measurement was a pulsed sinusoidal
signal. The pulses had a duty cycle of 5 % at 14 Hz and contained a 100 MHz signal in the
pulse.
7.4 Single-Ended PA Measurements
Once the transistor and bias network components were soldered to the design it was
time to start the matching of the amplifier. The goal was to have the amplifier matched
at 100 MHz and at the same time filter the harmonics of the signal. The matching is
performed, by adding capacitors between the transmission line and ground, similar to
the simulation in Chapter 4. To enhance the process, a network analyser was attached to
the amplifier to measure S11 and S22 on the input and output side of the amplifier. The
effect of the capacitor was determined by three factors, the capacitance value, the
position of the capacitor in relation to the transistor and the transmission line thickness.
The uncertain effect on how the RF signal running through the amplifier was effecting
the matching was the difficulty of the matching. Instead of measuring hot S-parameters
the tuning had to rely on how the amplifier was matched cold, and how it changed when
DC was applied. The matching of the amplifier was shifted to a higher frequency when it
was supplied with DC and it was known that when the RF is supplied it would lower the
matching frequency, however, by a smaller value than the DC [15]. This implies, the
matching had to aim at a lower frequency than the desired 100 MHz in order to have a
good match when everything was on. Figure 7.1 displays the difference between an
unmatched and a matched S22 of the single-ended design.
Page | 51
(a) (b) Figure 7.2; (a) Unmatched, (b) Capacitors added
By iterating capacitor values and position on both the input and output side of the
transistor a final optimized matching network was reached, matched to a frequency
below 100 MHz, since by applying DC bias pushes the matching up in frequency. A
finished matching network implies that power measurements could begin on the
amplifier.
The power measurements was performed in accordance with section 7.2.1, i.e, by slowly
increasing the power at the input, measurements was made of the output power, gain
and efficiency. Early into the measuring of the single-ended design the result in the three
mentioned parameters clearly did not correlate with the expected results from the
simulations. It was especially the power delivered to the load and the efficiency that was
not satisfactory, which led to an iterative process in changing the design to find one that
would increase the mentioned parameters. Since the transmission lines were static on
the card the things that could be changed were limited, however by changing capacitor
values and positions affected the performance of the amplifiers. Figure 7.2 displays gain
and efficiency curves for different capacitor values.
The graphs in Figure 7.2, shows how different capacitor values change the
characteristics of the amplifier. A larger value of the total capacitance added to the
amplifier gives a better efficiency at low power input signals. However, the increased
capacitance value puts the transistor into voltage limitation, meaning that the transistor
needs more drain voltage than what is supplied, which made the gain drop rapidly. The
aim of the capacitance tuning was to have a gain characteristic of the 142 pF curve but
with a higher efficiency. Unfortunately, that seemed to be impossible by only the
changing the capacitance at the output.
Page | 52
(a)
(b)
Figure 7.2 The effect of changing capacitance. (a) Gain as a function of output power. (b) Efficiency as a function of
output power
Since changing the capacitor value did not make the amplifier reach enough output
power, with a good efficiency, other solutions had to be considered. A change in
quiescent current puts the transistor into other classes of operation, which according to
theory also would give a change in efficiency. However, this change had almost no effect
on the performance of the amplifier. To see if the matching network had been tuned at
the wrong frequency, the frequency was swept when running the amplifier. If the
network had been matched at the wrong frequency the output power would have
increased at another frequency; however, it did not occur. Concluding, the matching
network was tuned at the right frequency.
Another investigation on the low efficiency was to look at the waveform at different
points throughout the amplifier. The desired waveform was to have a pure sinusoidal at
the load. A pure curve form means the harmonics are smaller than in a curve form that is
not and that the reflections are as small as possible. Figure 7.3 displays two different
waveforms at the transistor, when more capacitance was added the curve got smoother.
20
21
22
23
24
25
26
27
28
29
30
100 300 500 700 900 1100
Ga
in (
dB
)
Output Power (W)
C=149 pF
C=182 pF
C=229 pF
C=246 pF
C=295 pF
0
10
20
30
40
50
60
100 300 500 700 900 1100
Eff
icie
ncy
(%
)
Output Power (W)
C=149 pF
C=182 pF
C=229 pF
C=246 pF
C=295 pF
Page | 53
(a) (b)
Figure 7.3 Difference in waveform when more capacitance is added, a 150pF, b 317pF
Due to that none of the above mentioned attempts of changing the amplifier to increase
the efficiency had worked. Furthermore, it had throughout the design been hard to get
the right impedance of about 1 Ω at the transistor, it was questioned if the impedance
matching was correct. To test if the transistor impedance was matched incorrectly the
load attached to the amplifier was varied. This measurement is comparable with the
load-pull simulation performed in ADS. The result of the load varying measurement is
seen in Figure 7.4.
Page | 54
(a)
(b)
Figure 7.4 Preformance at different loads. a Gain as a function of output power, b Efficiency as a function of output
power
Figure 7.3 shows that the amplifier achieves 1 kW in output power while remaining
within a gain compression of less than 1 dB at a load of 𝑍𝐿 = 17.4 + 𝑗 ∗ 28.3. The
efficiency has also been increased, reaching 83 % at 1 kW of power delivered to the load.
Such high efficiency means that the amplifier is running in class E or F and becomes a
resonant circuit, making its performance even better than predicted by the simulations.
The result implies that the impedance the transistor sees at the drain is too high, which
means the amplifier is not able to give these figures without changing the load.
7.5 Push-Pull Measurements
The first measurement on the Push-Pull amplifier was performed with the setup from
simulation in ADS. The power on the input and output were measured in accordance to
the power measurement setup. The measurement result differed with the simulated
results and therefore capacitor tuning was performed. The result from these
measurements can be seen in Figure 7.5, the given capacitance values represents the
total capacitance on the input of the amplifier. The tuning did not give any drastic
20
21
22
23
24
25
26
27
28
29
30
0 200 400 600 800 1000 1200
Ga
in (
dB
)
Output Power (W)
CAP Z=17.4-j28.3 Ω
IND Z=17.4+j28.3 Ω
CAP Z=59.9-j12.4 Ω
0
10
20
30
40
50
60
70
80
90
100
0 200 400 600 800 1000 1200
Eff
icie
ncy
(%
)
Output Power (W)
CAP Z=17.4-j28.3 Ω
IND Z=17.4+j28.3 Ω
CAP Z=59.9-j12.4 Ω
Page | 55
16
17
18
19
20
21
22
23
24
25
26
0 100 200 300 400 500
Ga
in (
dB
)
Output Power (W)
C=232 pF
C=194 pF
C=82 pF
0
10
20
30
40
50
60
70
0 100 200 300 400 500
Eff
icie
ncy
(%
)
Output Power (W)
C=232 pF
C=194 pF
C=82 pF
changes in performance, as can be seen by comparison between lines in Figure 7.5.
Other parameters were also changed during the iterative tuning, such as capacitors and
inductor on the output matching network. These changes did not result in any major
improvements than the ones presented in Figure 7.5.
(a)
(b) Figure 7.5 Initial power measurements on the Push-Pull amplifier (a) gain as a function of output power at
different capacitance values, (b) efficiency as a function of output power at different capacitance values
As previously seen in the simulations done in ADS and CST on the BALUN, the pass band
on the transfer function is wide (See Figure 5.5). It could imply that the amplifier is
matched at the wrong frequency, the pass band is shifted up or down in frequency. The
centre frequency is outside the pass band, i.e, resulting in poor performance. The reason
was that the matching capacitors had not been tuned correctly, making the BALUNs
resonate at the wrong frequency. A sweep in frequency was performed with input
power turned on, to find a frequency were the matching is better. The measurements
shows, the amplifier was better matched at 115 MHz and had a pass band (-3 dB) from
92,5 MHz to 122 MHz. Figure 7.6, displays the difference in performance at 100 MHz and
115 MHz.
Page | 56
16
17
18
19
20
21
22
23
24
25
26
0 200 400 600 800 1000
Ga
in (
dB
)
Output Power (W)
f=100 MHz
f=115 MHz
0
10
20
30
40
50
60
70
80
90
0 200 400 600 800 1000
Eff
icie
ncy
(%
)
Output Power (W)
f=100 MHz
f=115 MHz
(a)
(b) Figure 7.6 Push-Pull amplifier measured at different frequency (a) gain as a function of output power at different capacitance values, (b) efficiency as a function of output power at different capacitance values
Figure 7.6a, displays a gain curve that is lower at 115 MHz but goes into compression for
a higher output power in comparison to 100 MHz. The efficiency in Figure 7.6b, reaches
a maximum of 76.5 % for a output power of 865 W at 115 MHz. The result at 115 MHz
shows that the amplifier is capable of delivering a high efficiency. However, the amplifier
does not reach 1 kW before going into -3 dB compression. A single measurement was
also performed with other values on the shunt inductor, which resulted in an output
power of over 1 kW with maintained efficiency at 115 MHz.
Page | 57
Chapter 8
Discussion and Conclusion The aim of the work presented in the thesis was to design, fabricate and measure a 1 kW
solid-state PA operating at 100 MHz for use in a cyclotron. From the beginning the idea
was to develop one preamplifier at 5 W and one power amplifier at 1 kW. The project
resulted in two different topologies of PA and the preamplifier was put on hold until
later into the project. There were no time to manufacture a prototype of the
preamplifier and therefore the functionality could not be measured and verified.
Although the thesis work did not include everything that was initially defined, two solid-
state PAs have been designed, prototypes manufactured and and evaluated through
measurements. Moreover, the design was performed using a technique that is not
common for this frequency, fact that make the thesis work narrow to research activity.
Although the amplifiers did not performed completely as specified, first results indicates
that both PAs have potential to reach the project specifications with some further work
and that the design approach is suitable for this kind of amplifiers. The following section
will discuss and conclude the biggest challenges during the project and also discuss
further work.
8.1 Conclusion of Single-ended Design
The single-ended design has fulfilled many of the conditions set in advance of the project
especially regarding simplicity of the topology. However, the design became large and
does not satisfy the power and efficiency conditions without optimizing the load
impedance value.
To utilize a single-ended design at this relatively low frequency with the impedance that
the transistor needs, within the measurements limits given, has posed compromises.
Since it was not possible to achieve the desired impedance at the transistor, a change in
substrate was considered. Changing to a substrate with a higher dielectric constant, gave
the possibility to create lower impedance at the transistor without changing the
dimensions unfortunately, this was proven in the measurements not to be enough to
make the transistor to deliver the specified power.
The amplifiers potential is displayed in Figure 7.4 were the load was changed to a lower
impedance value. In the measurement, the amplifier reaches efficiency levels beyond the
base classes of amplifiers. The high efficiency implies that the amplifier has become a
resonant circuit, which means that it is using the harmonics to give a higher gain and
Page | 58
efficiency. When an amplifier is using its harmonics to produce more power it is
operating in class E or F mode; however, more measurements have to be conducted to
be sure. To design an amplifier of Class E or F was not the target in the beginning of the
thesis; however, since the simulated harmonics were low, the design showed potential
in altering the class of operation.
Making the amplifier produce the high figures was one of the last measurements
performed to investigate why its efficiency initially was modest. Prior the last edit was a
substantial pursuit to find what was the problem with the amplifier. Numerous of
iterations and measurements were conducted, especially in changing the capacitance,
since the thought was that the problem was within tuning. However, the problem was
more profound and bigger changes of the design had to be made to make it work
properly.
A conclusion regarding the type of design is that it is well suited for this kind of
application, when simplicity and repeatability is important. Unfortunately, independent
of whatever dielectric is used, the design becomes physically large at the frequency
range used in the thesis. Further, a large design is more sensitive to parasitic
capacitances, harmonics and more complex to troubleshoot, a lesson learnt at the end of
the project. However, the single-ended design reaches 88 % at 1000 W output power
with a decreased load. And by additional measurements and tuning the amplifier will
probably reach the same values at a 50 Ω load.
8.2 Conclusion of Push-Pull Design
Important to take into consideration regarding the push-pull amplifier designed with
planar BALUNs, little has been written in this field at 100 MHz. The litterateur found on
the subject is brief and misses significant theory on how to design push-pull amplifiers
using planar BALUNs. Therefore, significant time has been spent on understanding the
functionality of the planar BALUN. This has also given an understanding on how to
improve the measurements results and why they did not satisfy the goals. With
additional measurement and tuning it is likely that the amplifier can be fine-tuned to
100 MHz and to make the BALUNs resonate at the right frequency.
During measurements on the push-pull amplifier it is hard to verify the functionality of
the BALUN´s. To enhance this measurement separate BALUNs could have been
manufactured for verification of functionality, prior to manufacturing the whole
amplifier. Measurements on a stand-alone BALUN could have given answer to how much
phase shift it is between the balanced ports and what the transfer function looks like.
Further, tuning for optimisation would also have been easier if the performance of all
individual parts were known.
Page | 59
Parts of the push-pull amplifier was simulated in different simulation software’s and
later merged in ADS for verification of functionality. This has proven to be more
complicated than expected and brought extra work with export between simulation
software’s. Even though, a lot of time were spent on converting the BALUNs from CST to
ADS it did not succeed. Therefore, simulation data had to be exported as a S-parameter
file instead of a component, imported into ADS and simulated as a S-parameter block. It
resulted in that the amplifier could not be completely simulated as a complete layout
component, like the single-ended design. Furthermore, it also gave another argument to
why it would be good to manufacture the BALUN´s separately.
The thesis has proven that it is possible to manufacture a small and a low complexity
amplifier, with the use of planar BALUNs at VHF delivering good efficiency and gain.
Even though it is not as simple to manufacture as the single-ended design it will save
time during the manufacturing process, due to the use of a planar structure instead of
i.e., coaxial cable. The measurement performed at 115 MHz shows promising results. As
mentioned, with some additional tuning it would have been possible to run the amplifier
at 100 MHz, achieving similar results.
8.3 Simulation and Measurement
The reliability in simulations and measurements can always be questioned, especially
when regarding working with high frequency. It was proven at several times throughout
the thesis was that the simulation programs gave a solid foundation, differences
compared to measured result still existed. At times major changes had to be made in
order to achieve results corresponding to the simulations. These findings can probably
be explained by assumptions and generalizations in the simulation environment,
especially regarding parasitic capacitances and harmonics. Furthermore, both the
transistor model and the load-pull simulations can be questioned in their accurateness,
since the simulations differed a lot from the reality. However they both provided
progression into the design instead of using calculations by hand.
Throughout the simulation phase of the project the focus was on getting a high gain,
though as experience was gathered it should have been shifted to efficiency and
waveform. Since in the measurements presented a good gain was achieved through with
a poor efficiency, mainly regarding the single-ended design. However, simulations
performed on the design showed promising results regarding effectiveness, which also
arises questions: are the simulations adequate?
During the measurements there has been a constant uncertainty of the accuracy of them.
Reaching an effectiveness of 88 % was something extraordinary that posed questions
about the reliability in the measurements. Preforming measurements on high power
levels at this frequency with a pulse duty cycle of 5 % sets high demand on the
measurement equipment. Further, performing measurements on hot S-parameters
Page | 60
would have made tuning of the amplifiers easier, though this was not possible. Instead a
trial and error approach was conducted when tuning the amplifiers.
8.4 Thesis Conclusion
Two PAs have been designed, manufactured and tested for evaluation. Nevertheless,
more time is needed for testing to come to final conclusions, to optimise and finalize the
design. Even though all goals have not been achieved, the project has given GE two 1 kW
solid-state based amplifiers that have the potential of fulfilling their needs. It has also
taken them one step closer to taking control of the production of power amplifiers for
use in their new cyclotrons. The work can be used as a foundation for future work, on
developing and understanding of planar structured PAs.
Page | 61
References [1] Diversity [Internet]. General Electric; [2015; Cited: 27-05-2015]. Available
from: http://www.ge.com/careers/culture/diversity [2] Ludwig R, Bogdanov G. RF Circuit Design: Theory and Application. 2nd
Edition. Pearson Education; 2009 [3] Pozar D M. Microwave Engineering. 4th Edition. Whiley; 2012 [4] Kazimierczuk M K. RF Power Amplifier. John Wiley & Sons. 2008 [5] Krauss H L, Bostian C W, Frederick H R. Solid State Radio Engineering. John
Wiley & Sons. 1980 [6] Cripps S C. RF Power Amplifiers for Wireless Communication. 2nd Edition.
Artech House. 2006 [7] AN10858: 174 MHz to 230 MHz DVB-T power amplifier with the BLF578
[Internet]. NXP Semiconductor. [Publiced: 26-03-2010; Cited: 27-05-2015]. Available from: http://www.nxp.com/documents/application_note/AN108585.pdf
[8] Fitz Patrick D. Modelling of a Printed VHF Balun Using E-M Simulation
Techniques. Paper presented at ARMMS Conference. 04-2013. Oxfordshire [9] BLF188XR; BLF188XRS: Power LDMOS transistor [Internet]. NXP
Semiconductor. [Publiced: 12-11-2013; Cited: 27-05-2015]. Available from: http://www.nxp.com/documents/data_sheet/BLF188XR_BLF188XRS.pdf
[10] BLF571; BLF571: HF / VHF power LDMOS transistor [Internet]. NXP
Semiconductor. [Published: 24-02-2009; Cited: 27-05-2015]. Available from: http://www.nxp.com/documents/data_sheet/BLF571.pdf
[11] Clayton R P. Introduction to Electromagnetic Compatibility. 2nd Edition.
John Wiley & Sons. 2006 [12] RO3000 Series Circuit Materials: RO3003, RO2006, RO3010 and RO3035
High Frequency Laminates [Internet]. Rogers Corporation. [Published: 2015; Cited: 27-05-2015]
[13] BLF188XR; Simulation Model for ADS 2012. NXP Semiconductor.
[Published: 29-04-2014; Cited: 01-02-2015]. Available from: http://www.nxp.com/products/mosfets/rf_power_transistors_ldmos/broadcast/0_500_mhz_hf_vhf/BLF188XR.html#support
Page | 62
[14] BLF571; Simulation Model for ADS 2011. NXP Semiconductor. [Published: 20-06-2013; Cited: 01-02-2015]. Available from: http://www.nxp.com/products/mosfets/rf_power_transistors_ldmos/rf_energy_ism/0_500_mhz_ism_xr_products/BLF571.html#support
[15] Dancila D, et al.. Solid-State Amplifier Development at FREIA. IPAC2014.
Dresden Germany.
Page | i
Appendix A
A.1 Harmonic Balance Simulations Equations
𝑃𝑑𝑖𝑠𝑠_𝑇𝑖𝑚𝑒 = (𝑡𝑠(𝑉𝑙𝑜𝑎𝑑[1])) ∗ (𝑡𝑠(𝐼𝐿𝑜𝑎𝑑[1]))
𝑃𝑑𝑖𝑠𝑠 = ∫ |𝑃𝑑𝑖𝑠𝑠_𝑇𝑖𝑚𝑒
20 ∗ 10−9|
𝑃𝑜𝑢𝑡 = (0.5 ∗ 𝑟𝑒𝑎𝑙( 𝑉𝑙𝑜𝑎𝑑 ∗ 𝑐𝑜𝑛𝑗(𝐼𝐿𝑜𝑎𝑑))
𝜂 = 𝑃𝑜𝑢𝑡[1]
𝑃𝑑𝑖𝑠𝑠 + 𝑃𝑜𝑢𝑡[1]
𝑃𝑜𝑢𝑡_𝑑𝐵𝑚 = 10 ∗ log(0.5 ∗ 𝑟𝑒𝑎𝑙( 𝑉𝑙𝑜𝑎𝑑 ∗ 𝑐𝑜𝑛𝑗(𝐼𝐿𝑜𝑎𝑑))) + 30 𝐺𝑎𝑖𝑛 = 𝑃𝑜𝑢𝑡_𝑑𝐵𝑚[1] − 𝑃𝐼𝑁 𝑃𝐷𝐶 = 𝑟𝑒𝑎𝑙(𝑉𝐷𝐶2[0] ∗ 𝐷𝐶2[0]
𝑃𝐴𝐸 =𝑃𝑜𝑢𝑡[1] − 𝑑𝑏𝑚𝑡𝑜𝑤(𝑃𝐼𝑁)
𝑃𝐷𝐶
𝐸𝑓𝑓𝑖𝑐𝑖𝑒𝑛𝑐𝑦 = 𝑚𝑎𝑔 (𝑃𝑜𝑢𝑡[1]
𝑃𝐷𝐶) ∗ 100
A.2 Stability Simulation Equation
Δ = 𝑚𝑎𝑔𝑑𝑒𝑙𝑡𝑎 = 𝑚𝑎𝑔(𝑆11 ∗ 𝑆22 − 𝑆12 ∗ 𝑆21)
Page | ii
Appendix B - Heat Sink Drawings
B.1 Single-Ended Heat Sink Drawing
Page | iii
B.2 BALUN Heat Sink Drawing
Page | iv
B.3 Heat Sink GE
Page | v
B.4 Single-Ended Amplifier
B.5 Push-Pull amplifier
Page | vi
Appendix C
C.1 Bill of Materials (BOM)
D
esignQ
uantity
Descrip
tion
Dis
tributo
r Part n
um
ber
Manufa
ctu
rer P
art N
um
ber
Pric
e (S
ek)
Dis
tributo
rS
um
(Sek)
BA
LUN
2A
luminium
elektrolytkondensator SM
D 470 µ
F 80 VD
C
67-240-25EEEFK1K471A
M20,72
Elfa41,44
BA
LUN
1Keram
isk kondesator SMD
2,2 µF 100 V
DC
65-503-05
GR
M32ER
72A225KA
35L14,3
Elfa14,3
BA
LUN
1Keram
isk kondensator SM
D 0,1 µ
F 100 VD
C65-611-46
C1206F104K1R
AC
780011,6
Elfa11,6
BA
LUN
2Keram
isk kondensator SM
D 1 µ
F 100 VD
C65-502-97
GR
M31C
R72A
105KA01L
0,7195Elfa
1,439
BA
LUN
1Keram
isk kondensator SM
D 820 pF 100 V
DC
65-832-80C
1206C821J1G
AC
C-7025
3,89Elfa
3,89
Single-ended
1C
apacitor, radial 100 uF 100 VD
C67-258-36
ECA
2AH
G101
6,65Elfa
6,65
Single-ended
1C
apacitor, radial 220 uF 100 VD
C67-258-37
ECA
2AH
G221
11Elfa
11
Single-ended
5C
apacitor SMD
100 pF 100 VD
C 1206
65-772-25C
1206C101J1G
AC
C-7025
3,72Elfa
18,6
Single-ended
1R
esistor SMD
47 Ω ± 1 %
120660-547-04
CR
CW
120647R0FKEA
0,447Elfa
0,447
Single-ended
1R
esistor SMD
56 Ω ± 1 %
120660-547-05
CR
CW
120656R0FKEA
0,447Elfa
0,447
Single-ended
1R
esistor SMD
33 Ω ± 1 %
120660-547-02
CR
CW
120633R0FKEA
0,447Elfa
0,447
Single-ended
1R
esistor SMD
100 Ω ± 1 %
120660-547-08
CR
CW
1206100RFKEA
0,447Elfa
0,447
Summ
a ELFA=
110,707
BA
LUN
2Keram
isk kondensator SM
D 10 µ
F 100 VD
C2112740R
LC
5750X7S2A106M
230KB14,11
Farnell28,22
BA
LUN
10Keram
isk kondensator SM
D 10 nF 100 V
DC
2320874M
C1206B
103K101CT
0,464Farnell
4,64
BA
LUN
2Keram
isk kondensator SM
D 1000 pF 630 V
DC
2218779G
RJ31B
R72J102KW
J1L1,27
Farnell2,54
BA
LUN
1Keram
isk kondensator SM
D 43 pF 500 V
DC
2218728G
QM
22M5C
2H4
30JB01L
10,55Farnell
10,55
BA
LUN
1Keram
isk kondensator SM
D 10 nF 500 V
DC
1855331C
1210X103KCR
AC
TU6,36
Farnell6,36
Single-ended
2C
apacitor SMD
33PF, 630V, 1206
2218883G
RM
31A5C
2J330JW01D
1,97Farnell
3,94
Single-ended
10C
apacitor SMD
18PF, 630V, 1206
2218878G
RM
31A5C
2J180JW01D
1,7Farnell
17
Single-ended
/ BA
LUN
Summ
a Farnell=73,25
1C
apacitor MIN
300VKIT 3.3pF-150pF
5981-MIN
300VKIT1
MIN
300VKIT1
469M
ouser469
1C
apacitor MC
F100VKIT 3.3pF-150pF
5982-MC
F100VKIT4
MC
F100VKIT4
394M
ouser394
Summ
a Mouser
863
Summ
a = 1 046,96 kr