1 l-edit tutorial eel 4310. 2 why use l-edit? l-edit is a freeware and is very useful for academic...
TRANSCRIPT
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L-EDIT Tutorial
EEL 4310
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Why use L-edit?
• L-Edit is a freeware and is very useful for academic purposes
• Though industry uses Cadence, L-Edit can illustrative the significant points for laying out CMOS circuits. Cadence is rather complex in comparison.
• L-Edit can be used to extract parasitic capacitance which enables us to predict the delay in CMOS circuits.
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DOWNLOAD INSTRUCTIONS
• The downloadable version of L-edit can be found in Dr Thompson’s website.
http://www.thompson.ece.ufl.edu/Fall2007/downloads.htm
• Download the file from the first link- stu712.zip:
Ftp site for L-Edit Pro student version • You can also download L-Edit from
www.tanner.com/eda
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Setup
• This version must run in 256 colors.
• For Windows XP users, set the display by right clicking the short cut created for L-edit and choosing properties.
• Then click the compatibility tab. Under display settings click 256 colors.
• Open L-edit
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Drawing Layout
• Create new Layout file– File > New.– In the following open window, Browse and choose
‘mamin08.tdb’ in ‘Copy TDB setup from file’ area. It usually locates in ~\stu712\mosis\. Else browse to find mamin08.tdb located in the mosis folder of stu712 file
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Relationship between Lambda and Microns
• Setup > Design
Establishing =.5, therefore
2=1
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To establish GRID
• Zoom the window to see grid
• Distance between grid points is 1 lambda
• In order to set mouse snap to Grid :– Click Setup -> Design– Click on the Grid tab– Set Mouse snap grid to 1 locator unit
Now the technology is setup!
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Inverter Layout
• Layout Specifications:
NMOS:– L = 2 Lambda, W = 6 Lambda
PMOS:– L = 2 Lambda, W = 12 Lambda
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PMOS• Choose N-Well in the left palette
and draw a box.• In the N-Well area, draw P-
Select. Notice that the size and position should obey Design Rule, which can be found at http://www.mosis.org/Technical/Layermaps/lm-scmos_scnpc.html.
• With the help of DRC button , the violation of design rule can be shown by right clicking the place which is highlighted. It is a good idea to run DRC at each stage of your design so that you can fix any error along the way
• Draw Active.• Draw Poly.
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NMOS
• Do not need to draw P-Well because the empty grid of L-Edit stands for P-Well.
• Draw N-Select.• Draw Active.• Draw Poly.
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Power Lines
• Draw Vdd and Gnd Lines
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Well Taps
• For PMOS, place a small N-Select on the N-Well, add a small Active layer. From this active layer put contacts to the Metal1 layer that connects to VDD.
• For NMOS, on the P-Well substrate, place a small P-Select and then Active layer. From this active layer put contacts to the Metal1 layer that connects to GND.
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• Connect Poly of PMOS and NMOS.
• Connect source of PMOS to VDD by Metal1.
• Connect source of NMOS to GND by Metal 1.
• Connect Drain of PMOS and NMOS by Metal 1.
• Add an input connect between Metal1 and Poly.
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LABELS
• Label the INPUT, OUTPUT, VDD and GND using button
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Design Rule Check
• Click Tools -> DRC (or the DRC box in the toolbar)
• Run DRC for the total layout.
• Click the Write errors to file box, and give a descriptive filename
• Fix the errors listed.
• Once there is no DRC error shown, the layout is ready to be extracted.
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Submitting HW
• When submitting an L-edit file as part of a homework or project, mail it to
• I only need the *.tdb file
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