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1 Memory Management Chapter 4 1 Basic memory management 2 Swapping 3 Virtual memory / Paging 4 Page replacement algorithms 5 Modeling page replacement algorithms 6 Design issues for paging systems 7 Implementation issues 8 Segmentation

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Page 1: 1 Memory Management Chapter 4 4.1 Basic memory management 4.2 Swapping 4.3 Virtual memory / Paging 4.4 Page replacement algorithms 4.5 Modeling page replacement

1

Memory Management

Chapter 4

4.1 Basic memory management4.2 Swapping4.3 Virtual memory / Paging4.4 Page replacement algorithms4.5 Modeling page replacement algorithms4.6 Design issues for paging systems4.7 Implementation issues4.8 Segmentation

Page 2: 1 Memory Management Chapter 4 4.1 Basic memory management 4.2 Swapping 4.3 Virtual memory / Paging 4.4 Page replacement algorithms 4.5 Modeling page replacement

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Memory Management

• Ideally programmers want memory that is– large

– fast

– non volatile

• Memory manager administers memory partitions and their allocation to processes

• Memory hierarchy – small amount of fast, expensive memory – cache

– some medium-speed, medium price main memory

– gigabytes of slow, cheap disk storage

• Memory manager handles the memory hierarchy

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Grundprobleme der Speicherverwaltung

Speichervorrat

Speicherstücke /Speicherbereiche

z.B.für Programmcodeund Datenbereiche

• Belegen und Freigeben von Speicherstücken

• Unterschiedliche Reihenfolgen,z.B. Keller-artig (LIFO), FIFO, beliebig

• Stücke konstanter Länge, unterschiedlicher Länge, Vielfacher konstanter Einheiten

• Zerstückelung des Speichers

• Kompaktieren / Verschieben

• Verschiebliche Speicherinhalte

• Verwaltungsaufwand

• Verschnitt

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Basic Memory ManagementMonoprogramming without Swapping or Paging

Three simple ways of organizing memory- an operating system with one user process

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Multiprogramming with Fixed Partitions

Fixed memory partitionsa) separate input queues for each partitionb) single input queue

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Relocation and Protection

• Cannot be sure where program will be loaded in memory– address locations of variables, code routines cannot be absolute

– must keep a program out of other processes’ partitions

• Use base and limit values– address locations added to base value to map to physical addr

– address locations larger than limit value is an error

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Swapping

Swapping ::=Prozesse werden insgesamt in Arbeitsspeicherein- bzw. ausgelagert

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Swapping (1)

Memory allocation changes as – processes come into memory– leave memory

Shaded regions are unused memory

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Swapping (2)

• Allocating space for growing data segment• Allocating space for growing stack & data segment

Bei dynamisch wachsender Bereichsgröße muss Maximalbedarf vorab reserviert werden.

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Variabel lange Stücke

als Vielfache konstanter Grundeinheiten

Verwaltung per Bitvektor (Bit Map)

(häufig bei Festplatten verwendet)

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Memory Management with Bit Maps

a) Part of memory with 5 processes, 3 holes1. tick marks show allocation units2. shaded regions are free

b) Corresponding bit mapc) Same information as a list

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Variabel lange Stücke

in beliebiger Länge

Verwaltung über verzeigerte Listen

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Speicherverwaltung mit verzeigerten Listen

• Listen: Freiliste, Belegtliste• Probleme: Zerstückelung, Verschmelzung freier Nachbarn, Kompaktieren• u.U. Sortieren der Freiliste: First Fit, Best Fit, ..

Frei:

Belegt:

Verwaltungsdaten imSpeicherstück:

• Stücklänge• Nachfolgerzeiger• Nachbarn finden

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Speicherverwaltung mit Tabellen

• Probleme: Zerstückelung, Verschmelzung freier Nachbarn, Kompaktieren

• Problem: Tabellenüberlauf: Reorganisation

Verwaltungsdaten in separaterStücktabelle:• Stückposition• Stücklänge• Frei / Belegt

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Virtueller Speicher• Prozesse bekommen Speicherbereiche

mit jeweils eigenem Adressraum unabhängig vom tatsächlich vorhandenen Arbeitsspeicher

• Verwaltung “seitenweise”: Paging

• Adressabbildung mit jedem Zugriff:MMU

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Virtual MemoryPaging (1)

The position and function of the MMU

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Paging (2)

The relation betweenvirtual addressesand physical memory addres-ses given bypage table:

1 Eintrag pro Seite

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Page Table

Internal operation of

MMUwith 16

4 KB pages

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Page Table Entry

Typical page table entry

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Multilevel Page TablesProblem:

Sehr große Seitentabellen

Multilevel Tabellen(nicht alle Tabellenimmer im Speicher)

• 32 bit address with 2 page table fields

• Two-level page tables

Second-level page tables

Top-level page table

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Inverted Page Tables

Comparison of a traditional page table with an inverted page table

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TLBs – Translation Lookaside Buffers

A TLB to speed up paging

(Assoziativspeicher-Tabelle in der MMU)

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Seitentausch• Virtuelle Adressräume >> Arbeitsspeicher:

Seiten müssen während des Betriebs ausgetauscht werden!

• Ablauf dazu:1. Seite n wird von Prozessor aus angesprochen

2. MMU erkennt: Seite n ist nicht im Arbeitsspeicher

3. Seitenfehlerinterrupt Interruptroutine

4. Wenn kein freier Seitenrahmen vorhanden:o Seite zum Auslagern auswählen (Strategie!!)o Auslagern

5. Seite n einlagern

6. Fortsetzen der Befehlsbearbeitung

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Page Replacement Algorithms

• Page fault forces choice – which page must be removed– make room for incoming page

• Modified page must first be saved– unmodified just overwritten

• Better not to choose an often used page– will probably need to be brought back in soon

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Optimal Page Replacement Algorithm

• Replace page needed at the farthest point in future– Optimal but unrealizable

• Estimate by …– logging page use on previous runs of process– although this is impractical

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Not Recently Used Page Replacement Algorithm

• Each page has Reference bit, Modified bit– bits are set when page is referenced, modified

• Pages are classified1. not referenced, not modified

2. not referenced, modified

3. referenced, not modified

4. referenced, modified

• NRU removes page at random– from lowest numbered non empty class

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FIFO Page Replacement Algorithm

• Maintain a linked list of all pages – in order they came into memory

• Page at beginning of list replaced

• Disadvantage– page in memory the longest may be often used

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Second Chance Page Replacement Algorithm

• Operation of a second chance– pages sorted in FIFO order, reference bit (R bit) set at access

• Example:Page list if fault occurs at time 20, A has R bit set(numbers above pages are loading times)

1. A is referenced: R bit set

2. Page replacement active: A gets second chance

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The Clock Page Replacement Algorithm

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Least Recently Used (LRU)

• Assume pages used recently will used again soon– throw out page that has been unused for longest time

• Must keep a linked list of pages– most recently used at front, least at rear– update this list every memory reference !!

• Alternatively keep counter in each page table entry– choose page with lowest value counter– periodically zero the counter

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Working Set Modell nach Denning• Lokalität der Speicherzugriffe

In jeder Phase seines Ablaufs greift ein Prozess immer nur auf eine Teilmenge der Seiten zu: Aktueller Working Set

• ThrashingWenn weniger Speicher verfügbar ist, als der momentane Working Set lang ist, verursacht der Prozess äußerst häufige Seitenwechsel. Er kommt kaum noch weiter.

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The Working Set Page Replacement Algorithm (1)

• The working set is the set of pages used by the k most recent memory references

• w(k,t) is the size of the working set at time, t

k

w(k, t)

AnzahlSeiten

für einen Zeitpunkt t:

Bei großen k ist Steigung nahe 0 !

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The Working Set Page Replacement Algorithm (2)

The working set algorithm

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Review of Page Replacement Algorithms

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Modeling Page Replacement AlgorithmsBelady's Anomaly

Referenzfolge

Speicherbelegung

a) FIFO with 3 page framesb) FIFO with 4 page framesa) hat trotz geringerem Speicher weniger Seitenfehler als b)

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Design Issues for Paging SystemsLocal versus Global Allocation Policies

a) Original configurationb) Local page replacementc) Global page replacement

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Wieviel Speicher braucht ein Prozess momentan?

Page fault rate as a function of the number of page frames assigned

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Load Control

• Despite good designs, system may still thrash

• When PFF algorithm indicates – some processes need more memory – but no processes need less

• Solution :Reduce number of processes competing for memory– swap one or more to disk, divide up pages they held– reconsider degree of multiprogramming

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Weitere Aspekte

• Optimale Seitengröße

• Mehr Bereichepro Prozess

• Geteilte Seiten

• Seiten räumen

• Implementierung

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Page Size (1)

Small page size

• Advantages– less internal fragmentation – better fit for various data structures, code sections– less unused program in memory

• Disadvantages– programs need many pages, larger page tables

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Page Size (2)

• Overhead due to page table and internal fragmentation

• Where– s = average process size in bytes

– p = page size in bytes

– e = page entry

2

s e poverhead

p

page table space

internal fragmentatio

n

Optimized when

2p se

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Separate Instruction and Data Spaces

links: One address spacerechts: Separate I and D spaces

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Shared Pages

Two processes sharing same program sharing its page table

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Cleaning Policy

• Need for a background process, paging daemon– periodically inspects state of memory

• When too few frames are free– selects pages to evict using a replacement algorithm

• It can use same circular list (clock) – as regular page replacement algorithm

but with different pointers

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Implementation IssuesOperating System Involvement with Paging

Four times when OS involved with paging1. Process creation

determine program size create page table

2. Process execution MMU reset for new process TLB flushed

3. Page fault time determine virtual address causing fault swap target page out, needed page in

4. Process termination time release page table, pages

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Page Fault Handling (1)

Page Fault Occurs

1. Hardware traps to kernel

2. General registers saved

3. OS determines which virtual page needed

4. OS checks validity of address, seeks page frame

5. If selected frame is dirty, write it to disk

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Page Fault Handling (2)

6. OS brings new page in from disk

7. Page tables updated

Faulting instruction backed up to when it began

6. Faulting process scheduled

7. Registers restored

Program continues

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Instruction Backup

An instruction causing a page fault• Seitenfehlerinterrupt wird mitten in Befehlsausführung

erzeugt

• Unterbrechung der Befehlsausführung

• Fortsetzung an unterbrochener Stelle

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Locking Pages in Memory

Virtual memory and I/O occasionally interact, e.g.:• Process issues a call for read from device into

buffer– while waiting for I/O, another processes starts up– has a page fault– buffer for the first process may be chosen to be paged

out

• Need to specify some pages locked– exempted from being target pages

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Backing Store

(a) Paging to static swap area(b) Backing up pages dynamically

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Segmentierung

• Mehrere unabhängig verlängerbare Speicherbereiche pro Prozess:

Segmente, je Segment eine eigene Adress-Dimension /ein eigener Adressraum

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• One-dimensional address space with growing tables

• One table may bump into another

Segmen-tation (1)

Beispiel:Compiler-Prozess

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Segmentation (2)

Allows each table to grow or shrink, independently

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Seg-men-tat-ion

Com-parison

of paging

and segmentation

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Implementation of Pure Segmentation

(a)-(d) Entstehung einer Zerstückelung(e) Entfernen der Zerstückelung durch Kompaktieren

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Segmentation with Paging: MULTICS (1)

• Jedes Segment hat eigene Seitentabelle.• 2 Seitenlängen.links: Descriptor segment points to page tablesrechts: Segment descriptor (numbers are field lengths)

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Segmentation with Paging: MULTICS (2)

A 34-bit MULTICS virtual address

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Segmentation with Paging: MULTICS (3)

Conversion of a 2-part MULTICS address into a main memory address

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Segmentation with Paging: Pentium (1)

Segment Selector (Inhalt der Segmentregister) enthält Index eines Segment Descriptors in der Segmenttabelle

2 Segmenttabellen:• Global Descriptor Table (GDT), BS und allen Prozessen gemeinsam

• Local Descriptor Table (LGT), spezifisch je Prozess

6 Segmentregister im Prozessor (CS: Code), DS: Data, ..)werden mit 16-bit Segment Selector geladen:

(Protection)

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Segmentation with Paging: Pentium (2)

Wichtige Inhalte• Segment Basis Adresse (Base)• Segmentgröße (Limit)

Segment Descriptor

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Segmentation with Paging: Pentium (3)

Conversion of a (selector, offset) pair to a linear address

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Segmentation with Paging: Pentium (4)

Mapping of a linear address onto a physical address in case of enabled paging