1 microprocessor-based systems course 9 design of the input/output interfaces (continue)
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Microprocessor-based Systems
Course 9 Design of the input/output interfaces (continue)
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Transfer through direct memory access (DMA- Direct memory access)
Why is it used? To increase the transfer speed In order to release the main processor from the transfer task
Implementation mode: Specialized circuit for handling the transfer – the DMA controller The transfer is programmed by the processor and than it is performed
by the DMA controller: the transfer is made between the memory and an I/O interface without the direct implication of the main processor
The transfer phases: Initialization: - the main processor programs the parameters of the
transfer (the DMA controller is behaving as a slave) The address of the memory zone The direction of the transfer The number of transferred data
The transfer phase: the controller performs the transfer and solve the synchronization with the peripheral device (the DMA controller is a master)
End of the transfer: the processor test the correctness of the transfer by reading the status of the DMA controller (the DMA controller is a slave)
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The scheme of connecting a DMA controller into a microprocessor system
Memory Address bus Data Bus μP Command Bus HOLD DMA DRQ Input/Output HLDA controller DACK interface
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The sequence for handling a DMA request1. An interface requires a transfer by activating the DRQi signal to the DMA
controller2. The DMA controller tests if the request is enabled and if there are no other
higher priority transfers in progress 3. If the request is enabled and there is no other request than it requests the
control of the bus by generating a HOLD signal to the processor4. The processor finishes the last cycle on the bus and than disables its bus
amplifiers (leaving the control of the bus to the DMA controller) and grants the HOLD request with the signal HOLDA (Hold Acknowledge) to the controller
5. The DMA controller take over the control of the bus by activating its bus amplifiers; it generates an address for the memory and DACKi (DMA Acknowledge) signal to the interface
6. The DMA controller generates a memory read signal (MRDC/) or an interface read signal (IORC/)
7. The addressed unit (memory or interface) generates the required data8. The DMA controller generates an interface write signal (IOWC/) or a memory
write signal (MWTC/); as result the data is transferred from the memory to the interface or vice-versa
9. The interface disable the DRQi signal and as a result the DMA controller disables its bus amplifiers
10. The DMA controller disables the HOLD signal, giving up the control of the bus in favor of the processor
11. The processor disables the HLDA signal, it activates its bus amplifiers and continues with the execution of instructions
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Time diagram for a DMA transfer
Address CPU DMA address CPU addr.
Data CPU DMA data
DRQ
HOLD
HLDA
DACK
MRD\
IOW\
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Internal structure of the I8237 DMA controller
IOR\ Decr. Inc./Decr. Addr. IOW\ Amp A0-3
MRD\ Cmd. MWT\ block Base Base Current Current
addr. counter addr. counter Adr. CS\ amp A4-7
AdrStb AEN RDY CLK Write reg Read reg EOP Data D0-7
amp DRQ0-3 DMA Cmd reg Status reg DACK0-3 request
HOLD arbitra- M a s k re g Temp. reg HLDA tion
Request r Mode reg
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Features of the I8237 DMA controller
can handle up to 4 peripheral devices (it has 4 independent DMA channels)
transfer speed 1,6Mocteţi/s more controllers may be connected in a cascading
mode in order to increase the handled channels the maximum dimension of a transferred block:
64KB it can handle memory to memory transfers More transfer modes:
Single Transfer Block Transfer (burst) Auto-initialized Transfer Memory to memory transfer
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Transfer through I/O processor
When is it used: a higher speed is required the peripheral device is complex (it has a complex
behavior) we want to discharge the main processor form I/O tasks
Implementation: Input/Output processor + Transfer program we use DMA-like mechanisms and interrupts to
synchronize the main and the I/O processors Types of processors used for this purpose:
Specialized I/O processors General purpose processors integrated into an interface
(ex: Z80) Microcontrollers and signal processors (ex: 8048, 8032,
etc.) Processors specialized for a specific peripheral device (e.g.
graphical processor)
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Advantages and drawbacks of the I/O processor-based transfer
Advantages: Higher speed Can be adapted to the behavior of a
complex peripheral device (through a program)
Drawbacks: Hard to implement and test Higher costs Concurrency problems on the system
bus and memory inconsistency
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Comparison between transfer modes
Transfer Complexity Cost Speed Processor Involvement
Through program
Small Small Small total
Through interrupts
Average Average Average Significant
Through DMA High High High Small
Through I/O processor
Very high Very high High Very small
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The serial interface Interface types:
Serial – reduced number of signals (2-3) and a bit-by-bit transfer Parallel – a number of parallel signals (usually 8 for data and some for control);
transfer of data is made in parallel Serial transmission:
A limited number of signals used for the transmission (usually 2 or 3 for a transmission direction)
the transmission is made sequentially bit-by-bit used for long distance transfers used to interconnect a computer with a peripheral device or two or mode computers
Serial transmission types: Based on the synchronization mode:
synchronous serial transmission – the transfer is controlled with a clock signal
Asynchronous serial transmission – no clock signal is used based on the interconnection mode:
point-to-point – connection between two equipments Multi-point – more equipments connected on the same link
based on the direction of the transfer: Unidirectional transfer – only one direction Bidirectional transfer:
Full duplex – 2 independent directions Half duplex – 2 directions, but alternatively
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Synchronous serial transfer
Issue: synchronization between the transmitter and the receiver; when is the optimal time for reading the next bit
Synchronous transfer = the speed of the transfer is controlled with a clock signal
Examples: I2C – serial bus for microcontrollers the keyboard interface of PCs
Advantages: easy implementation, reliable on short distances Drawbacks: extra wire for clock signal, limited transmission
distances
ceas dată 0 1 0 1 1
Synchronous serial transmssion
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Asynchronous serial transfer
no clock signal is used; synchronization is made through the specific structure of the transmitted data
Types: Character-based asynchronous transmission Message-based asynchronous transmission
The communication rules established through a standard protocol
The protocol specifies: Codification of the binary information (e.g. voltage levels,
current levels, light impulses, etc.) The communication environment (twisted or coaxial wires,
optical fibers, radio waves, etc.); topology The structure of the transmitted data The method used for synchronization The method used of error detection The method used for the flow control
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The RS232 (V24) standard
RS232 the best known and most used serial asynchronous transfer standard
Information coding: voltage levels “0” – (+3..+15V) ; usually 12V “1” – (-3..-15V); usually -12V
Communication environment: electric wires (including phone wires)
The structure of the transmitted data:
synchronization: through the first bit, stop bits and frequencies: 300,600, 1200, 2400,… 19200 Bauds
Error detection: parity bit
serial signal idle 5,6,7,8 data bits idle Start 0 Parity 1,2 Stop bits
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The RS232 (V24) standard
The data-flow control: Hardware – through pairs of signals
DSR-DTR – Dataset ready, Data Terminal Ready
RTS-CTS – Request to Send – Clear To Send Software: through special ASCII codes
XON-XOFF – Start/stop transmission Transmission distance: max. 100 m
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The RS232 (V24) standard
Long range transmission through MODEM and phone networks
Signals: TXD – transmission RXD – reception GND – ground DSR – Data Set Ready DTR – Data Terminal ready RTS – Request To send CTS – Clear To sent RI - ring
DTE DCE
MODEM
Phone networkRS232 RS232
Modulated analog signals
calculatorDCE
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The RS232 (V24) standard Transmission modes:
One direction, 2 wires/signals
Bidirectional with software control of data flow (XON –XOFF)
3 wires/signals
Bidirectional with hardware control of data flow (DTR-DSR or CTS-RST)
5-7 wires/signals
E m ite r R e c e iv e r T X D T X D R X D R X D G N D G N D D S R D S R D T R D T R C D C D R T S R T S C T S C T S U n id ir e c ţ io n a l tr a n s fe r
E m ite r R e c e iv e r T X D T X D R X D R X D G N D G N D D S R D S R D T R D T R C D C D R T S R T S C T S C T S
B id ir e c ţ io n a l tr a n s fe r , p r o to c o l X O /X O F F
Emiter Receiver TXD TXD RXD RXD GND GND DSR DSR DTR DTR CD CD RTS RTS CTS CTS
-Bidirectional transfer, protocol DTR-DSR
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Universal Serial Asynchronous Controller (USART) I8251
D0-7 Data Transmission reg TXD
amplifier Transmission ctrl TCLK
RD\ WR\ Control Reception reg. RXD C/D block CS\ Reception ctrl. RCLK
RST CLK MODEM ctrl DTR\,DSR\
RTS\,CTS\
Internal structure of the I8251 serial controller
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Other serial transmission standards: RS485:
Features: digital information coding through differential voltages
(not through voltage levels) twisted pair of wires for bidirectional transmission more devices connected on the same cable – multi-point
transmission used as low level protocol for industrial networks (ex:
Profibus, CAN) Advantages:
longer transmission range (till 1 km) higher noise immunity (because of twisted wires and
differential coding) used mainly in industrial environments
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The RS485 standard
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Other serial transmission standards:
HDLC/SDLC Serial asynchronous transmission on messages used for network transmission More efficient than the character-based
transmission (useful data/total no. of bits ration is better)
Very good error detection mechanism (CRC) Synchronization through PLL (Phase Lock Loop) The structure of the transmitted data:
message
Preambul ControlAdrress Useful Date CRC