1 multi-gigasample data acquisition system using national ultra-high-speed adcs robbie shergill data...

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Multi-Gigasample Data Acquisition System Using

National Ultra-High-Speed ADCs

Robbie ShergillData Conversion Division

2

© 2008 National Semiconductor CorporationConfidential

Objective

• One of the main applications of the Gigasample ADCs is in high-speed data and signal acquisition. A key technical driver of this application is ever higher frequency acquisitions. This class illustrates how National’s Gigasample ADCs can be used in a data/signal acquisition application with an example implementation that is capable of running at sample rates as high as 6 Gs/s.

• The class also describes how to capture the high-speed digital data output – a difficult task for many customers.

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Contents

• Quick review of the Gigasample ADC product offerings

• Interleaving multiple ADC channels to achieve higher sample rates

• An example 6 Gs/s data acquisition signal-path

• Digital data capture issues

4


UHS Product Family At-a-Glance

Generation 1 Generation 2 Generation 3

ADC081000 ADC08D1000ADC08D1500ADC08D500ADC081000ADC081500ADC08500

ADC083000ADC08B3000ADC08D1520*ADC08D1020*

* Expected to be released in January 2008

First Samples: 2003Production: Summer 2004

First Samples: 2004Production: Early 2005

First Samples: Fall ’06 – Winter ‘07Production: 2nd Half of 2007

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Key Features

• All 3rd Generation products have following key features:– Great combination of low-power (sub-2W) and excellent

dynamic performance (7+ ENOB).• Enables many leading-edge signal/data-acquisition systems that

were not possible before– Programmable full-scale range and offset for each channel

• Allows the user to optimize his signal-path design– Very flexible, high-speed LVDS digital interface

• Eases the FPGA data capture task– Provisions for ac-coupled or dc-coupled operation

• Supports both data-acquisition (scope) and communications markets

– High-speed channel synchronization• Necessary for multi-channel applications

6


New, Improved Members of National's Giga-Sample ADC Family - At-A-Glance Refer to the current datasheet for offical spec values. December 15, 2007

Feature ADC08D500/D1000/ D1500

ADC08500/1000/1500

ADC08D1020/1520 (note 1)

ADC083000

ADC08B3000

Number of Channels 1 or 2 (with 'D' designator) 2 (1 in DES mode) 1 1

Sampling Rate per channel (max) 500 / 1000 / 1500 Msps 1000 / 1500 Msps 3000 Msps 3000 Msps

Power Supply 1.8V to 2.0V

Number of Supplies Required 2 (Va and Vdr)

Package 128-pin TQFP w/thermal pad 20mm x 20mm x 1.4mm with 0.5mm pin-pitch

Power Dissipation - TYP 1.4 / 1.6 / 1.8 W - Duals 0.8 / 1.45 / 1.2 W - Singles

1.7 / 1.9 W 1.9 W 1.6 W

ENOB (typ) non-DES [@Fin = 748 MHz] 7.25 @1.5Gs/s 7.25 @1.5Gs/s n/a (Note 2) n/a (Note 2)

ENOB (typ) DES mode [@Fin = 748 MHz] 7.2 @1.5Gs/s 7.1 @1.5Gs/s 7.0 @3.0Gs/s 7.1 @3.0Gs/s

SNR (typ) non-DES [@Fin = 748 MHz] 47 dB @1.5Gs/s 46.5 dB @1.5Gs/s n/a (Note 2) n/a (Note 2)

SNR (typ) DES mode [@Fin = 748 MHz] 45.5 dB @1.5Gs/s 45.5 dB @1.5Gs/s 44.5 dB @3.0Gs/s 45 dB @3.0Gs/s

SFDR (typ) non-DES [@Fin = 748 MHz] 53 dB @1.5Gs/s 56.5 dB @1.5Gs/s n/a (Note 2) n/a (Note 2)

SFDR (typ) DES mode [@Fin = 748 MHz] 53.4 dB @1.5Gs/s 55.5 dB @1.5Gs/s 54.5 dB @3.0Gs/s 54 dB @3.0Gs/s

Full Power Input Bandwidth - non-DES mode (typ) 1.7 GHz 2.0 GHz n/a (Note 2) n/a (Note 2)

Full Power Input Bandwidth - DES mode (typ) 900 MHz 1.3 GHz 3.0 GHz 3.0 GHz

Digital Data Output Interface Parallel LVDS, 1:2 Dmux (Note 3) Parallel LVDS, 1:2 Dmux (Note 3) Parallel LVDS, 1:2 Dmux (Note 3) CMOS, 8- or 16-bit wide

On-chip memory buffer included NO NO NO YES (4K samples)

DCLK optionally active at all times (including during CAL) NO YES YES YES

Test pattern mode NO YES YES YES

1:1 Non-Demux LVDS Output (user option) NO YES YES n/a (CMOS Outputs)

Differential DCLK_RST input with improved setup time (user option) NO YES YES YES

CLK input phase adjust NO YES YES YES

2nd DCLK output in place of OR (user option) NO YES NO n/a (CMOS Outputs)

Improved dynamic performance in DES mode below CLK = ~1 GHz (user option) NO YES YES YES

UHS Product Key Features

NO

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Frequencies of Operation

Input Bandwidth ADC08D1500ADC08D1000ADC08D500

ADC08D1520ADC08D1020

ADC083000ADC08B3000

Non-DES 1.7 GHz 2.0 GHz n/a

DES 900 MHz 1.3 GHz 3.0 GHz

Max Sampling Rate

ADC08D500 ADC08D1000ADC08D1020

ADC08D1500ADC08D1520

ADC083000ADC08B3000

Non-DES(same as the CLK input frequency)

500 Ms/s 1 Gs/s 1.5 Gs/s n/a

DES(twice the CLK input frequency)

1 Gs/s 2 Gs/s 3 Gs/s 3 Gs/s

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Which Chip Should I Use?

• Seems easy: go by the sampling rate requirement; except...

• If Fs=2.5 Gs/s, should I use the ADC083000 or the ADC08D1520 in the DES mode?

• Depends on the input signal frequency (Fin):– With Fin up to 1.3 GHz, use the ADC08D1520 because it’ll give you slightly better dynamic performance;– With Fin higher than 1.3 GHz, you must use the ADC083000.

• Another consideration:– Use the DES mode to get 1:4 demux at the digital data output– Gives half the digital interface speed more ADC cost, but lower FPGA/ASIC cost.

• Example: – Need Fs=1.4 Gs/s Use ADC08D1520 in DES mode (CLK=700MHz) DCLK=175 MHZ instead of 350MHz!

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Achieving Very High Sample Rates

• Go for sheer bandwidth: maximize analog and digital switching speed

– No regard for power bipolar and SiGe processes

– Power efficiency smaller feature size CMOS

• Interleave multiple channels

– Quickest way to higher sample rates

– Brings its own challenges

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Interleaving Concept

• Same signal is processed through parallel channels

• Each channel is sampled by precisely phase-offset versions of a single clock source

• Data from each channel is then ‘interleaved’ into a single data stream

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Interleaving Concept – cont’d

ADC-3

ADC-2

ADC-1

ADC-0

Phase Gen

Data

Interleaver

Data 0,4,8...

Data 1,5,9...

Data 2,6,10...

Data 3,7,11...

Data 0,1,2,3,4,5,6,7,8,9,10,11,12...

Input Signal Data Output

CLK-0deg

CLK-90deg

CLK-180deg

CLK-270deg

[@ F MHz]

[@ 4F MHz]

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Interleaving Challenges

• Channel matching– Analog signal-path from the point of the split to the

sampler must be as well matched as possible– Offset mismatch and gain mismatch must be

minimized

• Timing– The clock edges at each sampler must be at precise

phase intervals– The signal-path delays must be as well matched as

possible– Must have a way to deal with the residual mismatches

in the analog and digital domains

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Effects of Interleaving

• Channel matching– Offset mismatch among the channels causes “offset spurs” in

the frequency spectrum of the interleaved output.– Gain mismatch among the channels causes “image spurs” in

the frequency spectrum of the interleaved output.– DNL mismatches among the ADCs also cause SNR loss.

• Timing– Clock phase error at each sampler also causes “image spurs”

that appear in the frequency spectrum of the interleaved output.

– The signal-path delay mismatches amongst the channels have the same effect as clock phase errors.

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Interleaving Related Spurs

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

Signal

Fs/2Fs/4Fin

Offset Spurs Offset Spurs:@ Fs/2, and@ Fs/4 (4x case only)Caused by Offsetmismatches

Image Spurs

Image Spurs:@ Fs/2 - Fin, and@ Fs/4 +/- Fin (4x case only)Caused by Phase & Gain mismatches

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An 8-bit, 6 Gs/s Signal Acquisition System

ADC08D1520

ADC08D1520

Clk Gen

XilinxVirtex-4FPGA

Power

Signal

Splitter

32

32

CK-90deg CK-0deg

VinA

VinB

SigIn

DataA

DataB

DclkA

DclkB

DataOut(eg, 128bits @ 187.5MHz DDR)

DclkRst

Serial I/F

CK_180 CK_0

Ch_I

Ch_Q

16

16

With the ADCs in the DES mode, an effective 4x interleaving is achieved. CLK signal = 1.5 GHz

Fsample = 6 Gs/s

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Signal Splitter Front-End

0-0 Splitter

Mini-Circuits

AnarenF-03 Balun

Trace matching criticalfrom this point to the ADC

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Clock Phase Generation

33pF

33pF

33pF

33pF

33pF

33pF

0-deg

90-deg

SplitterMini-CircuitsQCN-19+Or similar

Mini-CircuitsT-ADTL2-18+or similar

CLKB

CLKA

Trace matching criticalfrom this point to the ADC

Y1CLKOSC

3.3V

C31uF

C1100pF

C2100nF

R2150

R3 39

R4150

R549.9

C4100nF

R70.22

C6100nF

C810nF

C90.47uF

LD Control input from FPGA

C150100pF

3.3V

C166100nF

SDATASCLK

PLL_LEPLL_CE

R232.2k

R2014.3k

C25100nF

3.0V

3.0V

C17100nF

C184.7uF

R113.3k

C19100nF

C7100pF

R13 *180

C16100pF

3.0V

C10100pF

3.0V

C110.47uF

R80.22

R912K

R101k

C120.15uF

C13220pF

123456789

272625242322212019373839

10 11 12 13 14 15 16 17 18

36 35 34 33 32 31 30 29 28

U3LMX2531LQ1500E

R12 *180

R15 *30

Crystek# CCHD-950-25-60

60 MHz

5dB Pad

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Channel Synchronization Problem

CLK

DCLK-A

DCLK-B

DataA1/A2

DataB1/B2

Fig. 2a – Two devices’ outputs out of synchronization

Sample N-14 & N-13 Sample N-12 & N-11


N N+1 N+2

DCLK-B

DataB1/B2

Fig. 2b – Two devices’ outputs in synchronization


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DCLK_Rst Timing

CLK+

DCLK

Data

DCLK_RST

Assertion Region - asynchronous SAFE Region #3 – synchronous w.r.t. rising edge #3 of CLK+

Trh

Trs

Tod

#3#2#1 #4 (First Synchronized Edge)

Reset Synchronizing Edge

• The reset signal must be captured by the same edge on both ADCs inorder for them to be synchronized with each other.

ADC08D1020/1520: Trs = 90psec, Trh = 30psec;@ CLK=1.5GHz, Safe Region Window = 447psec

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DCLK_Rst Generation• The FPGA must synchronize the two ADCs once upon power-up and upon coming out of power-down mode. This circuit makes the FPGA reset signal synchronous with the ADC’s CLK input.

D Q

Div. 2

D Q

ADC ASIC/FPGA

DQDQDQ

2

2

Matched Delays

CLK+/- DCLK_RST

DCLK

Data

Reset

SYS_CLK

Synch

FF1FF2FF3

SET

LevelTranslation

To the other ADC through another, matched FF3 + Level Translation circuit

BUF1

[MC10EP51][MC10EP52]

[MC10EP11]

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PECL to LVDS Translation

• High-speed logic used here is +3.3V PECL while our Gig ADC’s • DCLK_RST input is LVDS.• This circuit does the requisite level-translation.

3.3V

1.9V

LVPECL Zo = 50 ohms

Zo = 50 ohms

100 ohms

ADCDiff.Rx

R1

R2

R1

R2

Voh-max = 2.54VVol-min = 1.365V

Vdiff = 1.6Vp-p nom.

Vdiff = 0.6Vp-p nom.Vcm = 1.2V nom.

R1 = 54 ohmsR2 = 105 ohms

D-FF ADC08D1020/1520

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Timing Skews in the ADCs

• Two timing delays within the ADC can cause channel- to-channel skew due to their chip-to-chip variation:

– Tad (Aperture Delay)– Tod (CLK input to Data output delay)

D QData

SamplerVin

CLK

Td1

Td2Td3

TodTad = Td2 – Td1

Tad is typically 1.6 nsec, but can vary from 1.35 nsec to 1.85 nsec in a system*Tod is typically 4.0 nsec, but can vary from 3.0 nsec to 5.0 nsec in a system*

{ * These spec limits are not guaranteed in the datasheet }

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Board Level Timing Skews

• Following are the main sources of timing skews at the board level:

– Imbalances in the analog front-end components and signal routing.– Imbalances in the multi-phase clock components and routing,– Imbalances in the digital data and clock routing from the ADCs to the FPGA.– Digital data and clock routing imbalances inside the FPGA

ADC08D1520

ADC08D1520

Clk Gen

XilinxVirtex-4FPGA

Power

Signal

Splitter

32

32

CK-90deg CK-0deg

VinA

VinB

SigIn

DataA

DataB

DclkA

DclkB


DclkRst

Serial I/F

ADC08D1520

ADC08D1520

Clk Gen

XilinxVirtex-4FPGA

Power

Signal

Splitter

32

32

CK-90deg CK-0deg

VinA

VinB

SigIn

DataA

DataB

DclkA

DclkB


DclkRst

Serial I/F

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Dealing with the mismatches

• The Gigasample ADCs help the user correct for all three types of mismatches in an interleaved system:– The offset of each channel can be corrected with the

Offset Registers provided on the ADC*.

– The gain of each channel can also be adjusted with the Full-Scale Voltage Adjust register on each ADC*.

– The timing mismatches can be reduced by using the Clock Phase Adjust feature of the ADCs.

[ * Gain and Offset can, and should, also be adjusted in the front-end].

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ADC Clock Phase Adjustment

• The latest Gigasample ADCs (ADC08D1020/1520, ADC08x3000) provide a means to adjust the clock input’s phase:

– Achieved by the user adding fixed delay through control register programming.

– Intended to correct small residual timing imbalances between channels after the user has done as careful a board design as possible.

D QData

SamplerVin

CLK

Td1

Td2Td3

TdpaCoarse/Intermediate Phase Adjust

Fine Phase Adjust

Serial Interface

Control Registers

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Clock Phase Adjust - Details

Coarse and Intermediate Clock Phase Adjust

0

500

1000

1500

2000

2500

3000

D14 - D10 - D7 ( Register 1111)

Adj

ust r

ange

in P

s

Series1

• Two registers provide Coarse (~72ps/step), Intermediate (~11ps/step) and Fine (~0.4ps/step) control over the added delay.

• Delay values are approximate, are specified nominally, and are not guaranteed

• Actual added delay is monotonic but not linear across the full range.

Fine Adjust Range

540

550

560

570580

590

600

610

00000000 00001111 00011111 00111111 01111111 11111111

D15 - D8 Register 1110

Adju

st R

ange

pS

Series1

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Clock Phase Adjust - Caution

• Max programmable delay is ~2.3 nsec.• However, ANY amount of delay added to the clock

signal path inside the chip causes a finite amount of SNR/SFDR degradation also.

• Amount of degradation is a function of the amount of delay.

• For small amount of phase adjustments the net benefit is definitely positive; but beyond some level it will not be so.

• Therefore, system design process should quantitatively trade-off the benefit of this feature versus its cost to determine the optimal amount of phase adjustment.

28


Effects of Added Clock Delay - 1

4547495153555759616365

0 20 40 60 80 100 120 140 160 180 200 220 240 260 280

Fine Clock Phase Register 1110

SF

DR

Code 0 represents NO clock phase adjust

Fs = 1.0 Gs/s

Fin = 497 MHz

Fin = 947 MHz

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6.5

7

7.5

8

0 20 40 60 80 100 120 140 160 180 200 220 240 260

Fine Clock Phase Register 1110

EN

OB



Fs = 1.0 Gs/s

Fin = 497 MHz

Fin = 947 MHz

30


45

47

49

51

53

55

57

59

61

0 20 40 60 80 100 120 140 160 180 200 220 240 260 280Coarse and Intermediate Clock Phase

Register 1111 D7 -D14

SF

DR



Fs = 1.0 Gs/s

Fin = 497 MHz

Fin = 947 MHz

31


5.5

6

6.5

7

7.5

8

0 20 40 60 80 100 120 140 160 180 200 220 240 260Coarse and Intermediate Clock Phase

Register 1111 D7 -D14

EN

OB



Fs = 1.0 Gs/s

Fin = 497 MHz

Fin = 947 MHz

Up to ~300psec of delay can be added without excessive amount of degradation.

32


Data Interleaving & Alignment

ADC08D1520

ADC08D152032

32VinA

VinB

DataA

DataB

DclkA

DclkB

DataOut

64

Register& Demux

ClockDeskew

DataDeskew

FIFO

DeskewLogic

64

ClockDeskew

DataDeskew

FIFO

128

DataReassembly

128

Earliest Sample

Latest Sample

WCK RCK

WCK

RCK

CLKOut

FPGA

Register& Demux

Serial Interface

Channel Control: Test pattern enable CLK phase adjustment

33


Deskewing with Test Patterns

• The “digital domain” skew between the channels can add-up to more than one DCLK cycle.

• This type of skew can be removed in the FPGA by using the test patterns that the Gig ADCs offer:

– Put the ADCs into Test Pattern mode– Capture the data from each channel into separate FIFOs –each with

that particular channels’ DCLK.– Compare the data output from the FIFOs with each other.– Delay one of the FIFO read clocks until the data match.– The channels are now digitally aligned.– Put the ADCs into normal operation mode.

• Same digital technique can be used in the FPGA for skew from the front-end, but system level analog signal injection is required.

34


ADC083Kx2-RB Reference Board

35


Initial Rev. A Performance

Fs/4 +/- FinFs/2 - Fin

36


Capturing the Digital Data Output

• Device provides a built-in ‘Demux-by-2’ function at the output of each ADC for the purpose of slowing down the data frequency.

• All products have 32 data signals with a source-synchronous clock (DCLK).

• In the DES mode since the two ADCs act as one, there is an effective Demux-by-2 occurring.

• Regardless, there is always* the following relationship between the Sampling Clock input (CLK) and the DCLK output:

Fdclk = Fclk / 2 in SDR mode (in MHz)

Fdclk = Fclk / 4 in DDR mode (in

MHz)

* See next slide

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Except...The Non-Demux Mode!

• On the ADC08D1020 and ADC08D1520 devices we have added a Non-Demux mode of operation

• This is intended for those customers that use advance technology ASICs with digital LVDS I/O that can operate at rates in excess of 1.0Gbps

• Benefit is half as many data lines.• In the Non-Demux (1:1) mode, there is the following

relationship between the Sampling Clock input (CLK) and the DCLK output:

Fdclk = Fclk in SDR mode (in MHz)

Fdclk = Fclk / 2 in DDR mode (in

MHz)

38


Digital Output Timing – DDR Mode

• In Normal Mode, pin 4 floating or ½ supply voltage• In Extended Control Mode, program Configuration Register

nDE bit

DCLK

DATA

Sampling CLK

Latching Edges

DDR 90-degree mode shown. This requires the use of Extended Control Mode

Tod

Tosu Toh

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Digital Output Timing – SDR Mode

• In Normal Mode, Pin 4 is not floating or ½ supply voltage

• In Extended Control Mode, program Configuration Register nDE bit

DCLK

DATA

INPUT CLK

Data may be captured with the rising edges...

... But the timing is specified as a skew time between the

falling edge of DCLK and the Data transition time.

40


Digital Output Timing – Non-Demux Mode (DDR)

• Example: 2.5Gs/s ADC operation– Chip Mode: DES, Non-Demux, DDR– Fclkin = 1.25GHz, Fsample = 2.5 Gs/s, Fdclk = 612.5 MHz– Output Data Rate = 2.5 GByte/s– Output Data Bus Width = 16 bits (LVDS differential pairs)– Output Data Bit Rate = 1.25 Gbps– Output Data Line Frequency = 612.5 MHz

41


Digital Data Output - Electricals

• Differential LVDS• NOT ANSI/IEEE spec compliant because of 1.9V supply• However, Vod and Vos are designed to work reliably with

typical ASIC and FPGA receivers in chip-to-chip connections (eg, up to 8” board traces)

Vod = 280 – 720 (510 typ) mVp-p-or-400 – 920 (710 typ) mVp-p

Vos (common-mode)Vos = 0.8V or 1.2V

Vdd = 1.9V (typ)

Vdd = 2.5V (typ)

Vidiff =200 – 1200mVp-p

CM Range =0.3 to 2.2 Volts

ADC Output FPGA Input

42


Digital Data Capture

• Difficult at these frequencies and bus-widths

• Additional distortion and data-to-clock skews caused by board layout– 24 Gbps total throughput 750 Mbps per signal– 1.333 nsec theoretical-best data bit window at transmit– ~210 psec lost to: fixed skew, distortion and jitter

• ADC’s typical output setup/hold specs:– @ 1Gs/s [2Gs/s in DES]: Tsu = 825ps, Th = 965ps– @ 1.5Gs/s [3Gs/s in DES]: Tsu = 570ps, Th = 555ps

• Further skews inside the FPGA before latching occurs

43


Digital Data Capture - 2

• Barely enough capture window remains at the latching flop; but the accumulated data-to-clock skew becomes intolerable!

Tsu Th

TsuTh

ADC Output:Total Available Data Window = 570 + 555 = 1125 ps

FPGA Input:Minimum Required Data Window = 930 ps

44


Digital Data Capture - Deskewing

• Performance FPGAs of today, as well as the Price/Performance FPGAs provide DLL circuits for deskewing the clock with respect to the data bus.

45


Data-DCLK Deskewing Method

1. Put the ADC in Test Pattern mode.

2. Set the DCM’s clock offset to 0.

3. Capture enough data and compare to the expected pattern.

4. If correct, change the clock offset to the next positive-

direction value.

5. Repeat steps 3-4 until at least one byte mismatches.

6. Set the clock offset to the next step from 0 in the negative

direction.

7. Capture enough data and compare to the expected pattern.

8. If correct, change the clock offset to the next positive-

direction value.

9. Repeat steps 7-8 until at least one byte mis-matches.

10. Determine the range of clock offsets that worked

11. Set the DCM’s clock offset to the middle of the range.

46


DCS BigGig FPGA Architecture

FIFO_0

FIFO_1

FIFO_7

HDCLK=DCLK/2

CAPTURE

1:2

DEMUX

Freq. Msrmt.

AcquisitionControl

uC Interface& Registers

Control & Status

DCMDCLK_p

ADC_DATA

DCLK

CLK100

ADR, DATA, CTL

(to uC)

Serial Interface

ControlControl

To ADC

32 64

Total=128

16

16

16

FPGA

DCMCLK100

(100MHz)

OSCADC_DCLK

RENWEN

MUX

16

LVDS Interface& Datapath

47

Appendix

48


ADC08D1520 Test Pattern

50


The ADC083000 and the ADC08B3000 differ from each other in the following way:

A. B. C. D. E.

20% 20% 20%20%20%

1010

Multi-Gigasample Data Acquisition System Using National Ultra-High-Speed ADCs

A. The ADC08B3000 offers higher bandwidth

B. The ADC083000 can operate at a higher sample rate

C. The ADC08B3000 includes an on-board buffer

D. The ADC083000 can run at 3 Gsamples/second

E. The ADC08B3000 is the “better” of the two converters.

51


A. They enhance the full-power bandwidth over the previous generation

B. They have much better SNR performance than the previous generation

C. The DCLK does not have to stop on the new generation devices when they enter the calibration cycle

D. They have test patterns

Which of the following is NOT true about the latest generation of the Gigasample converters

A. B. C. D.

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52


A. You are working with input signal frequencies greater than 1.3 GHz and you will not settle for lower dynamic performance

B. You need lower power C. You need higher SFDR

performance than what the ADC08D1520 can provide

D. You are going to design an interleaved system and must have the clock phase adjust feature

The only reason you must use the ADC083000 over the ADC08D1520 is when:

A. B. C. D.

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53


A. They are always lower magnitude than image spurs

B. Offset mismatches just don’t occur as much in typical systems

C. As number of channels goes up, the amount of offset error between them goes down

D. They are in well-known, fixed locations with respect to the sampling frequency

Offset spurs are easier to deal with than image spurs because:

A. B. C. D.

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54


A. The clock frequency is so highB. The reset signal comes from a

different clock domain so it is asynchronous with the ADC’s clock

C. The reset signal is PECL while the ADC’s input is LVDS

D. All of the above

The reason it is so difficult to synchronize multiple channels in the design example shown in this class is because :

A. B. C. D.

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1010


55


A. Running at higher clock frequencies

B. Reducing the image spurs caused by timing mismatches in the clocking network of an interleaved system

C. Achieving much better linearity performance in interleaved systems

D. All of the above

The clock phase adjust feature of the latest family of Gigasample ADCs is useful for :

A. B. C. D.

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1010


56


A. Deskewing the DCLK in relation to the data outputs so reliable captures can occur

B. Aligning the channels in multiple-channel systems

C. Early digital backend development and system debug

D. All of the above

The test patterns of the Gigasample ADC family are useful for :

A. B. C. D.

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57


A. Data and DCLK frequency is reduced so its easier to capture very high speed data

B. More data linesC. It is easier for ADC designer

to generate a DCLK in DDR mode

D. None of the above

The benefit of the Demux function and the DDR output mode is :

A. B. C. D.

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58


A. The differential voltage does not meet the minimum Vod spec of the standard

B. The common mode voltage is not specified for the minimum LVDS standard spec

C. The rise and fall times are shorter than the minimum required by the standard

D. All of the above

The LVDS output of the ADC08D1520 is not exactly ANSI/IEEE spec compliant because :

A. B. C. D.

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The DCM in the Xilinx FPGA is useful for :

A. B. C. D.

25% 25%25%25%

1010


A. Working with test patternsB. Adjusting the DCLK timing

so reliable data captures can occur

C. Adjusting the LVDS signal’s differential voltage

D. Reducing the image spurs

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1 multi-gigasample data acquisition system using national ultra-high-speed adcs robbie shergill data...

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