1

New England Lead Free Electronics Consortium

Greg Morose

Toxics Use Reduction Institute

University of Massachusetts Lowell

PbPbPbPbPbPb

2

Agenda

• Consortium Overview

• Phase III Process

• Phase III Results and Conclusions

• Next Steps

3

Lead-free Electronics Challenges

2. What process modifications?

4. Which board finishes?

3. Which component finishes?

1. Which lead-free solders?

4

New England Lead-free Electronics Consortium

Government Academia

Industry

Pull testingStatistical analysis

FundingProject Mngmt.Outreach

ComponentsEquipmentTechnical expertise

5

Consortium: Previous Work

Phase I: 2001-2002– 66 test vehicles– Type 1: 4” x 5.5” FR-4 board, single layer, single

sided, SMT only (Assembly Class B)

PbPbPbPbPbPb

6

Phase I – Parameters• Solder Alloys

• Sn/Ag/Cu(95.5/3.8/0.7)

• Sn/Ag (96.5/3.5)• Sn/Bi (57/43)

• PWB Surface Finishes • OSP (Organic Solder Protectants)

• Electroless Nickel Immersion Gold (ENIG)

• Thermal Profiles • Soak with 60sec, 90sec, 120sec above liquidus

• Linear with 60sec, 90sec, 120sec above liquidus temp.

• Reflow Environment • Nitrogen vs. Air reflow

7

Consortium: Previous Work

Phase II: 2002-2004– 100 test vehicles– Type 1: 6” x 9” board, single layer, single sided,

SMT only (Assembly Class B)

8

Phase II – Parameters1. PWB Finishes – Solder Mask Over Bare Copper with Hot

Air Solder Leveling (SMOBC/HASL), Matte Tin (Sn), Immersion Silver (Ag), Organic Solder Preservative (OSP), and Electroless Nickel Immersion Gold (ENIG).

2. Reflow Atmospheres – Two Treatments – Air and Nitrogen.

3. Solder Pastes – 95.5Sn-3.8 Ag-0.7Cu alloy from three different suppliers (A, B and C), all incorporating no-clean fluxes.

4. Component Lead Finishes – matte tin, tin/silver/copper, nickel/palladium/gold, and nickel/gold.

Sn-Pb eutectic solder PWB using the solder treatments as control PWBs.

9

Phase III

• Implementation not experimentation, test vehicle simulates production board

• Focus on solder joint integrity

• Funding: U.S. EPA

10

Problem Solving Approach

Our Outputs (Y’s) are determined by our Inputs (X’s). If we know enough about our X’s we can accurately predict Y.

Y1: Defects per unit (attribute data)Y2: Solder joint pull strength (continuous data)

By

Solder joint integrity = (reflow profile, solder paste, print speed, surface finish, component finish, laminate material, etc.)

))xx,...,,...,xx,,xx,,f(xf(x==YYkk332211

11

Critical Inputs

Alloys: Multiple

Atmosphere: air, nitrogen

Solder supplier: Multiple

Thermal profile: soak, ramp/peak

Laminate material: Multiple

Surface finish: Multiple

SAC 305

Air

Ramp/peak

2 suppliers

2 laminates

3 finishes

12

Design Manufacturing

ReliabilityTesting Board fab

Visual testing

Components

Solder Paste

ProcessEquipment

New England Lead-free Consortium – Phase III

13

Phase III Process

14

Phase III Test Vehicle

Board Quantity: 40

Board Layers: 20

Board Thickness: 0.110”

Board Size: 16” x 18”

Laminate Materials:

Supplier ASupplier B

15

Phase III ComponentsComponent Types:

Component Lead Finishes:

SMT (Qty: 1,713): BGAs, uBGAs, SOICs, resistors, capacitors, QFPs, etc.

THT (Qty: 53): Connectors, resistors, relays, inductors, etc.

• SnPb• NiPdAu • Sn• Au• PdAg• SnCu

• matte Sn • NiAu • SnNi• SnAgCu• SnBi

16

Phase III Parameters

• Electroless nickel immersion gold (ENIG)• Immersion Silver• Organic solder protectants (OSP)

Surface Finishes:

Solder paste:

Lead free SAC 305 no clean (Supplier A, Supplier B)

Tin/Lead (Supplier A, Supplier B)

17

Phase III StencilMaterial: Stainless steel laser cut and electropolished

Thickness: 6 mils (step down to 5 mils for uBGAs)

Top Stencil Apertures:

For leaded devices – 10% expansion in length for both directions and a 1 to 1 ratio for widthFor fine pitch devices – based on pad sizeFor discretes – 10% increase in length on termination side only, and a 1 to 1 ratio for width

10% standard reduction

Bottom Stencil Apertures::

Aperture Styles:For discretes – radial aperture, home plate, kings crown, and standard

18

DOE 1 – Lead-free Boards

Board Solder Paste Surface Finish PWB Laminate Components Testing

1 LF - A ENIG Laminate - A SMT, THT HALT

2 LF - A ENIG Laminate - A SMT TC

3 LF - A ENIG Laminate - B SMT, THT TC

4 LF - A ENIG Laminate - B SMT HALT

5 LF - A Imm. Ag Laminate - A SMT, THT HALT

6 LF - A Imm. Ag Laminate - A SMT TC

7 LF - A Imm. Ag Laminate - B SMT, THT TC

8 LF - A Imm. Ag Laminate - B SMT HALT

9 LF - A OSP Laminate - A SMT, THT HALT

10 LF - A OSP Laminate - A SMT TC

11 LF - A OSP Laminate - B SMT, THT TC

12 LF - A OSP Laminate - B SMT HALT

19

DOE 1 – Lead-free Boards

Board Solder Paste Surface Finish PWB Laminate Components Testing

13 LF - B ENIG Laminate - A SMT, THT HALT

14 LF - B ENIG Laminate - A SMT TC

15 LF - B ENIG Laminate - B SMT, THT TC

16 LF - B ENIG Laminate - B SMT HALT

17 LF - B Imm. Ag Laminate - A SMT, THT HALT

18 LF - B Imm. Ag Laminate - A SMT TC

19 LF - B Imm. Ag Laminate - B SMT, THT TC

20 LF - B Imm. Ag Laminate - B SMT HALT

21 LF - B OSP Laminate - A SMT, THT HALT

22 LF - B OSP Laminate - A SMT TC

23 LF - B OSP Laminate - B SMT, THT TC

24 LF - B OSP Laminate - B SMT HALT

20

DOE 2 – Tin/Lead Boards

Board Solder Paste Surface Finish PWB Laminate Components Testing

25 SnPb - A ENIG Laminate - B SMT, THT HALT

26 SnPb - A ENIG Laminate - B SMT TC

27 SnPb - B ENIG Laminate - B SMT, THT TC

28 SnPb - B ENIG Laminate - B SMT HALT

29 SnPb - A Imm. Ag Laminate - B SMT, THT HALT

30 SnPb - A Imm. Ag Laminate - B SMT TC

31 SnPb - B Imm. Ag Laminate - B SMT, THT HALT

32 SnPb - B Imm. Ag Laminate - B SMT TC

33 SnPb - A OSP Laminate - B SMT HALT

34 SnPb - A OSP Laminate - B SMT, THT TC

35 SnPb - B OSP Laminate - B SMT HALT

36 SnPb - B OSP Laminate - B SMT, THT TC

21

Phase III Overall Process PbPbPbPbPbPb

AOI, Visual, and X-Ray Inspection

Pull & Shear Test

AssemblyBoard Design

Thermal Cycling &HALT

Board Fabrication, IST

22

IST Preconditioning Profile (260 C)IST TEMPERATURE PROFILE @260 C

POWER & SENSE CIRCUIT (.040" Grid Test Vehicles)

0102030405060708090

100110120130140150160170180190200210220230240250260270

1 11 20 29 38 48 57 66 75 84 93 102

111

120

129

138

147

156

165

174 1 13 25 37 49 61 73 85 97 109

CYCLE TIME IN SECONDS

TE

MP

ER

AT

UR

E C

HA

NG

E I

N D

EG

RE

ES

C

Power

Sense

6 test coupons: 3 Thermal Excursions6 test coupons: 6 Thermal Excursions

Location:Dynamic Details Inc.Sterling, Virginia

23

IST Temperature Profile (150 C)

IST TEMPERATURE PROFILE @150 CPOWER & SENSE CIRCUIT (.040" Grid Test Vehicles)

0

10

20

30

40

50

60

70

80

90

100

110

120

130

140

150

160

1 16 28 41 54 67 79 92 105 117 130 143 155 168 181 9 22 35 47 60 73 85

CYCLE TIME IN SECONDS

TE

MP

ER

AT

UR

E C

HA

NG

E I

N D

EG

RE

ES

C

Power

Sense

24

Assembly Process

Universal PlacementMachine 4791 HSP

Universal PlacementMachine GSM

Vitronics Soltec XPM 1030

DEK Horizon 265 Screen Printer

Omron Inspection System

Premier Rework RW116

25

Printing Process

Blades: 19 inch stainless steel, 9 mils

Separation Speed: 0.047 inches/second for all boards

Blade pressure: 30 lbs for all boards

Print Speed:

Lead Boards: 0.8 inches/second for all boards

Lead-free Boards: 2.0 inches/second for first five boards (bottom only), 1.5 inches/second for all remaining boards

26

Placement Process

Universal PlacementMachine 4791 HSP: High speed placement of discretes (resistors and capacitors)

Universal PlacementMachine GSM:Placement of other SMT components (SOIC, BGA, uBGA, QFP, etc.)

27

Reflow Process

Reflow Oven: Vitronics Soltec XPM 1030

Reflow Atmosphere: Air only

Software: Datapaq

Heating Zones: 10

Cooling Zones: 3

Line Speed: 25.0 in/min

Profile: Ramp to Peak

28

Reflow Process

Target Maximum Temperature:

Target TAL:

Lead: 208 – 218 degrees C

Lead-free: 240 – 248 degrees C

Lead: 60 – 90 seconds

Lead-free: 60 – 90 seconds

29

THT Process

Tape Flux Insert Preheat SolderChange Nozzle

Tape

FluxInsertPreheatSolderChange nozzle

30

THT ProcessParameter Lead Boards Lead-free Boards

Alloy Tin/Lead SAC 305

Flux Alpha 3215 Alpha 3215

Preheat Temperature 110 degrees C 110 degrees C

Solder pot temperature

260 degrees C 280 degrees C

Dwell time 12 seconds 12 – 20 seconds

31

Visual Inspection

Location: Hudson, NH, Benchmark Electronics

Method:

• Seven experienced and trained inspectors

• Review AOI Results for false/true calls

• Magnification: 10x

• Standard: IPC 610D, Class 2

• Identify defects/process indicators

32

Thermal Cycling

Cycle Time:Approx. 40 minutes per cycle - Ramp rate: 10 degrees C per minute - 10 minute dwell time at 0 C - 10 minute dwell time at 100 C

Equipment:Thermotron F125 CHV37-30

Method:Meet the requirements of IPC-9701, test condition TC12,000 Cycles

Location: Andover, MA, Raytheon

33

Thermal Cycling

                       

                       

                       

                       

                       

                       

                       

                       

                       

                       

                       

                       

                       

                       

Time

T (max) = 100 C

T (min) = 0 C

Upper dwell time = 10 minutes

Lower dwell time = 10 minutes

Tem

per

atu

re

Ramp rate = 10 C/ minute

34

Highly Accelerated Life Testing (HALT)

Location: North Reading, MA, Teradyne

Method:

Equipment: Qualmark HALT/HASS System

Temperature Cycling: -60 degrees C to 160 degrees CVibration: Static to 80 GrmsDynamic measurement of resistance: 17 daisy chainsSingle test cycle: 206 minutes

35

HALT Profile

-100

-50

0

50

100

150

200

0 20 40 60 80 100 120 140 160 180 200 220

Run Time (minutes)

Te

mp

era

ture

(C

)

0

10

20

30

40

50

60

70

80

90

Vib

rati

on

(G

rms

)

Chamber Temp.

Table Vib.

Turi HALT Profile

36

Pull Testing

Location: Lowell, MA, University of Massachusetts

Method:

Equipment:Instron pull test machine

45 degree angle to get vertical and shear stressPull rate of 0.1” per minute, record the peak pull force

37

Pull Testing

38

Results & Conclusions

39

IST Results

Material Finish Precondition Cycles

P/F Cycle FailureOccurred

No. Of ISTCycles

A ENIG 3x P   500

A OSP 3x F Cycle 3  

A Ag 3x P   500

A ENIG 6x F Cycle 5  

A OSP 6x F Cycle 5  

A Ag 6x P   500

B ENIG 3x P   500

B OSP 3x P   29

B Ag 3x P   500

B ENIG 6x P   500

B OSP 6x F Cycle 1  

B Ag 6x P   500

40

Visual InspectionDescription Tin/Lead

PWBsLead-free

PWBs209: Bent pin Y Y

261: Tombstone Y Y

602: Solder bridge Y Y

615/616: Non-wetting Y Y

626: Disturbed solder Y Y

713: Foreign matter Y Y

606: Pinholes, blowholes Y Y

613: Insufficient solder Y Y

672: Solder balls Y Y

205: Misregistration Y Y

270: Raised part Y Y

603: Solder splatter Y Y

612: Excess solder Y Y

620: Unsoldered lead Y

701: Delamination Y

770: Damaged pad Y Y

41

Total ComponentsComponents

Per BoardLead-free (24

Boards)Tin/Lead

(12 Boards) Totals

SMT 1,713 41,112 20,556 61,668

THT 53 636 318 954

1,766 41,748 20,874 62,622

Lead-free 24 Boards

(x2 inspections)

Tin/Lead 12 Boards

(x2 inspections) Totals

SMT 377 349 726

THT 246 21 267

Totals 623 370 993

Total Defects

42

Defects Per Unit (Board)Lead-free

(24 Boards)Tin/Lead

(12 Boards) Totals

SMT 7.8 14.5 10.1

THT 10.2 1.7 7.4

Lead-free (24 Boards)

Tin/Lead (12 Boards) Totals

SMT 0.005 0.008 0.006

THT 0.193 0.033 0.144

Defects Per Unit (Component)

43

Visual Inspection Summary

DOE 1 - Lead-free Boards:

• For THT components, there is no statistical difference for solder paste supplier, surface finish, or laminate material supplier.

• For SMT components, there is borderline statistical difference for solder paste supplier and laminate supplier. There is no statistical difference for surface finish.

• There is a statistical difference for the interaction of solder paste supplier and laminate material supplier for SMT components.

Best SMT Combination: Laminate “Z”, ENIG, either paste

44

Visual Inspection Summary

DOE 2 - Tin/Lead Boards:

There is no statistical difference for solder paste supplier, surface finish, or interaction effects for SMT or THT components. (Probability is > 0.05 for all of these factors)

45

Lead-free vs. Tin/LeadSMT Defects

Mean: 7.9 Mean: 14.5

No statistical difference for SMT component defects (P > 0.05)Data

SMT Defects LeadedSMT Defects Lead-free

30

25

20

15

10

5

0

Interval Plot of SMT Defects Lead-free, SMT Defects Leaded95% CI for the Mean

46

Lead-free vs. Tin/LeadTHT Defects

Mean: 10.2 Mean: 1.7

Statistical Difference, Lead-free has more THT defects (P < 0.05)Data

THT Defects LeadedTHT Defects Lead-free

14

12

10

8

6

4

2

0

Interval Plot of THT Defects Lead-free, THT Defects Leaded95% CI for the Mean

47

Component Finish - SMT

Component Finish

Component Type

Number of Components

Defect Rate (Lead-free

solder paste)

Defect Rate (Tin/Lead solder

paste)

Tin/copper SMT 144 0% 0%

Tin/bismuth SMT 432 0.3% 0%

Tin SMT 59,076 0.3% 0.8%

Gold SMT 108 1.4% 0%

Tin/lead SMT 468 2.1% 0%

Nickel/palladium/gold SMT 612 3.1% 1.0%

Matte tin SMT 324 5.1% 8.3%

Nickel/gold SMT 240 9.1% 18.7%

Tin/silver/copper SMT 168 13.5% 4.2%

Palladium/silver SMT 36 16.7% 0%

48

Component Finish - THT

Component Finish

Component Type

Number of Components

Defect Rate (Lead-free

solder paste)

Defect Rate (Tin/Lead solder

paste)

Tin THT 576 15.1% 1.8%

Other lead-free THT 198 15.5% 2.3%

Tin/copper THT 54 17.4% 5.6%

Nickel/palladium/gold THT 36 20.8% 0%

Tin/nickel THT 90 46.7% 15%

49

Pull Testing ResultsM

ean o

f Pull

Forc

e

Supplier BSupplier A

8.5

8.0

7.5

7.0

6.5

OSPIm AgENIG Supplier BSupplier A

Sn/BISn

8.5

8.0

7.5

7.0

6.5

BackFront

Solder Supplier Laminate Finish Laminate type

Lead Finish Pull Direction

Main Effects Plot (data means) for Pull Force

Lead-free DOE

No statistical difference for solder paste supplier, board finish, or laminate

There is a statistical difference for lead finish/SOIC and pull direction.

50

Pull Testing Results

Lead-free versus Tin/Lead Results

Source ProbabilitySolder Paste (TL/LF) 0.76

No statistical difference for solder paste type (lead-free or tin/lead), Probability > 0.05

Lead-free: 7.61Tin/Lead: 7.53

Mean

51

Conclusions

• With careful selection of materials, lead-free electronics assembly is possible with equal or fewer defects than tin/lead assembly for SMT components

• Further process optimization is required for THT component assembly

• After thermal cycling, solder joint strength for lead-free electronics assembly is comparable to tin/lead assembly

52

Next Steps

Further inspection and X-ray of HALT boards

Electrical testing of certain components

Further testing and optimization for THT componentsVitronics selective solder machine, Phase III boards & components,Dwell time, solder pot temperature, flux, etc.

Develop a Failure Modes and Effect Analysis (FMEA)Potential failure modes, severity of effect, probability of occurrence, detection capability, and recommended mitigation actions

53

Multiwave Technology

54

Select Wave Technology

55

FMEA Overview

Process Step/Input

Potential Failure Mode Potential Failure EffectsSEV

Potential CausesOCC

Current ControlsDET

RPN

Actions Recommended

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

What is the Input

What What can go can go wrong wrong

with the with the Input?Input?

What can What can be done?be done?

What is What is the Effect the Effect

on the on the Outputs?Outputs?

What are What are the the

Causes?Causes?

How can How can these be these be found or found or

prevented?prevented?

How How Bad?Bad?

How How Often?Often?

How How well?well?

56

Risk Priority Number

• Severity (of Effect)- importance of effect on customer requirements, safety or other risks of failure occurring (1=Not Severe, 10=Very Severe)

• Occurrence (of Cause)- frequency with which a given cause or failure occurs (1=Not Likely, 10=Very Likely)

• Detection (capability of Current Controls) - ability of current control system to detect or prevent causes or failures (1=Likely to Detect, 10=Never able to Detect)

EffectsEffects CausesCauses ControlsControls

RPN = Severity X Occurrence X Detection

57

Consortium Information

For further information about the consortium, please contact:

Greg MoroseToxics Use Reduction Institute

(978) 934-2954Gregory_Morose@uml.edu

http://www.turi.org/content/content/view/full/339/

Or visit our website: